aarch64: Add support for +mops

This patch adds support for FEAT_MOPS, an Armv8.8-A extension
that provides memcpy and memset acceleration instructions.

I took the perhaps controversial decision to generate the individual
instruction forms using macros rather than list them out individually.
This becomes useful with a follow-on patch to check that code follows
the correct P/M/E sequence.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en]

include/
	* opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro.
	(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS.
	(AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd.
	(AARCH64_OPND_MOPS_ADDR_Rs): Likewise.
	(AARCH64_OPND_MOPS_WB_Rn): Likewise.

opcodes/
	* aarch64-asm.h (ins_x0_to_x30): New inserter.
	* aarch64-asm.c (aarch64_ins_x0_to_x30): New function.
	* aarch64-dis.h (ext_x0_to_x30): New extractor.
	* aarch64-dis.c (aarch64_ext_x0_to_x30): New function.
	* aarch64-tbl.h (aarch64_feature_mops): New feature set.
	(aarch64_feature_mops_memtag): Likewise.
	(MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN)
	(MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN)
	(MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN)
	(MOPS_SET_INSN): New macros.
	(aarch64_opcode_table): Add MOPS instructions.
	(aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd,
	AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
	* aarch64-opc.c (aarch64_print_operand): Handle
	AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and
	AARCH64_OPND_MOPS_WB_Rn.
	(verify_three_different_regs): New function.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

gas/
	* doc/c-aarch64.texi: Document +mops.
	* config/tc-aarch64.c (parse_x0_to_x30): New function.
	(parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd,
	AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
	(aarch64_features): Add "mops".
	* testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test.
	* testsuite/gas/aarch64/mops_invalid.s,
	* testsuite/gas/aarch64/mops_invalid.d,
	* testsuite/gas/aarch64/mops_invalid.l: Likewise.

1 files changed, 6 insertions, 1 deletions

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 493b797..183d281 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -87,6 +87,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SSBS	     (1ULL << 47) /* SSBS mechanism enabled.  */
 #define AARCH64_FEATURE_MEMTAG       (1ULL << 48) /* Memory Tagging Extension.  */
 #define AARCH64_FEATURE_TME	     (1ULL << 49) /* Transactional Memory Extension.  */
+#define AARCH64_FEATURE_MOPS	     (1ULL << 50) /* Standardization of memory operations.  */
 #define AARCH64_FEATURE_I8MM	     (1ULL << 52) /* Matrix Multiply instructions.  */
 #define AARCH64_FEATURE_F32MM	     (1ULL << 53)
 #define AARCH64_FEATURE_F64MM	     (1ULL << 54)
@@ -143,7 +144,8 @@ typedef uint32_t aarch64_insn;
 						 AARCH64_FEATURE_V8_7	\
 						 | AARCH64_FEATURE_LS64)
 #define AARCH64_ARCH_V8_8	AARCH64_FEATURE (AARCH64_ARCH_V8_7,	\
-						 AARCH64_FEATURE_V8_8)
+						 AARCH64_FEATURE_V8_8	\
+						 | AARCH64_FEATURE_MOPS)
 #define AARCH64_ARCH_V8_R	(AARCH64_FEATURE (AARCH64_ARCH_V8_4,	\
 						 AARCH64_FEATURE_V8_R)	\
 			      & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
@@ -461,6 +463,9 @@ enum aarch64_opnd
   AARCH64_OPND_SME_PnT_Wm_imm,           /* SME <Pn>.<T>[<Wm>, #<imm>].  */
   AARCH64_OPND_TME_UIMM16,	/* TME unsigned 16-bit immediate.  */
   AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
+  AARCH64_OPND_MOPS_ADDR_Rd,	/* [Rd]!, in bits [0, 4].  */
+  AARCH64_OPND_MOPS_ADDR_Rs,	/* [Rs]!, in bits [16, 20].  */
+  AARCH64_OPND_MOPS_WB_Rn	/* Rn!, in bits [5, 9].  */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an