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authorAlan Modra <amodra@gmail.com>2000-02-23 13:52:23 +0000
committerAlan Modra <amodra@gmail.com>2000-02-23 13:52:23 +0000
commit5b93d8bb517c1f5715435dcf627a8642f557ddb2 (patch)
treee09626193185adb6455a6251622f32180183db5c /include
parentab91fdd5f80265ca7aabee53c9626d393ea8eb86 (diff)
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Add IBM 370 support.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog8
-rw-r--r--include/dis-asm.h1
-rw-r--r--include/elf/ChangeLog4
-rw-r--r--include/elf/i370.h46
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/i370.h265
6 files changed, 326 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index c78135e..b34f2fd 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,7 +1,11 @@
+2000-02-23 Linas Vepstas <linas@linas.org>
+
+ * dis-asm.h (print_insn_i370): Declare.
+
2000-02-22 Chandra Chavva <cchavva@cygnus.com>
- * opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation cannot
- be combined in parallel with ADD/SUBppp.
+ * opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation
+ cannot be combined in parallel with ADD/SUBppp.
Tue Feb 22 15:19:54 2000 Andrew Cagney <cagney@b1.cygnus.com>
diff --git a/include/dis-asm.h b/include/dis-asm.h
index 1f835d3..874c3b6 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -157,6 +157,7 @@ extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*));
+extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*));
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 54df0cf..129ad30 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2000-02-23 Linas Vepstas <linas@linas.org>
+
+ * i370.h: New file.
+
2000-02-22 Nick Clifton <nickc@cygnus.com>
* common.h (ELF_ST_OTHER): Remove definition.
diff --git a/include/elf/i370.h b/include/elf/i370.h
new file mode 100644
index 0000000..9c021f0
--- /dev/null
+++ b/include/elf/i370.h
@@ -0,0 +1,46 @@
+/* i370 ELF support for BFD.
+ Copyright (C) 1995, 2000 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* This file holds definitions specific to the i370 ELF ABI. Note
+ that most of this is not actually implemented by BFD. */
+
+#ifndef _ELF_I370_H
+#define _ELF_I370_H
+
+/* Processor specific section headers, sh_type field */
+
+#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \
+ entries in this section \
+ based on the address \
+ specified in the associated \
+ symbol table entry. */
+
+#define EF_I370_RELOCATABLE 0x00010000 /* i370 -mrelocatable flag */
+#define EF_I370_RELOCATABLE_LIB 0x00008000 /* i370 -mrelocatable-lib flag */
+/* Processor specific section flags, sh_flags field */
+
+#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \
+ this section from executable \
+ and shared objects that it \
+ builds when those objects \
+ are not to be furhter \
+ relocated. */
+#endif /* _ELF_I370_H */
+
+
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index b5befb8..3ce923a 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2000-02-23 Linas Vepstas <linas@linas.org>
+
+ * i370.h: New file.
+
2000-02-22 Andrew Haley <aph@cygnus.com>
* mips.h: (OPCODE_IS_MEMBER): Add comment.
diff --git a/include/opcode/i370.h b/include/opcode/i370.h
new file mode 100644
index 0000000..f2049e7
--- /dev/null
+++ b/include/opcode/i370.h
@@ -0,0 +1,265 @@
+/* i370.h -- Header file for S/390 opcode table
+ Copyright 1994, 95, 98, 99, 2000 Free Software Foundation, Inc.
+ PowerPC version written by Ian Lance Taylor, Cygnus Support
+ Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef I370_H
+#define I370_H
+
+/* The opcode table is an array of struct i370_opcode. */
+typedef union
+{
+ unsigned int i[2];
+ unsigned short s[4];
+ unsigned char b[8];
+} i370_insn_t;
+
+struct i370_opcode
+{
+ /* The opcode name. */
+ const char *name;
+
+ /* the length of the instruction */
+ char len;
+
+ /* The opcode itself. Those bits which will be filled in with
+ operands are zeroes. */
+ i370_insn_t opcode;
+
+ /* The opcode mask. This is used by the disassembler. This is a
+ mask containing ones indicating those bits which must match the
+ opcode field, and zeroes indicating those bits which need not
+ match (and are presumably filled in by operands). */
+ i370_insn_t mask;
+
+ /* One bit flags for the opcode. These are used to indicate which
+ specific processors support the instructions. The defined values
+ are listed below. */
+ unsigned long flags;
+
+ /* An array of operand codes. Each code is an index into the
+ operand table. They appear in the order which the operands must
+ appear in assembly code, and are terminated by a zero. */
+ unsigned char operands[8];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+ in the order in which the disassembler should consider
+ instructions. */
+extern const struct i370_opcode i370_opcodes[];
+extern const int i370_num_opcodes;
+
+/* Values defined for the flags field of a struct i370_opcode. */
+
+/* Opcode is defined for the original 360 architecture. */
+#define I370_OPCODE_360 (0x01)
+
+/* Opcode is defined for the 370 architecture. */
+#define I370_OPCODE_370 (0x02)
+
+/* Opcode is defined for the 370-XA architecture. */
+#define I370_OPCODE_370_XA (0x04)
+
+/* Opcode is defined for the ESA/370 architecture. */
+#define I370_OPCODE_ESA370 (0x08)
+
+/* Opcode is defined for the ESA/390 architecture. */
+#define I370_OPCODE_ESA390 (0x10)
+
+/* Opcode is defined for the ESA/390 w/ BFP facility. */
+#define I370_OPCODE_ESA390_BF (0x20)
+
+/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */
+#define I370_OPCODE_ESA390_BS (0x40)
+
+/* Opcode is defined for the ESA/390 w/ checksum facility. */
+#define I370_OPCODE_ESA390_CK (0x80)
+
+/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */
+#define I370_OPCODE_ESA390_CM (0x100)
+
+/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */
+#define I370_OPCODE_ESA390_FX (0x200)
+
+/* Opcode is defined for the ESA/390 w/ HFP facility. */
+#define I370_OPCODE_ESA390_HX (0x400)
+
+/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */
+#define I370_OPCODE_ESA390_IR (0x800)
+
+/* Opcode is defined for the ESA/390 w/ move-inverse facility. */
+#define I370_OPCODE_ESA390_MI (0x1000)
+
+/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */
+#define I370_OPCODE_ESA390_PC (0x2000)
+
+/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */
+#define I370_OPCODE_ESA390_PL (0x4000)
+
+/* Opcode is defined for the ESA/390 w/ square-root facility. */
+#define I370_OPCODE_ESA390_QR (0x8000)
+
+/* Opcode is defined for the ESA/390 w/ resume-program facility. */
+#define I370_OPCODE_ESA390_RP (0x10000)
+
+/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */
+#define I370_OPCODE_ESA390_SA (0x20000)
+
+/* Opcode is defined for the ESA/390 w/ subspace group facility. */
+#define I370_OPCODE_ESA390_SG (0x40000)
+
+/* Opcode is defined for the ESA/390 w/ string facility. */
+#define I370_OPCODE_ESA390_SR (0x80000)
+
+/* Opcode is defined for the ESA/390 w/ trap facility. */
+#define I370_OPCODE_ESA390_TR (0x100000)
+
+#define I370_OPCODE_ESA390_SUPERSET (0x1fffff)
+
+
+/* The operands table is an array of struct i370_operand. */
+
+struct i370_operand
+{
+ /* The number of bits in the operand. */
+ int bits;
+
+ /* How far the operand is left shifted in the instruction. */
+ int shift;
+
+ /* Insertion function. This is used by the assembler. To insert an
+ operand value into an instruction, check this field.
+
+ If it is NULL, execute
+ i |= (op & ((1 << o->bits) - 1)) << o->shift;
+ (i is the instruction which we are filling in, o is a pointer to
+ this structure, and op is the opcode value; this assumes twos
+ complement arithmetic).
+
+ If this field is not NULL, then simply call it with the
+ instruction and the operand value. It will return the new value
+ of the instruction. If the ERRMSG argument is not NULL, then if
+ the operand value is illegal, *ERRMSG will be set to a warning
+ string (the operand will be inserted in any case). If the
+ operand value is legal, *ERRMSG will be unchanged (most operands
+ can accept any value). */
+ i370_insn_t (*insert) PARAMS ((i370_insn_t instruction, long op,
+ const char **errmsg));
+
+ /* Extraction function. This is used by the disassembler. To
+ extract this operand type from an instruction, check this field.
+
+ If it is NULL, compute
+ op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+ if ((o->flags & I370_OPERAND_SIGNED) != 0
+ && (op & (1 << (o->bits - 1))) != 0)
+ op -= 1 << o->bits;
+ (i is the instruction, o is a pointer to this structure, and op
+ is the result; this assumes twos complement arithmetic).
+
+ If this field is not NULL, then simply call it with the
+ instruction value. It will return the value of the operand. If
+ the INVALID argument is not NULL, *INVALID will be set to
+ non-zero if this operand type can not actually be extracted from
+ this operand (i.e., the instruction does not match). If the
+ operand is valid, *INVALID will not be changed. */
+ long (*extract) PARAMS ((i370_insn_t instruction, int *invalid));
+
+ /* One bit syntax flags. */
+ unsigned long flags;
+
+ /* name -- handy for debugging, otherwise pointless */
+ char * name;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+ the operands field of the i370_opcodes table. */
+
+extern const struct i370_operand i370_operands[];
+
+/* Values defined for the flags field of a struct i370_operand. */
+
+/* This operand should be wrapped in parentheses rather than
+ separated from the previous by a comma. This is used for S, RS and
+ SS form instructions which want their operands to look like
+ reg,displacement(basereg) */
+#define I370_OPERAND_SBASE (0x01)
+
+/* This operand is a base register. It may or may not appear next
+ to an index register, i.e. either of the two forms
+ reg,displacement(basereg)
+ reg,displacement(index,basereg) */
+#define I370_OPERAND_BASE (0x02)
+
+/* This pair of operands should be wrapped in parentheses rather than
+ separated from the last by a comma. This is used for the RX form
+ instructions which want their operands to look like
+ reg,displacement(index,basereg) */
+#define I370_OPERAND_INDEX (0x04)
+
+/* This operand names a register. The disassembler uses this to print
+ register names with a leading 'r'. */
+#define I370_OPERAND_GPR (0x08)
+
+/* This operand names a floating point register. The disassembler
+ prints these with a leading 'f'. */
+#define I370_OPERAND_FPR (0x10)
+
+/* This operand is a displacement. */
+#define I370_OPERAND_RELATIVE (0x20)
+
+/* This operand is a length, such as that in SS form instructions. */
+#define I370_OPERAND_LENGTH (0x40)
+
+/* This operand is optional, and is zero if omitted. This is used for
+ the optional B2 field in the shift-left, shift-right instructions. The
+ assembler must count the number of operands remaining on the line,
+ and the number of operands remaining for the opcode, and decide
+ whether this operand is present or not. The disassembler should
+ print this operand out only if it is not zero. */
+#define I370_OPERAND_OPTIONAL (0x80)
+
+
+/* Define some misc macros. We keep them with the operands table
+ for simplicity. The macro table is an array of struct i370_macro. */
+
+struct i370_macro
+{
+ /* The macro name. */
+ const char *name;
+
+ /* The number of operands the macro takes. */
+ unsigned int operands;
+
+ /* One bit flags for the opcode. These are used to indicate which
+ specific processors support the instructions. The values are the
+ same as those for the struct i370_opcode flags field. */
+ unsigned long flags;
+
+ /* A format string to turn the macro into a normal instruction.
+ Each %N in the string is replaced with operand number N (zero
+ based). */
+ const char *format;
+};
+
+extern const struct i370_macro i370_macros[];
+extern const int i370_num_macros;
+
+
+#endif /* I370_H */