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| author | Sudi Das <sudi.das@arm.com> | 2019-01-25 13:57:14 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2019-01-25 14:49:51 +0000 |
| commit | 550fd7bf6858cd708c54ec90412ffb653a932c3d (patch) | |
| tree | f840ab8ecfb8f9464264e25430d43551a9101b77 /include | |
| parent | 183445093ebd6be285e29f75b877e62a723918c6 (diff) | |
| download | gdb-550fd7bf6858cd708c54ec90412ffb653a932c3d.zip gdb-550fd7bf6858cd708c54ec90412ffb653a932c3d.tar.gz gdb-550fd7bf6858cd708c54ec90412ffb653a932c3d.tar.bz2 | |
AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
* opcode/aarch64.h (enum aarch64_opnd): Remove
AARCH64_OPND_ADDR_SIMPLE_2.
(enum aarch64_insn_class): Remove ldstgv_indexed.
*** opcodes/ChangeLog ***
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 7 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
2 files changed, 7 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 6263644..c14276b 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,10 @@ +2019-01-25 Sudakshina Das <sudi.das@arm.com> + Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * opcode/aarch64.h (enum aarch64_opnd): Remove + AARCH64_OPND_ADDR_SIMPLE_2. + (enum aarch64_insn_class): Remove ldstgv_indexed. + 2019-01-22 Tom Tromey <tom@tromey.com> * coff/ecoff.h: Include coff/sym.h. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 77e9c10..0c0234a 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -275,7 +275,6 @@ enum aarch64_opnd AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ - AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */ AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ @@ -562,7 +561,6 @@ enum aarch64_insn_class ldstnapair_offs, ldstpair_off, ldstpair_indexed, - ldstgv_indexed, loadlit, log_imm, log_shift, |