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| author | Cooper Qu <cooper.qu@linux.alibaba.com> | 2020-09-02 14:06:03 +0800 |
|---|---|---|
| committer | Lifang Xia <lifang_xia@c-sky.com> | 2020-09-02 14:21:31 +0800 |
| commit | 4211a3400108b45732415cda0cacb087ab8690b1 (patch) | |
| tree | 780aa663468ff715258195d610048c841aeda8ea /include | |
| parent | 8119cc38379eb136a62b64f642ab4e3b6d4c6abd (diff) | |
| download | gdb-4211a3400108b45732415cda0cacb087ab8690b1.zip gdb-4211a3400108b45732415cda0cacb087ab8690b1.tar.gz gdb-4211a3400108b45732415cda0cacb087ab8690b1.tar.bz2 | |
CSKY: Add CPU CK803r3.
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.
gas/
* config/tc-csky.c (csky_cpus): Add ck803r3.
(CSKY_ISA_803R3): Define.
(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
include/
* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Move divul and divsl
to CSKYV2_ISA_3E3R3 instruction set.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/csky.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 9daa866..c6f00b3 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com> + + * opcode/csky.h (CSKYV2_ISA_3E3R3): Define. + 2020-08-31 Alan Modra <amodra@gmail.com> PR 26493 diff --git a/include/opcode/csky.h b/include/opcode/csky.h index 493e822..ab2b210 100644 --- a/include/opcode/csky.h +++ b/include/opcode/csky.h @@ -31,6 +31,7 @@ #define CSKYV2_ISA_3E3R1 (1L << 6) #define CSKYV2_ISA_3E3R2 (1L << 7) #define CSKYV2_ISA_10E60 (1L << 8) +#define CSKYV2_ISA_3E3R3 (1L << 9) #define CSKY_ISA_TRUST (1L << 11) #define CSKY_ISA_CACHE (1L << 12) |