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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:07:00 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:31:52 +0800 |
| commit | c63af675b9b69abbbf5e48d7b77ec2d311c5b6a8 (patch) | |
| tree | 53be9708af2762146c7cc787b284414a1b3b043e /include | |
| parent | 4d8f1ff3bc75dde16f52513de77c7b22a0650f7a (diff) | |
| download | gdb-c63af675b9b69abbbf5e48d7b77ec2d311c5b6a8.zip gdb-c63af675b9b69abbbf5e48d7b77ec2d311c5b6a8.tar.gz gdb-c63af675b9b69abbbf5e48d7b77ec2d311c5b6a8.tar.bz2 | |
RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds integer arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
integer arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VADCVVM): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 58618a4..df4b7ab 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2885,6 +2885,18 @@ #define MASK_TH_VAMOMAXUWV 0xf800707f #define MATCH_TH_VAMOMAXUDV 0xe000702f #define MASK_TH_VAMOMAXUDV 0xf800707f +#define MATCH_TH_VADCVVM 0x42000057 +#define MASK_TH_VADCVVM 0xfe00707f +#define MATCH_TH_VADCVXM 0x42004057 +#define MASK_TH_VADCVXM 0xfe00707f +#define MATCH_TH_VADCVIM 0x42003057 +#define MASK_TH_VADCVIM 0xfe00707f +#define MATCH_TH_VSBCVVM 0x4a000057 +#define MASK_TH_VSBCVVM 0xfe00707f +#define MATCH_TH_VSBCVXM 0x4a004057 +#define MASK_TH_VSBCVXM 0xfe00707f +#define MATCH_TH_VWMACCSUVV 0xf8002057 +#define MASK_TH_VWMACCSUVV 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f |