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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 11:00:49 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:35 +0100 |
| commit | ff6054520cc86ac2f34c21bcc2e44ede50b56cdc (patch) | |
| tree | e6585111c7956ce55bba8a2881162623d2e85b57 /include/opcode | |
| parent | af4bcb4ce6939da1738c847a06789d2223b67ca4 (diff) | |
| download | gdb-ff6054520cc86ac2f34c21bcc2e44ede50b56cdc.zip gdb-ff6054520cc86ac2f34c21bcc2e44ede50b56cdc.tar.gz gdb-ff6054520cc86ac2f34c21bcc2e44ede50b56cdc.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b4987de..144ec7e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -76,6 +76,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_CVADP 0x40000000000ULL /* Random Number instructions. */ #define AARCH64_FEATURE_RNG 0x80000000000ULL +/* BTI instructions. */ +#define AARCH64_FEATURE_BTI 0x100000000000ULL /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -105,7 +107,8 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_FRINTTS \ | AARCH64_FEATURE_SB \ | AARCH64_FEATURE_PREDRES \ - | AARCH64_FEATURE_CVADP) + | AARCH64_FEATURE_CVADP \ + | AARCH64_FEATURE_BTI) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) @@ -285,6 +288,7 @@ enum aarch64_opnd AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ AARCH64_OPND_PRFOP, /* Prefetch operation. */ AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ + AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ @@ -1090,6 +1094,13 @@ struct aarch64_inst aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; }; +/* Defining the HINT #imm values for the aarch64_hint_options. */ +#define HINT_OPD_CSYNC 0x11 +#define HINT_OPD_C 0x22 +#define HINT_OPD_J 0x24 +#define HINT_OPD_JC 0x26 +#define HINT_OPD_NULL 0x00 + /* Diagnosis related declaration and interface. */ |