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| author | saurabh.jha@arm.com <saurabh.jha@arm.com> | 2024-05-28 15:45:50 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-05-28 17:28:29 +0100 |
| commit | c3bb4211d972e681eadbdb8d800530323d98060f (patch) | |
| tree | 264912c9a034da0d112001904aab13d2812bd986 /include/opcode | |
| parent | 2db17c87bd67099921ae78f90f839122041f284a (diff) | |
| download | gdb-c3bb4211d972e681eadbdb8d800530323d98060f.zip gdb-c3bb4211d972e681eadbdb8d800530323d98060f.tar.gz gdb-c3bb4211d972e681eadbdb8d800530323d98060f.tar.bz2 | |
gas, aarch64: Add AdvSIMD lut extension
Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links:
* luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
* luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en
These instructions needed definition of some new operands. We will first
discuss operands for the third operand of the instructions and then
discuss a vector register list operand needed for the second operand.
The third operands are vectors with bit indices and without type
qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12
and they have 1 bit, 2 bit, and 3 bit indices respectively. For these
new operands, we defined new parsing case branch. The lsb and width of
these operands are the same as many existing but the convention is to
give different names to fields that serve different purpose so we
introduced new fields in aarch64-opc.c and aarch64-opc.h for these new
operands.
For the second operand of these instructions, we introduced a new
operand called LVn_LUT. This represents a vector register list with
stride 1. We defined new inserter and extractor for this new operand and
it is encoded in FLD_Rn. We are enforcing the number of registers in the
reglist using opcode flag rather than operand flag as this is what other
SIMD vector register list operands are doing. The disassembly also uses
opcode flag to print the correct number of registers.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ef4a3ff..95448b5 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -236,6 +236,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FAMINMAX, /* FP8 instructions. */ AARCH64_FEATURE_FP8, + /* LUT instructions. */ + AARCH64_FEATURE_LUT, AARCH64_NUM_FEATURES }; @@ -523,10 +525,14 @@ enum aarch64_opnd AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when qualifier is S_H. */ + AARCH64_OPND_Em_INDEX1_14, /* AdvSIMD 1-bit encoded index in Vm at [14] */ + AARCH64_OPND_Em_INDEX2_13, /* AdvSIMD 2-bit encoded index in Vm at [14:13] */ + AARCH64_OPND_Em_INDEX3_12, /* AdvSIMD 3-bit encoded index in Vm at [14:12] */ AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single structure to all lanes. */ + AARCH64_OPND_LVn_LUT, /* AdvSIMD Vector register list used in lut. */ AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ @@ -1026,7 +1032,8 @@ enum aarch64_insn_class the, sve2_urqvs, sve_index1, - rcpc3 + rcpc3, + lut }; /* Opcode enumerators. */ |