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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2023-11-16 12:18:28 +0000 |
|---|---|---|
| committer | srinath <srinath.parvathaneni@arm.com> | 2023-11-16 12:18:34 +0000 |
| commit | 311276f10c4f85827d3264a2682ae9219917060f (patch) | |
| tree | 22824b06a8cd530256bad14437b55f92b2ba8c7d /include/opcode | |
| parent | 43e228e98c33d3dbb428f4061de0362ba13ffbf5 (diff) | |
| download | gdb-311276f10c4f85827d3264a2682ae9219917060f.zip gdb-311276f10c4f85827d3264a2682ae9219917060f.tar.gz gdb-311276f10c4f85827d3264a2682ae9219917060f.tar.bz2 | |
aarch64: Add support to new features in RAS extension.
This patch also adds support for:
1. FEAT_RASv2 feature and "ERXGSR_EL1" system register.
RASv2 feature is enabled by passing +rasv2 to -march
(eg: -march=armv8-a+rasv2).
2. FEAT_SCTLR2 and following system registers.
SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3.
3. FEAT_FGT2 and following system registers.
HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2
4. FEAT_PFAR and following system registers.
PFAR_EL1, PFAR_EL2 and PFAR_EL12.
FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default
enabled from Armv9.4-A architecture.
This patch also adds support for two read only system registers
id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from
Armv8-A Architecture.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 881a421..03ef907 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -175,6 +175,14 @@ enum aarch64_feature_bit { AARCH64_FEATURE_THE, /* LSE128. */ AARCH64_FEATURE_LSE128, + /* ARMv8.9-A RAS Extensions. */ + AARCH64_FEATURE_RASv2, + /* System Control Register2. */ + AARCH64_FEATURE_SCTLR2, + /* Fine Grained Traps. */ + AARCH64_FEATURE_FGT2, + /* Physical Fault Address. */ + AARCH64_FEATURE_PFAR, AARCH64_NUM_FEATURES }; @@ -233,7 +241,11 @@ enum aarch64_feature_bit { #define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A) \ | AARCH64_FEATBIT (X, SPEv1p4) \ | AARCH64_FEATBIT (X, SPE_CRR) \ - | AARCH64_FEATBIT (X, SPE_FDS)) + | AARCH64_FEATBIT (X, SPE_FDS) \ + | AARCH64_FEATBIT (X, RASv2) \ + | AARCH64_FEATBIT (X, SCTLR2) \ + | AARCH64_FEATBIT (X, FGT2) \ + | AARCH64_FEATBIT (X, PFAR)) #define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \ | AARCH64_FEATBIT (X, F16) \ |