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authorRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:06 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:06 +0100
commit405f0c4131cbdf540d9e9559ba5d6e4f445a3818 (patch)
tree1f60d65b54504e98306dd77b6fc754c547471ecb /gprof
parentb9ca389690810dd03e96a6d11470539f923d03b9 (diff)
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aarch64: Try to avoid inappropriate default errors
After parsing a '{' and the first register, parse_typed_reg would report errors in subsequent registers in the same way as for the first register. It used set_default_error, which reports errors of the form "operand N must be X". The problem is that if there are multiple opcode entries for the same mnemonic, there could be several matches that lead to a default error. There's no guarantee that the default error for the register list is the one that will be chosen. To take an example from the testsuite: ext z0.b,{z31.b,z32.b},#0 gave: operand 2 must be an SVE vector register with the error being reported against the single-vector version of ext, even though the operand is clearly a list. This patch uses set_fatal_syntax_error to bump the priority of the error once we're sure that the operand is a list of the right type.
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