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| author | Ambrogino Modigliani <ambrogino.modigliani@gmail.com> | 2016-11-25 21:01:42 +0100 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2016-11-27 15:03:06 +1030 |
| commit | 5c3024d2c1d4c4f141d8364d487604f70678792a (patch) | |
| tree | a4a248569472996ba801b29edaa88df38d090c0e /gold/tilegx.cc | |
| parent | 2b0f37619f797bf640b2d45acb615817dd202954 (diff) | |
| download | gdb-5c3024d2c1d4c4f141d8364d487604f70678792a.zip gdb-5c3024d2c1d4c4f141d8364d487604f70678792a.tar.gz gdb-5c3024d2c1d4c4f141d8364d487604f70678792a.tar.bz2 | |
Fix spelling in comments in C source files (gold)
* aarch64.cc: Fix spelling in comments.
* arm.cc: Fix spelling in comments.
* icf.cc: Fix spelling in comments.
* layout.cc: Fix spelling in comments.
* layout.h: Fix spelling in comments.
* mips.cc: Fix spelling in comments.
* output.h: Fix spelling in comments.
* plugin.h: Fix spelling in comments.
* script-sections.h: Fix spelling in comments.
* script.h: Fix spelling in comments.
* stringpool.h: Fix spelling in comments.
* tilegx.cc: Fix spelling in comments.
Diffstat (limited to 'gold/tilegx.cc')
| -rw-r--r-- | gold/tilegx.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gold/tilegx.cc b/gold/tilegx.cc index 03b1a50..7ab99ab 100644 --- a/gold/tilegx.cc +++ b/gold/tilegx.cc @@ -2527,7 +2527,7 @@ Target_tilegx<size, big_endian>::make_plt_section(Symbol_table* symtab, this->got_section(symtab, layout); // Ensure that .rela.dyn always appears before .rela.plt, - // becuase on TILE-Gx, .rela.dyn needs to include .rela.plt + // because on TILE-Gx, .rela.dyn needs to include .rela.plt // in it's range. this->rela_dyn_section(layout); @@ -3375,7 +3375,7 @@ Target_tilegx<size, big_endian>::Scan::local(Symbol_table* symtab, // tilegx dynamic linker will not update local got entry, // so, if we are generating a shared object, we need to add a // dynamic relocation for this symbol's GOT entry to inform - // dynamic linker plus the load base explictly. + // dynamic linker plus the load base explicitly. if (parameters->options().output_is_position_independent()) { unsigned int got_offset @@ -3431,7 +3431,7 @@ Target_tilegx<size, big_endian>::Scan::local(Symbol_table* symtab, // // R_TILEGX_TLS_GD_CALL implicitly reference __tls_get_addr, // while all other target, x86/arm/mips/powerpc/sparc - // generate tls relocation against __tls_get_addr explictly, + // generate tls relocation against __tls_get_addr explicitly, // so for TILEGX, we need the following hack. if (opt_t == tls::TLSOPT_NONE) { if (!target->tls_get_addr_sym_defined_) { |