gdbserver: update target description creation for x86/linux

This commit is part of a series which aims to share more of the target
description creation between GDB and gdbserver for x86/Linux.

After some refactoring earlier in this series the shared
x86_linux_tdesc_for_tid function was added into nat/x86-linux-tdesc.c.
However, this function still relies on amd64_linux_read_description
and i386_linux_read_description which are implemented separately for
both gdbserver and GDB.  Given that at their core, all these functions
do is:

  1. take an xcr0 value as input,
  2. mask out some feature bits,
  3. look for a cached pre-generated target description and return it
     if found,
  4. if no cached target description is found then call either
     amd64_create_target_description or
     i386_create_target_description to create a new target
     description, which is then added to the cache.  Return the newly
     created target description.

The inner functions amd64_create_target_description and
i386_create_target_description are already shared between GDB and
gdbserver (in the gdb/arch/ directory), so the only thing that
the *_read_description functions really do is add the caching layer,
and it feels like this really could be shared.

However, we have a small problem.

Despite using the same {amd64,i386}_create_target_description
functions in both GDB and gdbserver to create the target descriptions,
on the gdbserver side we cache target descriptions based on a reduced
set of xcr0 feature bits.

What this means is that, in theory, different xcr0 values can map to
the same cache entry, which could result in the wrong target
description being used.

However, I'm not sure if this can actually happen in reality.  Within
gdbserver we already split the target description cache based on i386,
amd64, and x32.  I suspect within a given gdbserver session we'll only
see at most one target description for each of these.

The cache conflicting problem is caused by xcr0_to_tdesc_idx, which
maps an xcr0 value to a enum x86_linux_tdesc value, and there are only
7 usable values in enum x86_linux_tdesc.

In contrast, on the GDB side there are 64, 32, and 16 cache slots for
i386, amd64, and x32 respectively.

On the GDB side it is much more important to cache things correctly as
a single GDB session might connect to multiple different remote
targets, each of which might have slightly different x86
architectures.

And so, if we want to merge the target description caching between GDB
and gdbserver, then we need to first update gdbserver so that it
caches in the same way as GDB, that is, it needs to adopt a mechanism
that allows for the same number of cache slots of each of i386, amd64,
and x32.  In this way, when the caching is shared, GDB's behaviour
will not change.

Unfortunately it's a little more complex than that due to the in
process agent (IPA).

When the IPA is in use, gdbserver sends a target description index to
the IPA, and the IPA uses this to find the correct target description
to use, the IPA having first generated every possible target
description.

Interestingly, there is certainly a bug here which results from only
having 7 values in enum x86_linux_tdesc.  As multiple possible target
descriptions in gdbserver map to the same enum x86_linux_tdesc value,
then, when the enum x86_linux_tdesc value is sent to the IPA there is
no way for gdbserver to know that the IPA will select the correct
target description.  This bug will get fixed by this commit.

** START OF AN ASIDE **

Back in the day I suspect this approach of sending a target
description index made perfect sense.  However since this commit:

  commit a8806230241d201f808d856eaae4d44088117b0c
  Date:   Thu Dec 7 17:07:01 2017 +0000

      Initialize target description early in IPA

I think that passing an index was probably a bad idea.

We used to pass the index, and then use that index to lookup which
target description to instantiate and use, the target description was
not generated until the index arrived.

However, the above commit fixed an issue where we can't call malloc()
within (certain parts of) the IPA (apparently), so instead we now
pre-compute _every_ possible target description within the IPA.  The
index is only used to lookup which of the (many) pre-computed target
descriptions to use.

It would (I think) have been easier all around if the IPA just
self-inspected, figured out its own xcr0 value, and used that to
create the one target description that is required.  So long as the
xcr0 to target description code is shared (at compile time) with
gdbserver, then we can be sure that the IPA will derive the same
target description as gdbserver, and we would avoid all this index
passing business, which has made this commit so very, very painful.

I did look at how a process might derive its own xcr0 value, but I
don't believe this is actually that simple, so for now I've just
doubled down on the index passing approach.

While reviewing earlier iterations of this patch there has been
discussion about the possibility of removing the IPA from GDB.  That
would certainly make all of the code touched in this patch much
simpler, but I don't really want to do that as part of this series.

** END OF AN ASIDE **

Currently then for x86/linux, gdbserver sends a number between 0 and 7
to the IPA, and the IPA uses this to create a target description.

However, I am proposing that gdbserver should now create one of (up
to) 64 different target descriptions for i386, so this 0 to 7 index
isn't going to be good enough any more (amd64 and x32 have slightly
fewer possible target descriptions, but still more than 8, so the
problem is the same).

For a while I wondered if I was going to have to try and find some
backward compatible solution for this mess.  But after seeing how
lightly the IPA is actually documented, I wonder if it is not the case
that there is a tight coupling between a version of gdbserver and a
version of the IPA?  At least I'm hoping so, and that's what I've
assumed in this commit.

In this commit I have thrown out the old IPA target description index
numbering scheme, and switched to a completely new numbering scheme.
Instead of the index that is passed being arbitrary, the index is
instead calculated from the set of xcr0 features that are present on
the target.  Within the IPA we can then reverse this logic to recreate
the xcr0 value based on the index, and from the xcr0 value we can
choose the correct target description.

With the gdbserver to IPA numbering scheme issue resolved I have then
update the gdbserver versions of amd64_linux_read_description and
i386_linux_read_description so that they cache target descriptions
using the same set of xcr0 features as GDB itself.

After this gdbserver should now always come up with the same target
description as GDB does on any x86/Linux target.

This commit does not introduce any new code sharing between GDB and
gdbserver as previous commits in this series have done.  Instead this
commit is all about bringing GDB and gdbserver into alignment
functionally so that the next commit(s) can merge the GDB and
gdbserver versions of these functions.

Notes On The Implementation
---------------------------

Previously, within gdbserver, target descriptions were cached within
arrays.  These arrays were sized based on enum x86_linux_tdesc and
xcr0_to_tdesc_idx returned the array (cache) index.

Now we need different array lengths for each of i386, amd64, and x32.
And the index to use within each array is calculated based on which
xcr0 bits are set and valid for a particular target type.

I really wanted to avoid having fixed array sizes, or having the set
of relevant xcr0 bits encoded in multiple places.

The solution I came up with was to create a single data structure
which would contain a list of xcr0 bits along with flags to indicate
which of the i386, amd64, and x32 targets the bit is relevant for.  By
making the table constexpr, and adding some constexpr helper
functions, it is possible to calculate the sizes for the cache arrays
at compile time, as well as the bit masks needed to each target type.

During review it was pointed out[1] that possibly the failure to check
the SSE and X87 bits for amd64/x32 targets might be an error, however,
if this is the case then this is an issue that existed long before
this patch.  I'd really like to keep this patch focused on reworking
the existing code and try to avoid changing how target descriptions
are actually created, mostly out of fear that I'll break something.

[1] https://inbox.sourceware.org/gdb-patches/MN2PR11MB4566070607318EE7E669A5E28E1B2@MN2PR11MB4566.namprd11.prod.outlook.com

Approved-By: John Baldwin <jhb@FreeBSD.org>
Approved-By: Felix Willgerodt <felix.willgerodt@intel.com>

1 files changed, 8 insertions, 35 deletions

diff --git a/gdbserver/linux-amd64-ipa.cc b/gdbserver/linux-amd64-ipa.cc
index df5e6ac..6f4ce6f 100644
--- a/gdbserver/linux-amd64-ipa.cc
+++ b/gdbserver/linux-amd64-ipa.cc
@@ -164,47 +164,21 @@ supply_static_tracepoint_registers (struct regcache *regcache,
 
 #endif /* HAVE_UST */
 
-#if !defined __ILP32__
-/* Map the tdesc index to xcr0 mask.  */
-static uint64_t idx2mask[X86_TDESC_LAST] = {
-  X86_XSTATE_X87_MASK,
-  X86_XSTATE_SSE_MASK,
-  X86_XSTATE_AVX_MASK,
-  X86_XSTATE_MPX_MASK,
-  X86_XSTATE_AVX_MPX_MASK,
-  X86_XSTATE_AVX_AVX512_MASK,
-  X86_XSTATE_AVX_MPX_AVX512_PKU_MASK,
-};
-#endif
-
 /* Return target_desc to use for IPA, given the tdesc index passed by
    gdbserver.  */
 
 const struct target_desc *
 get_ipa_tdesc (int idx)
 {
-  if (idx >= X86_TDESC_LAST)
-    {
-      internal_error ("unknown ipa tdesc index: %d", idx);
-    }
+  uint64_t xcr0 = x86_linux_tdesc_idx_to_xcr0 (idx);
 
 #if defined __ILP32__
-  switch (idx)
-    {
-    case X86_TDESC_SSE:
-      return amd64_linux_read_description (X86_XSTATE_SSE_MASK, true);
-    case X86_TDESC_AVX:
-      return amd64_linux_read_description (X86_XSTATE_AVX_MASK, true);
-    case X86_TDESC_AVX_AVX512:
-      return amd64_linux_read_description (X86_XSTATE_AVX_AVX512_MASK, true);
-    default:
-      break;
-    }
+  bool is_x32 = true;
 #else
-  return amd64_linux_read_description (idx2mask[idx], false);
+  bool is_x32 = false;
 #endif
 
-  internal_error ("unknown ipa tdesc index: %d", idx);
+  return amd64_linux_read_description (xcr0, is_x32);
 }
 
 /* Allocate buffer for the jump pads.  The branch instruction has a
@@ -272,11 +246,10 @@ void
 initialize_low_tracepoint (void)
 {
 #if defined __ILP32__
-  amd64_linux_read_description (X86_XSTATE_SSE_MASK, true);
-  amd64_linux_read_description (X86_XSTATE_AVX_MASK, true);
-  amd64_linux_read_description (X86_XSTATE_AVX_AVX512_MASK, true);
+  for (int i = 0; i < x86_linux_x32_tdesc_count (); i++)
+    amd64_linux_read_description (x86_linux_tdesc_idx_to_xcr0 (i), true);
 #else
-  for (auto i = 0; i < X86_TDESC_LAST; i++)
-    amd64_linux_read_description (idx2mask[i], false);
+  for (int i = 0; i < x86_linux_amd64_tdesc_count (); i++)
+    amd64_linux_read_description (x86_linux_tdesc_idx_to_xcr0 (i), false);
 #endif
 }