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authorLuis Machado <luis.machado@arm.com>2023-02-07 09:36:23 +0000
committerLuis Machado <luis.machado@arm.com>2023-10-04 16:23:39 +0100
commitca65640ff724f330e90e63ae0b14a195be79b4f6 (patch)
tree1ad86912de1ab8a0a62166e4b8922626a732a1b5 /gdb/features
parent89c4ee8398e3915c6685bb74057eb5644cf36959 (diff)
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sme: Enable SME registers and pseudo-registers
The SME (Scalable Matrix Extension) [1] exposes a new matrix register ZA with variable sizes. It also exposes a new mode called streaming mode. Similarly to SVE, the ZA register size is dictated by a vector length, but the SME vector length is called streaming vetor length. The total size for ZA in a given moment is svl x svl. In streaming mode, the SVE registers have their sizes based on svl rather than the regular vector length (vl). The feature detection is controlled by the HWCAP2_SME bit, but actual support should be validated by attempting a ptrace call for one of the new register sets: NT_ARM_ZA and NT_ARM_SSVE. Due to its large size, the ZA register is exposed as a vector of bytes, but we introduce a number of pseudo-registers that gives various different views into the ZA contents. These can be arranged in a couple categories: tiles and tile slices. Tiles are matrices the same size or smaller than ZA. Tile slices are vectors which map to ZA's rows/columns in different ways. A new dynamic target description is provided containing the ZA register, the SVG register and the SVCR register. The size of ZA, like the SVE vector registers, is based on the vector length register SVG (VG for SVE). This patch enables SME register support for gdb. [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture Co-Authored-By: Ezra Sitorus <ezra.sitorus@arm.com> Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Diffstat (limited to 'gdb/features')
-rw-r--r--gdb/features/aarch64-sme.c63
1 files changed, 63 insertions, 0 deletions
diff --git a/gdb/features/aarch64-sme.c b/gdb/features/aarch64-sme.c
new file mode 100644
index 0000000..697a301
--- /dev/null
+++ b/gdb/features/aarch64-sme.c
@@ -0,0 +1,63 @@
+/* Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "gdbsupport/tdesc.h"
+#include <cmath>
+
+/* This function is NOT auto generated from xml. Create the AArch64 SME
+ feature into RESULT. SVL is the streaming vector length in bytes.
+
+ The ZA register has a total size of SVL x SVL.
+
+ When in Streaming SVE mode, the effective SVE vector length, VL, is equal
+ to SVL. */
+
+static int
+create_feature_aarch64_sme (struct target_desc *result, long regnum,
+ size_t svl)
+{
+ struct tdesc_feature *feature;
+ tdesc_type *element_type;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.sme");
+
+ /* The SVG register. */
+ tdesc_create_reg (feature, "svg", regnum++, 1, nullptr, 64, "int");
+
+ /* SVCR flags type. */
+ tdesc_type_with_fields *type_with_fields
+ = tdesc_create_flags (feature, "svcr_flags", 8);
+ tdesc_add_flag (type_with_fields, 0, "SM");
+ tdesc_add_flag (type_with_fields, 1, "ZA");
+
+ /* The SVCR register. */
+ tdesc_create_reg (feature, "svcr", regnum++, 1, nullptr, 64, "svcr_flags");
+
+ /* Byte type. */
+ element_type = tdesc_named_type (feature, "uint8");
+ /* Vector of bytes. */
+ element_type = tdesc_create_vector (feature, "sme_bv", element_type,
+ svl);
+ /* Vector of vector of bytes (Matrix). */
+ element_type = tdesc_create_vector (feature, "sme_bvv", element_type,
+ svl);
+
+ /* The following is the ZA register set. */
+ tdesc_create_reg (feature, "za", regnum++, 1, nullptr,
+ std::pow (svl, 2) * 8, "sme_bvv");
+ return regnum;
+}