diff options
| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2021-01-12 13:57:23 +0000 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2021-01-12 14:03:58 +0000 |
| commit | 5291fe3cd14f2861fad43303a10550e71dc14182 (patch) | |
| tree | 80ab70388403d31b63df0fcc67a505e059164c7c /gdb/features | |
| parent | d546b61084cec687e0063b2e0e169b4690341c23 (diff) | |
| download | gdb-5291fe3cd14f2861fad43303a10550e71dc14182.zip gdb-5291fe3cd14f2861fad43303a10550e71dc14182.tar.gz gdb-5291fe3cd14f2861fad43303a10550e71dc14182.tar.bz2 | |
aarch64: Add support for bfloat16 in gdb.
This patch adds support for bfloat16 in AArch64 gdb.
Also adds the field "bf" to vector registers h0-h31.
Also adds the vector "bf" to h field in vector registers v0-v31.
The following is how the vector register h and v looks like.
Before this patch:
(gdb) p $h0
$1 = {f = 0, u = 0, s = 0}
(gdb) p/x $h0
$2 = {f = 0x0, u = 0x0, s = 0x0}
(gdb) p $v0.h
$3 = {f = {0, 0, 0, 0, 0, 0, 0, 0}, u = {0, 0, 0, 0, 0, 0, 0, 0}, s = {0, 0, 0, 0, 0, 0, 0, 0}}
(gdb) p/x $v0.h
$4 = {f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
s = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}
After this patch:
(gdb) p $h0
$1 = {bf = 0, f = 0, u = 0, s = 0}
(gdb) p/x $h0
$2 = {bf = 0x0, f = 0x0, u = 0x0, s = 0x0}
(gdb) p $v0.h
$3 = {bf = {0, 0, 0, 0, 0, 0, 0, 0}, f = {0, 0, 0, 0, 0, 0, 0, 0}, u = {0, 0, 0, 0, 0, 0, 0, 0},
s = {0, 0, 0, 0, 0, 0, 0, 0}}
(gdb) p/x $v0.h
$4 = {bf = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
u = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, s = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}
gdb/ChangeLog:
2021-01-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* aarch64-tdep.c (aarch64_vnh_type): Add "bf" field in h registers.
(aarch64_vnv_type): Add "bf" type in h field of v registers.
* features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerated.
* features/aarch64-fpu.xml: Add bfloat16 type.
gdb/testsuite/ChangeLog:
2021-01-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gdb.arch/aarch64-fp.exp: Modify to test bfloat16 support.
Diffstat (limited to 'gdb/features')
| -rw-r--r-- | gdb/features/aarch64-fpu.c | 5 | ||||
| -rw-r--r-- | gdb/features/aarch64-fpu.xml | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c index 5b636a5..a80b7d4 100644 --- a/gdb/features/aarch64-fpu.c +++ b/gdb/features/aarch64-fpu.c @@ -37,6 +37,9 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum) element_type = tdesc_named_type (feature, "int16"); tdesc_create_vector (feature, "v8i", element_type, 8); + element_type = tdesc_named_type (feature, "bfloat16"); + tdesc_create_vector (feature, "v8bf16", element_type, 8); + element_type = tdesc_named_type (feature, "uint8"); tdesc_create_vector (feature, "v16u", element_type, 16); @@ -68,6 +71,8 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum) tdesc_add_field (type_with_fields, "s", field_type); type_with_fields = tdesc_create_union (feature, "vnh"); + field_type = tdesc_named_type (feature, "v8bf16"); + tdesc_add_field (type_with_fields, "bf", field_type); field_type = tdesc_named_type (feature, "v8f"); tdesc_add_field (type_with_fields, "f", field_type); field_type = tdesc_named_type (feature, "v8u"); diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml index 14b3137..2235d07 100644 --- a/gdb/features/aarch64-fpu.xml +++ b/gdb/features/aarch64-fpu.xml @@ -17,6 +17,7 @@ <vector id="v8f" type="ieee_half" count="8"/> <vector id="v8u" type="uint16" count="8"/> <vector id="v8i" type="int16" count="8"/> + <vector id="v8bf16" type="bfloat16" count="8"/> <vector id="v16u" type="uint8" count="16"/> <vector id="v16i" type="int8" count="16"/> <vector id="v1u" type="uint128" count="1"/> @@ -32,6 +33,7 @@ <field name="s" type="v4i"/> </union> <union id="vnh"> + <field name="bf" type="v8bf16"/> <field name="f" type="v8f"/> <field name="u" type="v8u"/> <field name="s" type="v8i"/> |