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authorAlan Hayward <alan.hayward@arm.com>2018-08-22 09:17:24 +0100
committerAlan Hayward <alan.hayward@arm.com>2018-08-22 09:19:01 +0100
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Add AArch64 SVE to NEWS and GDB manual
gdb/ * NEWS: Add SVE to 8.2 section. gdb/doc/ * doc/gdb.texinfo (AArch64 SVE): New subsubsection.
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-rw-r--r--gdb/doc/gdb.texinfo16
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diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
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@@ -1,3 +1,7 @@
+2018-08-21 Alan Hayward <alan.hayward@arm.com>
+
+ * gdb.texinfo (AArch64 SVE): New subsubsection.
+
2018-08-14 Jan Vrany <jan.vrany@fit.cvut.cz>
* gdb.texinfo (GDB/MI Data Manipulation): Document
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 433a269..eb898f9 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -23451,6 +23451,22 @@ Show whether AArch64 debugging messages are displayed.
@end table
+@subsubsection AArch64 SVE.
+@cindex AArch64 SVE.
+
+When @value{GDBN} is debugging the AArch64 architecture, if the Scalable Vector
+Extension (SVE) is present, then @value{GDBN} will provide the vector registers
+@code{$z0} through @code{$z31}, vector predicate registers @code{$p0} through
+@code{$p15}, and the @code{$ffr} register. In addition, the pseudo register
+@code{$vg} will be provided. This is the vector granule for the current thread
+and represents the number of 64-bit chunks in an SVE @code{z} register.
+
+If the vector length changes, then the @code{$vg} register will be updated,
+but the lengths of the @code{z} and @code{p} registers will not change. This
+is a known limitation of @value{GDBN} and does not affect the execution of the
+target process.
+
+
@node i386
@subsection x86 Architecture-specific Issues