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authorChristophe Lyon <christophe.lyon@arm.com>2022-04-01 10:22:16 +0100
committerChristophe Lyon <christophe.lyon@arm.com>2022-04-27 15:18:18 +0100
commitae7e2f45aa4798be449f282bbf75ad41e73f055e (patch)
tree9f22bd3ae6c6e9dd732f1bb7a10d22e6693d1cc9 /gdb/arm-tdep.h
parent0824193fd31467b6ff39132d0d72aaa9c01cc9aa (diff)
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gdb/arm: Add support for multiple stack pointers on Cortex-M
Armv8-M architecture with Security extension features four stack pointers to handle Secure and Non-secure modes. This patch adds support to switch between them as needed during unwinding, and replaces all updates of cache->prev_sp with calls to arm_cache_set_prev_sp. Signed-off-by: Torbjörn Svensson <torbjorn.svensson@st.com> Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com> Signed-off-by: Christophe Lyon <christophe.lyon@arm.com>
Diffstat (limited to 'gdb/arm-tdep.h')
-rw-r--r--gdb/arm-tdep.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 4017067..864406e 100644
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -125,10 +125,17 @@ struct arm_gdbarch_tdep : gdbarch_tdep
register. */
int pacbti_pseudo_count = 0; /* Total number of PACBTI pseudo registers. */
- int m_profile_msp_regnum = 0; /* M-profile MSP register number. */
- int m_profile_psp_regnum = 0; /* M-profile PSP register number. */
+ int m_profile_msp_regnum = ARM_SP_REGNUM; /* M-profile MSP register number. */
+ int m_profile_psp_regnum = ARM_SP_REGNUM; /* M-profile PSP register number. */
+
+ /* Secure and Non-secure stack pointers with security extension. */
+ int m_profile_msp_ns_regnum = ARM_SP_REGNUM; /* M-profile MSP_NS register number. */
+ int m_profile_psp_ns_regnum = ARM_SP_REGNUM; /* M-profile PSP_NS register number. */
+ int m_profile_msp_s_regnum = ARM_SP_REGNUM; /* M-profile MSP_S register number. */
+ int m_profile_psp_s_regnum = ARM_SP_REGNUM; /* M-profile PSP_S register number. */
bool is_m = false; /* Does the target follow the "M" profile. */
+ bool have_sec_ext = false; /* Do we have security extensions? */
CORE_ADDR lowest_pc = 0; /* Lowest address at which instructions
will appear. */