[aarch64] Add TPIDR2 register support for Linux

With the AArch64 Scalable Matrix Extension we have a new TPIDR2 register, and
it will be added to the existing NT_ARM_TLS register set. Kernel patches are
being reviewed here:

https://lore.kernel.org/linux-arm-kernel/20220818170111.351889-1-broonie@kernel.org/

From GDB's perspective, we handle it in a similar way to the existing TPIDR
register. But we need to consider cases of systems that only have TPIDR and
systems that have both TPIDR and TPIDR2.

With that in mind, the following patch adds the required code to support
TPIDR2 and turns the org.gnu.gdb.aarch64.tls feature into a
dynamically-generated target description as opposed to a static target
description containing only TPIDR.

That means we can remove the gdb/features/aarch64-tls.xml file and replace the
existing gdb/features/aarch64-tls.c auto-generated file with a new file that
dynamically generates the target description containing either TPIDR alone or
TPIDR and TPIDR2.

In the future, when *BSD's start to support this register, they can just
enable it as is being done for the AArch64 Linux target.

The core file read/write code has been updated to support TPIDR2 as well.

On GDBserver's side, there is a small change to the find_regno function to
expose a non-throwing version of it.

It always seemed strange to me how find_regno causes the whole operation to
abort if it doesn't find a particular register name. The patch moves code
from find_regno into find_regno_no_throw and makes find_regno call
find_regno_no_throw instead.

This allows us to do register name lookups to find a particular register
number without risking erroring out if nothing is found.

The patch also adjusts the feature detection code for aarch64-fbsd, since
the infrastructure is shared amongst all aarch64 targets. I haven't added
code to support TPIDR2 in aarch64-fbsd though, as I'm not sure when/if
that will happen.

2 files changed, 12 insertions, 7 deletions

diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c
index 0f73286..565c5e7 100644
--- a/gdb/arch/aarch64.c
+++ b/gdb/arch/aarch64.c
@@ -53,8 +53,9 @@ aarch64_create_target_description (const aarch64_features &features)
   if (features.mte)
     regnum = create_feature_aarch64_mte (tdesc.get (), regnum);
 
-  if (features.tls)
-    regnum = create_feature_aarch64_tls (tdesc.get (), regnum);
+  /* TLS registers.  */
+  if (features.tls > 0)
+    regnum = create_feature_aarch64_tls (tdesc.get (), regnum, features.tls);
 
   return tdesc.release ();
 }
diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h
index 8e3fd36..b1a6ce3 100644
--- a/gdb/arch/aarch64.h
+++ b/gdb/arch/aarch64.h
@@ -33,7 +33,9 @@ struct aarch64_features
 
   bool pauth = false;
   bool mte = false;
-  bool tls = false;
+
+  /* A positive TLS value indicates the number of TLS registers available.  */
+  uint8_t tls = 0;
 };
 
 inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs)
@@ -56,7 +58,9 @@ namespace std
       h = features.vq;
       h = h << 1 | features.pauth;
       h = h << 1 | features.mte;
-      h = h << 1 | features.tls;
+      /* Shift by two bits for now.  We may need to increase this in the future
+	 if more TLS registers get added.  */
+      h = h << 2 | features.tls;
       return h;
     }
   };
@@ -96,7 +100,9 @@ enum aarch64_regnum
   AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7
 };
 
-#define V_REGISTER_SIZE 16
+/* Sizes of various AArch64 registers.  */
+#define AARCH64_TLS_REGISTER_SIZE 8
+#define V_REGISTER_SIZE	  16
 
 /* Pseudo register base numbers.  */
 #define AARCH64_Q0_REGNUM 0
@@ -117,8 +123,6 @@ enum aarch64_regnum
 #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1
 #define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1
 
-#define	AARCH64_TLS_REGS_SIZE (8)
-
 /* There are a number of ways of expressing the current SVE vector size:
 
    VL : Vector Length.