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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2021-07-21 12:33:44 -0300 |
|---|---|---|
| committer | Luis Machado <luis.machado@linaro.org> | 2021-10-11 16:03:56 -0300 |
| commit | ae66a8f19ef6bf2dc7369cf26073f34ddf7c175b (patch) | |
| tree | f3b480e48c9d4d7cef64a49764ce9a9415933f64 /gdb/arch | |
| parent | ecbf5d4f9b716c50908f62cbb9917ed42d45a254 (diff) | |
| download | gdb-ae66a8f19ef6bf2dc7369cf26073f34ddf7c175b.zip gdb-ae66a8f19ef6bf2dc7369cf26073f34ddf7c175b.tar.gz gdb-ae66a8f19ef6bf2dc7369cf26073f34ddf7c175b.tar.bz2 | |
[ARM] Add support for M-profile MVE extension
This patch adds support for the M-profile MVE extension, which includes the
following:
- New M-profile XML feature m-profile-mve
- MVE vector predication status and control register (VPR)
- p0 pseudo register (contained in the VPR)
- q0 ~ q7 pseudo vector registers
- New feature bits
- Documentation update
Pseudo register p0 is the least significant bits of vpr and can be accessed
as $p0 or displayed through $vpr. For more information about the register
layout, please refer to [1].
The q0 ~ q7 registers map back to the d0 ~ d15 registers, two d registers
per q register.
The register dump looks like this:
(gdb) info reg all
r0 0x0 0
r1 0x0 0
r2 0x0 0
r3 0x0 0
r4 0x0 0
r5 0x0 0
r6 0x0 0
r7 0x0 0
r8 0x0 0
r9 0x0 0
r10 0x0 0
r11 0x0 0
r12 0x0 0
sp 0x0 0x0 <__Vectors>
lr 0xffffffff -1
pc 0xd0c 0xd0c <Reset_Handler>
xpsr 0x1000000 16777216
d0 0 (raw 0x0000000000000000)
d1 0 (raw 0x0000000000000000)
d2 0 (raw 0x0000000000000000)
d3 0 (raw 0x0000000000000000)
d4 0 (raw 0x0000000000000000)
d5 0 (raw 0x0000000000000000)
d6 0 (raw 0x0000000000000000)
d7 0 (raw 0x0000000000000000)
d8 0 (raw 0x0000000000000000)
d9 0 (raw 0x0000000000000000)
d10 0 (raw 0x0000000000000000)
d11 0 (raw 0x0000000000000000)
d12 0 (raw 0x0000000000000000)
d13 0 (raw 0x0000000000000000)
d14 0 (raw 0x0000000000000000)
d15 0 (raw 0x0000000000000000)
fpscr 0x0 0
vpr 0x0 [ P0=0 MASK01=0 MASK23=0 ]
s0 0 (raw 0x00000000)
s1 0 (raw 0x00000000)
s2 0 (raw 0x00000000)
s3 0 (raw 0x00000000)
s4 0 (raw 0x00000000)
s5 0 (raw 0x00000000)
s6 0 (raw 0x00000000)
s7 0 (raw 0x00000000)
s8 0 (raw 0x00000000)
s9 0 (raw 0x00000000)
s10 0 (raw 0x00000000)
s11 0 (raw 0x00000000)
s12 0 (raw 0x00000000)
s13 0 (raw 0x00000000)
s14 0 (raw 0x00000000)
s15 0 (raw 0x00000000)
s16 0 (raw 0x00000000)
s17 0 (raw 0x00000000)
s18 0 (raw 0x00000000)
s19 0 (raw 0x00000000)
s20 0 (raw 0x00000000)
s21 0 (raw 0x00000000)
s22 0 (raw 0x00000000)
s23 0 (raw 0x00000000)
s24 0 (raw 0x00000000)
s25 0 (raw 0x00000000)
s26 0 (raw 0x00000000)
s27 0 (raw 0x00000000)
s28 0 (raw 0x00000000)
s29 0 (raw 0x00000000)
s30 0 (raw 0x00000000)
s31 0 (raw 0x00000000)
q0 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q1 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q2 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q3 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q4 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q5 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q6 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q7 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
p0 0x0 0
Built and regtested with a simulator.
[1] https://developer.arm.com/documentation/ddi0553/bn
Co-Authored-By: Luis Machado <luis.machado@linaro.org>
Diffstat (limited to 'gdb/arch')
| -rw-r--r-- | gdb/arch/arm.c | 7 | ||||
| -rw-r--r-- | gdb/arch/arm.h | 3 |
2 files changed, 10 insertions, 0 deletions
diff --git a/gdb/arch/arm.c b/gdb/arch/arm.c index 7407c4a..a18b38b 100644 --- a/gdb/arch/arm.c +++ b/gdb/arch/arm.c @@ -27,6 +27,7 @@ #include "../features/arm/xscale-iwmmxt.c" #include "../features/arm/arm-m-profile.c" #include "../features/arm/arm-m-profile-with-fpa.c" +#include "../features/arm/arm-m-profile-mve.c" /* See arm.h. */ @@ -439,6 +440,12 @@ arm_create_mprofile_target_description (arm_m_profile_type m_type) regnum = create_feature_arm_arm_m_profile_with_fpa (tdesc, regnum); break; + case ARM_M_TYPE_MVE: + regnum = create_feature_arm_arm_m_profile (tdesc, regnum); + regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum); + regnum = create_feature_arm_arm_m_profile_mve (tdesc, regnum); + break; + default: error (_("Invalid Arm M type: %d"), m_type); } diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index f6a155d..eabcb43 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -59,6 +59,8 @@ enum gdb_regnum { /* Register count constants. */ enum arm_register_counts { + /* Number of Q registers for MVE. */ + ARM_MVE_NUM_Q_REGS = 8, /* Number of argument registers. */ ARM_NUM_ARG_REGS = 4, /* Number of floating point argument registers. */ @@ -89,6 +91,7 @@ enum arm_m_profile_type { ARM_M_TYPE_M_PROFILE, ARM_M_TYPE_VFP_D16, ARM_M_TYPE_WITH_FPA, + ARM_M_TYPE_MVE, ARM_M_TYPE_INVALID }; |