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authorAnton Kolesov <Anton.Kolesov@synopsys.com>2017-02-10 14:12:06 +0300
committerAnton Kolesov <Anton.Kolesov@synopsys.com>2017-03-28 21:36:35 +0300
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treeb3df9e1ebf01db2652e0c1b99cab8b68e814eddb /gdb/arc-tdep.h
parent3be78afdeddd3ebf57eb0df8b029cf596f468c7a (diff)
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arc: Add disassembler helper
Add disassembler helper for GDB, that uses opcodes structure arc_instruction and adds convenience functions to handle instruction operands. This interface solves at least those problems with arc_instruction: * Some instructions, like "push_s", have implicit operands which are not directly present in arc_instruction. * Operands of particular meaning, like branch/jump targets, have various locations and meaning depending on type of branch/target. * Access to operand value is abstracted into a separate function, so callee code shouldn't bother if operand value is an immediate value or in a register. Testcases included in this commit are fairly limited - they test exclusively branch instructions, something that will be used in software single stepping. Most of the other parts of this disassembler helper are tested during prologue analysis testing. gdb/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * configure.tgt: Add arc-insn.o. * arc-tdep.c (arc_delayed_print_insn): Make non-static. (dump_arc_instruction_command): New function. (arc_fprintf_disasm): Likewise. (arc_disassemble_info): Likewise. (arc_insn_get_operand_value): Likewise. (arc_insn_get_operand_value_signed): Likewise. (arc_insn_get_memory_base_reg): Likewise. (arc_insn_get_memory_offset): Likewise. (arc_insn_get_branch_target): Likewise. (arc_insn_dump): Likewise. (arc_insn_get_linear_next_pc): Likewise. * arc-tdep.h (arc_delayed_print_insn): Add function declaration. (arc_disassemble_info): Likewise. (arc_insn_get_branch_target): Likewise. (arc_insn_get_linear_next_pc): Likewise. * NEWS: Mention new "maint print arc arc-instruction". gdb/doc/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * gdb.texinfo (Synopsys ARC): Add "maint print arc arc-instruction". gdb/testsuite/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * gdb.arch/arc-decode-insn.S: New file. * gdb.arch/arc-decode-insn.exp: Likewise.
Diffstat (limited to 'gdb/arc-tdep.h')
-rw-r--r--gdb/arc-tdep.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h
index 326f486..1bf1817 100644
--- a/gdb/arc-tdep.h
+++ b/gdb/arc-tdep.h
@@ -123,4 +123,29 @@ arc_mach_is_arcv2 (struct gdbarch *gdbarch)
return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arcv2;
}
+/* Function to access ARC disassembler. Underlying opcodes disassembler will
+ print an instruction into stream specified in the INFO, so if it is
+ undesired, then this stream should be set to some invisible stream, but it
+ can't be set to an actual NULL value - that would cause a crash. */
+int arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info);
+
+/* Return properly initialized disassemble_info for ARC disassembler - it will
+ not print disassembled instructions to stderr. */
+
+struct disassemble_info arc_disassemble_info (struct gdbarch *gdbarch);
+
+/* Get branch/jump target address for the INSN. Note that this function
+ returns branch target and doesn't evaluate if this branch is taken or not.
+ For the indirect jumps value depends in register state, hence can change.
+ It is an error to call this function for a non-branch instruction. */
+
+CORE_ADDR arc_insn_get_branch_target (const struct arc_instruction &insn);
+
+/* Get address of next instruction after INSN, assuming linear execution (no
+ taken branches). If instruction has a delay slot, then returned value will
+ point at the instruction in delay slot. That is - "address of instruction +
+ instruction length with LIMM". */
+
+CORE_ADDR arc_insn_get_linear_next_pc (const struct arc_instruction &insn);
+
#endif /* ARC_TDEP_H */