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| author | Alan Modra <amodra@gmail.com> | 2017-03-06 19:39:34 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2017-03-06 21:54:23 +1030 |
| commit | 73f07bffaf8d423295a38dde51dfe6ec7b273280 (patch) | |
| tree | c7f5d0cba46cac8c01b3e23a671b147f101785e6 /gdb/amd64-nat.c | |
| parent | ea0de82ec2d7f109ba179d8d55130805e680f02d (diff) | |
| download | gdb-73f07bffaf8d423295a38dde51dfe6ec7b273280.zip gdb-73f07bffaf8d423295a38dde51dfe6ec7b273280.tar.gz gdb-73f07bffaf8d423295a38dde51dfe6ec7b273280.tar.bz2 | |
Don't decode powerpc insns with invalid fields
Certain insns have restrictions on fields. For example, the insn
mentioned in the PR, lqarx, must specify an even general purpose
register as its destination and that register cannot appear in
either of the base or index reg fields. This holds even when the RA0
field is 0 (meaning a zero rather than r0).
PR 21124
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
(extract_raq, extract_ras, extract_rbx): New functions.
(powerpc_operands): Use opposite corresponding insert function.
(Q_MASK): Define.
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
register restriction.
Diffstat (limited to 'gdb/amd64-nat.c')
0 files changed, 0 insertions, 0 deletions