diff options
| author | Sam James <sam@gentoo.org> | 2023-08-02 12:06:23 +0100 |
|---|---|---|
| committer | Sam James <sam@gentoo.org> | 2023-08-02 12:06:23 +0100 |
| commit | b5c37946cce4b41af0436529b139fa3d23e61f73 (patch) | |
| tree | 02129ebadb74e7d3f2430cf8221799ce186600e3 /gas | |
| parent | 675b9d612cc59446e84e2c6d89b45500cb603a8d (diff) | |
| download | gdb-b5c37946cce4b41af0436529b139fa3d23e61f73.zip gdb-b5c37946cce4b41af0436529b139fa3d23e61f73.tar.gz gdb-b5c37946cce4b41af0436529b139fa3d23e61f73.tar.bz2 | |
Revert "2.41 Release sources"
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d.
See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
Diffstat (limited to 'gas')
108 files changed, 4269 insertions, 2654 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 597650d..26d7dc1 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,20 +1,168 @@ -2023-07-30 Nick Clifton <nickc@redhat.com> +2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/tc-bpf.h (elf_tc_final_processing): Define. + * config/tc-bpf.c (bpf_elf_final_processing): New function. + +2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/tc-bpf.c (signed_overflow): Copy function from + tc-aarch64.c. + (encode_insn): Check for overflow in constant immediates. + (add_relaxed_insn): Pass relax argument to encode_insn. + (add_fixed_insn): Likewise. + * testsuite/gas/bpf/disp16-overflow.d: New file. + * testsuite/gas/bpf/disp16-overflow.s: Likewise. + * testsuite/gas/bpf/disp16-overflow.l: Likewise. + * testsuite/gas/bpf/disp32-overflow.d: Likewise. + * testsuite/gas/bpf/disp32-overflow.s: Likewise. + * testsuite/gas/bpf/disp32-overflow.l: Likewise. + * testsuite/gas/bpf/imm32-overflow.d: Likewise. + * testsuite/gas/bpf/imm32-overflow.s: Likewise. + * testsuite/gas/bpf/imm32-overflow.l: Likewise. + * testsuite/gas/bpf/offset16-overflow.d: Likewise. + * testsuite/gas/bpf/offset16-overflow.s: Likewise. + * testsuite/gas/bpf/offset16-overflow.l: Likewise. + * testsuite/gas/bpf/disp16-overflow-relax.d: Likewise. + * testsuite/gas/bpf/disp16-overflow-relax.l: Likewise. + * testsuite/gas/bpf/disp16-overflow-relax.s: Likewise. + * testsuite/gas/bpf/jump-relax-jump-be.d: New file. + * testsuite/gas/bpf/bpf.exp: Run new tests. + +2023-07-28 Jose E. Marchesi <jose.marchesi@oracle.com> + + PR gas/30690 + * config/tc-bpf.c (struct bpf_insn): Add fields is_relaxable and + relaxed_exp. + (enum options): Add OPTION_NO_RELAX. + (md_longopts): Likewise for -mno-relax. + (do_relax): New global. + (md_parse_option): Handle OPTION_NO_RELAX. + (RELAX_BRANCH_ENCODE): Define. + (RELAX_BRANCH_P): Likewise. + (RELAX_BRANCH_LENGTH): Likewise. + (RELAX_BRANCH_CONST): Likewise. + (RELAX_BRANCH_UNCOND): Likewise. + (relaxed_branch_length): New function. + (md_estimate_size_before_relax): Likewise. + (read_insn_word): Likewise. + (encode_int16): Likewise. + (encode_int32): Likewise. + (write_insn_bytes): Likewise. + (md_convert_frag): Likewise. + (encode_insn): Likewise. + (install_insn_fixups): Likewise. + (add_fixed_insn): Likewise. + (add_relaxed_insn): Likewise. + (md_assemble): Move instruction encoding logic to the above + new functions. + * testsuite/gas/bpf/jump-relax-ja.d: New test. + * testsuite/gas/bpf/jump-relax-ja-be.d: Likewise. + * testsuite/gas/bpf/jump-relax-ja.s: And corresponding source. + * testsuite/gas/bpf/jump-relax-jump.d: New test. + * testsuite/gas/bpf/jump-relax-jump-be.d: Likewise. + * testsuite/gas/bpf/jump-relax-jump.s: And corresponding source. + * testsuite/gas/bpf/bpf.exp: Run new tests. + * doc/c-bpf.texi (BPF Options): Document -mno-relax. + +2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> + + * testsuite/gas/bpf/alu.s: Add test for NEGI and NEG32I. + * testsuite/gas/bpf/alu32.s: Likewise. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu.d: Add expected results. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32.d: Likewise. + * testsuite/gas/bpf/alu32-be.d: Likewise. + * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. - This is the 2.41 release. - * configure: Regenerate. - * po/gas.pot: Regenerate. +2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> + + * testsuite/gas/bpf/alu.s: The register neg instruction gets only + one argument. + * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu.d: Likewise. + * testsuite/gas/bpf/alu32-be.d: Likewise. + * testsuite/gas/bpf/alu32.d: Likewise. + * testsuite/gas/bpf/alu32.s: Likewise. + * doc/c-bpf.texi (BPF Instructions): Update accordingly. + +2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> + + * doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions. + * testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions. + * testsuite/gas/bpf/alu.d: Likewise. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + +2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> + + * doc/c-bpf.texi (BPF Instructions): The pseudoc syntax for MOVS* + doesn't use `s=' but `='. + +2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> - modified: gold/po/gold.pot - modified: gprof/configure - modified: gprofng/configure - modified: gprofng/doc/version.texi - modified: gprofng/libcollector/configure - modified: ld/configure - modified: ld/po/ld.pot - modified: libiberty/functions.texi - modified: opcodes/configure - modified: opcodes/po/opcodes.pot - modified: src-release.sh + * doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS* + and LDXS* instructions. + * testsuite/gas/bpf/mem-pseudoc.d: Likewise. + * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/mem-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. + +2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/tc-bpf.c (struct bpf_insn): New field `id'. + (md_assemble): Save the ids of successfully parsed instructions + and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate. + (md_apply_fix): Adapt to the new BFD reloc. + * testsuite/gas/bpf/jump.s: Test JAL. + * testsuite/gas/bpf/jump.d: Likewise. + * testsuite/gas/bpf/jump-pseudoc.d: Likewise. + * testsuite/gas/bpf/jump-be.d: Likewise. + * testsuite/gas/bpf/jump-be-pseudoc.d: Likewise. + * doc/c-bpf.texi (BPF Instructions): Document new instruction + jal/gotol. + Document new operand type disp32. + +2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + + * testsuite/gas/bpf/mem.s: Add signed load instructions. + * testsuite/gas/bpf/mem-pseudoc.s: Likewise. + * testsuite/gas/bpf/mem.d: Likewise. + * testsuite/gas/bpf/mem-pseudoc.d: Likewise. + * testsuite/gas/bpf/mem-be.d: Likewise. + * doc/c-bpf.texi (BPF Instructions): Document the signed load + instructions. + +2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + + * testsuite/gas/bpf/alu.s: Test movs instructions. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. + * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu.d: Add expected results. + * testsuite/gas/bpf/alu32.d: Likewise. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu32-be.d: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. 2023-07-03 Nick Clifton <nickc@redhat.com> diff --git a/gas/Makefile.in b/gas/Makefile.in index 427f42d..b56cd9a 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -2230,7 +2230,7 @@ de-stage3: doc/asconfig.texi: doc/$(CONFIG).texi doc/$(am__dirstamp) $(AM_V_at)rm -f doc/asconfig.texi - $(AM_V_GEN)cp -p $(srcdir)/doc/$(CONFIG).texi doc/asconfig.texi + $(AM_V_GEN)cp $(srcdir)/doc/$(CONFIG).texi doc/asconfig.texi && touch -m -r $(srcdir)/doc/$(CONFIG).texi doc/asconfig.texi $(AM_V_at)chmod u+w doc/asconfig.texi # Maintenance @@ -1,5 +1,15 @@ -*- text -*- +* Add support for Intel PBNDKB instructions. + +* Add support for Intel SM4 instructions. + +* Add support for Intel SM3 instructions. + +* Add support for Intel SHA512 instructions. + +* Add support for Intel AVX-VNNI-INT16 instructions. + Changes in 2.41: * Add support for Intel FRED instructions. diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c index 753a929..dc05b35 100644 --- a/gas/config/obj-elf.c +++ b/gas/config/obj-elf.c @@ -1088,8 +1088,9 @@ obj_elf_attach_to_group (int dummy ATTRIBUTE_UNUSED) if (elf_group_name (now_seg)) { - as_warn (_("section %s already has a group (%s)"), - bfd_section_name (now_seg), elf_group_name (now_seg)); + if (strcmp (elf_group_name (now_seg), gname) != 0) + as_warn (_("section %s already has a group (%s)"), + bfd_section_name (now_seg), elf_group_name (now_seg)); return; } diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index 8d16cb5..d9b13a0 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -49,7 +49,7 @@ && (SUB_OPCODE (x) == 0x28)) #ifndef TARGET_WITH_CPU -#define TARGET_WITH_CPU "arc700" +#define TARGET_WITH_CPU "hs38_linux" #endif /* TARGET_WITH_CPU */ #define ARC_GET_FLAG(s) (*symbol_get_tc (s)) diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c index 3b86f9c..b4566d8 100644 --- a/gas/config/tc-bpf.c +++ b/gas/config/tc-bpf.c @@ -22,42 +22,46 @@ #include "as.h" #include "subsegs.h" #include "symcat.h" -#include "opcodes/bpf-desc.h" -#include "opcodes/bpf-opc.h" -#include "cgen.h" +#include "opcode/bpf.h" #include "elf/common.h" #include "elf/bpf.h" #include "dwarf2dbg.h" +#include "libiberty.h" #include <ctype.h> -const char comment_chars[] = ";"; +/* Data structure representing a parsed BPF instruction. */ + +struct bpf_insn +{ + enum bpf_insn_id id; + int size; /* Instruction size in bytes. */ + bpf_insn_word opcode; + uint8_t dst; + uint8_t src; + expressionS offset16; + expressionS imm32; + expressionS imm64; + expressionS disp16; + expressionS disp32; + + unsigned int has_dst : 1; + unsigned int has_src : 1; + unsigned int has_offset16 : 1; + unsigned int has_disp16 : 1; + unsigned int has_disp32 : 1; + unsigned int has_imm32 : 1; + unsigned int has_imm64 : 1; + + unsigned int is_relaxable : 1; + expressionS *relaxed_exp; +}; + +const char comment_chars[] = ";#"; const char line_comment_chars[] = "#"; const char line_separator_chars[] = "`"; const char EXP_CHARS[] = "eE"; const char FLT_CHARS[] = "fFdD"; -static const char *invalid_expression; -static char pseudoc_lex[256]; -static const char symbol_chars[] = -"_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789"; - -static const char arithm_op[] = "+-/<>%&|^"; - -static void init_pseudoc_lex (void); - -#define LEX_IS_SYMBOL_COMPONENT 1 -#define LEX_IS_WHITESPACE 2 -#define LEX_IS_NEWLINE 3 -#define LEX_IS_ARITHM_OP 4 -#define LEX_IS_STAR 6 -#define LEX_IS_CLSE_BR 7 -#define LEX_IS_OPEN_BR 8 -#define LEX_IS_EQUAL 9 -#define LEX_IS_EXCLA 10 - -#define ST_EOI 100 -#define MAX_TOKEN_SZ 100 - /* Like s_lcomm_internal in gas/read.c but the alignment string is allowed to be optional. */ @@ -110,18 +114,16 @@ const pseudo_typeS md_pseudo_table[] = -/* ISA handling. */ -static CGEN_BITSET *bpf_isa; - - - /* Command-line options processing. */ enum options { OPTION_LITTLE_ENDIAN = OPTION_MD_BASE, OPTION_BIG_ENDIAN, - OPTION_XBPF + OPTION_XBPF, + OPTION_DIALECT, + OPTION_ISA_SPEC, + OPTION_NO_RELAX, }; struct option md_longopts[] = @@ -129,6 +131,9 @@ struct option md_longopts[] = { "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN }, { "EB", no_argument, NULL, OPTION_BIG_ENDIAN }, { "mxbpf", no_argument, NULL, OPTION_XBPF }, + { "mdialect", required_argument, NULL, OPTION_DIALECT}, + { "misa-spec", required_argument, NULL, OPTION_ISA_SPEC}, + { "mno-relax", no_argument, NULL, OPTION_NO_RELAX}, { NULL, no_argument, NULL, 0 }, }; @@ -136,18 +141,39 @@ size_t md_longopts_size = sizeof (md_longopts); const char * md_shortopts = ""; -extern int target_big_endian; +/* BPF supports little-endian and big-endian variants. The following + global records what endianness to use. It can be configured using + command-line options. It defaults to the host endianness + initialized in md_begin. */ -/* Whether target_big_endian has been set while parsing command-line - arguments. */ static int set_target_endian = 0; +extern int target_big_endian; + +/* Whether to relax branch instructions. Default is yes. Can be + changed using the -mno-relax command line option. */ + +static int do_relax = 1; + +/* The ISA specification can be one of BPF_V1, BPF_V2, BPF_V3, BPF_V4 + or BPF_XPBF. The ISA spec to use can be configured using + command-line options. It defaults to the latest BPF spec. */ + +static int isa_spec = BPF_V4; + +/* The assembler supports two different dialects: "normal" syntax and + "pseudoc" syntax. The dialect to use can be configured using + command-line options. */ -static int target_xbpf = 0; +enum target_asm_dialect +{ + DIALECT_NORMAL, + DIALECT_PSEUDOC +}; -static int set_xbpf = 0; +static int asm_dialect = DIALECT_NORMAL; int -md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) +md_parse_option (int c, const char * arg) { switch (c) { @@ -156,12 +182,39 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) target_big_endian = 1; break; case OPTION_LITTLE_ENDIAN: - set_target_endian = 1; + set_target_endian = 0; target_big_endian = 0; break; + case OPTION_DIALECT: + if (strcmp (arg, "normal") == 0) + asm_dialect = DIALECT_NORMAL; + else if (strcmp (arg, "pseudoc") == 0) + asm_dialect = DIALECT_PSEUDOC; + else + as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), + arg); + break; + case OPTION_ISA_SPEC: + if (strcmp (arg, "v1") == 0) + isa_spec = BPF_V1; + else if (strcmp (arg, "v2") == 0) + isa_spec = BPF_V2; + else if (strcmp (arg, "v3") == 0) + isa_spec = BPF_V3; + else if (strcmp (arg, "v4") == 0) + isa_spec = BPF_V4; + else if (strcmp (arg, "xbpf") == 0) + isa_spec = BPF_XBPF; + else + as_fatal (_("-misa-spec=%s is not valid. Expected v1, v2, v3, v4 o xbpf"), + arg); + break; case OPTION_XBPF: - set_xbpf = 1; - target_xbpf = 1; + /* This is an alias for -misa-spec=xbpf. */ + isa_spec = BPF_XBPF; + break; + case OPTION_NO_RELAX: + do_relax = 0; break; default: return 0; @@ -175,43 +228,22 @@ md_show_usage (FILE * stream) { fprintf (stream, _("\nBPF options:\n")); fprintf (stream, _("\ - --EL generate code for a little endian machine\n\ - --EB generate code for a big endian machine\n\ - -mxbpf generate xBPF instructions\n")); +BPF options:\n\ + -EL generate code for a little endian machine\n\ + -EB generate code for a big endian machine\n\ + -mdialect=DIALECT set the assembly dialect (normal, pseudoc)\n\ + -misa-spec set the BPF ISA spec (v1, v2, v3, v4, xbpf)\n\ + -mxbpf alias for -misa-spec=xbpf\n")); } - -static void -init_pseudoc_lex (void) -{ - const char *p; - - for (p = symbol_chars; *p; ++p) - pseudoc_lex[(unsigned char) *p] = LEX_IS_SYMBOL_COMPONENT; - - pseudoc_lex[' '] = LEX_IS_WHITESPACE; - pseudoc_lex['\t'] = LEX_IS_WHITESPACE; - pseudoc_lex['\r'] = LEX_IS_WHITESPACE; - pseudoc_lex['\n'] = LEX_IS_NEWLINE; - pseudoc_lex['*'] = LEX_IS_STAR; - pseudoc_lex[')'] = LEX_IS_CLSE_BR; - pseudoc_lex['('] = LEX_IS_OPEN_BR; - pseudoc_lex[']'] = LEX_IS_CLSE_BR; - pseudoc_lex['['] = LEX_IS_OPEN_BR; - - for (p = arithm_op; *p; ++p) - pseudoc_lex[(unsigned char) *p] = LEX_IS_ARITHM_OP; - - pseudoc_lex['='] = LEX_IS_EQUAL; - pseudoc_lex['!'] = LEX_IS_EXCLA; -} +/* This function is called once, at assembler startup time. This + should set up all the tables, etc that the MD part of the assembler + needs. */ void md_begin (void) { - /* Initialize the `cgen' interface. */ - /* If not specified in the command line, use the host endianness. */ if (!set_target_endian) @@ -223,50 +255,15 @@ md_begin (void) #endif } - /* If not specified in the command line, use eBPF rather - than xBPF. */ - if (!set_xbpf) - target_xbpf = 0; - - /* Set the ISA, which depends on the target endianness. */ - bpf_isa = cgen_bitset_create (ISA_MAX); - if (target_big_endian) - { - if (target_xbpf) - cgen_bitset_set (bpf_isa, ISA_XBPFBE); - else - cgen_bitset_set (bpf_isa, ISA_EBPFBE); - } - else - { - if (target_xbpf) - cgen_bitset_set (bpf_isa, ISA_XBPFLE); - else - cgen_bitset_set (bpf_isa, ISA_EBPFLE); - } - /* Ensure that lines can begin with '*' in BPF store pseudoc instruction. */ lex_type['*'] |= LEX_BEGIN_NAME; - /* Set the machine number and endian. */ - gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN, - target_big_endian ? - CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE, - CGEN_CPU_OPEN_INSN_ENDIAN, - CGEN_ENDIAN_LITTLE, - CGEN_CPU_OPEN_ISAS, - bpf_isa, - CGEN_CPU_OPEN_END); - bpf_cgen_init_asm (gas_cgen_cpu_desc); - - /* This is a callback from cgen to gas to parse operands. */ - cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); - /* Set the machine type. */ bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf); - init_pseudoc_lex(); } +/* Round up a section size to the appropriate boundary. */ + valueT md_section_align (segT segment, valueT size) { @@ -275,6 +272,20 @@ md_section_align (segT segment, valueT size) return ((size + (1 << align) - 1) & -(1 << align)); } +/* Return non-zero if the indicated VALUE has overflowed the maximum + range expressible by an signed number with the indicated number of + BITS. */ + +static bool +signed_overflow (offsetT value, unsigned bits) +{ + offsetT lim; + if (bits >= sizeof (offsetT) * 8) + return false; + lim = (offsetT) 1 << (bits - 1); + return (value < -lim || value >= lim); +} + /* Functions concerning relocs. */ @@ -310,34 +321,194 @@ md_number_to_chars (char * buf, valueT val, int n) } arelent * -tc_gen_reloc (asection *sec, fixS *fix) +tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixP) { - return gas_cgen_tc_gen_reloc (sec, fix); + bfd_reloc_code_real_type r_type = fixP->fx_r_type; + arelent *reloc; + + reloc = XNEW (arelent); + + if (fixP->fx_pcrel) + { + r_type = (r_type == BFD_RELOC_8 ? BFD_RELOC_8_PCREL + : r_type == BFD_RELOC_16 ? BFD_RELOC_16_PCREL + : r_type == BFD_RELOC_24 ? BFD_RELOC_24_PCREL + : r_type == BFD_RELOC_32 ? BFD_RELOC_32_PCREL + : r_type == BFD_RELOC_64 ? BFD_RELOC_64_PCREL + : r_type); + } + + reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type); + + if (reloc->howto == (reloc_howto_type *) NULL) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("relocation is not supported")); + return NULL; + } + + //XXX gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); + + reloc->sym_ptr_ptr = XNEW (asymbol *); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); + + /* Use fx_offset for these cases. */ + if (fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY + || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) + reloc->addend = fixP->fx_offset; + else + reloc->addend = fixP->fx_addnumber; + + reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; + return reloc; } -/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. This - is called when the operand is an expression that couldn't be fully - resolved. Returns BFD_RELOC_NONE if no reloc type can be found. - *FIXP may be modified if desired. */ + +/* Relaxations supported by this assembler. */ + +#define RELAX_BRANCH_ENCODE(uncond, constant, length) \ + ((relax_substateT) \ + (0xc0000000 \ + | ((uncond) ? 1 : 0) \ + | ((constant) ? 2 : 0) \ + | ((length) << 2))) + +#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) +#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xff) +#define RELAX_BRANCH_CONST(i) (((i) & 2) != 0) +#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) -bfd_reloc_code_real_type -md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, - const CGEN_OPERAND *operand, - fixS *fixP) + +/* Compute the length of a branch seuqence, and adjust the stored + length accordingly. If FRAG is NULL, the worst-case length is + returned. */ + +static unsigned +relaxed_branch_length (fragS *fragp, asection *sec, int update) { - switch (operand->type) + int length, uncond; + + if (!fragp) + return 8 * 3; + + uncond = RELAX_BRANCH_UNCOND (fragp->fr_subtype); + length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); + + if (uncond) + /* Length is the same for both JA and JAL. */ + length = 8; + else { - case BPF_OPERAND_IMM64: - return BFD_RELOC_BPF_64; - case BPF_OPERAND_DISP32: - fixP->fx_pcrel = 1; - return BFD_RELOC_BPF_DISP32; - default: - break; + if (RELAX_BRANCH_CONST (fragp->fr_subtype)) + { + int64_t val = fragp->fr_offset; + + if (val < -32768 || val > 32767) + length = 8 * 3; + else + length = 8; + } + else if (fragp->fr_symbol != NULL + && S_IS_DEFINED (fragp->fr_symbol) + && !S_IS_WEAK (fragp->fr_symbol) + && sec == S_GET_SEGMENT (fragp->fr_symbol)) + { + offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; + + /* Convert to 64-bit words, minus one. */ + val = (val - 8) / 8; + + /* See if it fits in the signed 16-bits field. */ + if (val < -32768 || val > 32767) + length = 8 * 3; + else + length = 8; + } + else + /* Use short version, and let the linker relax instead, if + appropriate and if supported. */ + length = 8; } - return BFD_RELOC_NONE; + + if (update) + fragp->fr_subtype = RELAX_BRANCH_ENCODE (uncond, + RELAX_BRANCH_CONST (fragp->fr_subtype), + length); + + return length; } - + +/* Estimate the size of a variant frag before relaxing. */ + +int +md_estimate_size_before_relax (fragS *fragp, asection *sec) +{ + return (fragp->fr_var = relaxed_branch_length (fragp, sec, true)); +} + +/* Read a BPF instruction word from BUF. */ + +static uint64_t +read_insn_word (bfd_byte *buf) +{ + return bfd_getb64 (buf); +} + +/* Write the given signed 16-bit value in the given BUFFER using the + target endianness. */ + +static void +encode_int16 (int16_t value, char *buffer) +{ + uint16_t val = value; + + if (target_big_endian) + { + buffer[0] = (val >> 8) & 0xff; + buffer[1] = val & 0xff; + } + else + { + buffer[1] = (val >> 8) & 0xff; + buffer[0] = val & 0xff; + } +} + +/* Write the given signed 32-bit value in the given BUFFER using the + target endianness. */ + +static void +encode_int32 (int32_t value, char *buffer) +{ + uint32_t val = value; + + if (target_big_endian) + { + buffer[0] = (val >> 24) & 0xff; + buffer[1] = (val >> 16) & 0xff; + buffer[2] = (val >> 8) & 0xff; + buffer[3] = val & 0xff; + } + else + { + buffer[3] = (val >> 24) & 0xff; + buffer[2] = (val >> 16) & 0xff; + buffer[1] = (val >> 8) & 0xff; + buffer[0] = value & 0xff; + } +} + +/* Write a BPF instruction to BUF. */ + +static void +write_insn_bytes (bfd_byte *buf, char *bytes) +{ + int i; + + for (i = 0; i < 8; ++i) + md_number_to_chars ((char *) buf + i, (valueT) bytes[i], 1); +} + /* *FRAGP has been relaxed to its final size, and now needs to have the bytes inside it modified to conform to the new size. @@ -348,35 +519,258 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, void md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, - fragS *fragP ATTRIBUTE_UNUSED) + fragS *fragp ATTRIBUTE_UNUSED) { - as_fatal (_("convert_frag called")); -} + bfd_byte *buf = (bfd_byte *) fragp->fr_literal + fragp->fr_fix; + expressionS exp; + fixS *fixp; + bpf_insn_word word; + int disp_is_known = 0; + int64_t disp_to_target = 0; -int -md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, - segT segment ATTRIBUTE_UNUSED) -{ - as_fatal (_("estimate_size_before_relax called")); - return 0; + uint64_t code; + + gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); + + /* Expression to be used in any resulting relocation in the relaxed + instructions. */ + exp.X_op = O_symbol; + exp.X_add_symbol = fragp->fr_symbol; + exp.X_add_number = fragp->fr_offset; + + gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); + + /* Read an instruction word from the instruction to be relaxed, and + get the code. */ + word = read_insn_word (buf); + code = (word >> 60) & 0xf; + + /* Determine whether the 16-bit displacement to the target is known + at this point. */ + if (RELAX_BRANCH_CONST (fragp->fr_subtype)) + { + disp_to_target = fragp->fr_offset; + disp_is_known = 1; + } + else if (fragp->fr_symbol != NULL + && S_IS_DEFINED (fragp->fr_symbol) + && !S_IS_WEAK (fragp->fr_symbol) + && sec == S_GET_SEGMENT (fragp->fr_symbol)) + { + offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; + /* Convert to 64-bit blocks minus one. */ + disp_to_target = (val - 8) / 8; + disp_is_known = 1; + } + + /* The displacement should fit in a signed 32-bit number. */ + if (disp_is_known && signed_overflow (disp_to_target, 32)) + as_bad_where (fragp->fr_file, fragp->fr_line, + _("signed instruction operand out of range, shall fit in 32 bits")); + + /* Now relax particular jump instructions. */ + if (code == BPF_CODE_JA) + { + /* Unconditional jump. + JA d16 -> JAL d32 */ + + gas_assert (RELAX_BRANCH_UNCOND (fragp->fr_subtype)); + + if (disp_is_known) + { + if (disp_to_target >= -32768 && disp_to_target <= 32767) + { + /* 16-bit disp is known and in range. Install a fixup + for the disp16 if the branch value is not constant. + This will be resolved by the assembler and units + converted. */ + + if (!RELAX_BRANCH_CONST (fragp->fr_subtype)) + { + /* Install fixup for the JA. */ + reloc_howto_type *reloc_howto + = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort(); + + fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, + bfd_get_reloc_size (reloc_howto), + &exp, + reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + } + } + else + { + /* 16-bit disp is known and not in range. Turn the JA + into a JAL with a 32-bit displacement. */ + char bytes[8]; + + bytes[0] = ((BPF_CLASS_JMP32|BPF_CODE_JA|BPF_SRC_K) >> 56) & 0xff; + bytes[1] = (word >> 48) & 0xff; + bytes[2] = 0; /* disp16 high */ + bytes[3] = 0; /* disp16 lo */ + encode_int32 ((int32_t) disp_to_target, bytes + 4); + + write_insn_bytes (buf, bytes); + } + } + else + { + /* The displacement to the target is not known. Do not + relax. The linker will maybe do it if it chooses to. */ + + reloc_howto_type *reloc_howto = NULL; + + gas_assert (!RELAX_BRANCH_CONST (fragp->fr_subtype)); + + /* Install fixup for the JA. */ + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort (); + + fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, + bfd_get_reloc_size (reloc_howto), + &exp, + reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + } + + buf += 8; + } + else + { + /* Conditional jump. + JXX d16 -> JXX +1; JA +1; JAL d32 */ + + gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); + + if (disp_is_known) + { + if (disp_to_target >= -32768 && disp_to_target <= 32767) + { + /* 16-bit disp is known and in range. Install a fixup + for the disp16 if the branch value is not constant. + This will be resolved by the assembler and units + converted. */ + + if (!RELAX_BRANCH_CONST (fragp->fr_subtype)) + { + /* Install fixup for the branch. */ + reloc_howto_type *reloc_howto + = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort(); + + fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, + bfd_get_reloc_size (reloc_howto), + &exp, + reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + } + + buf += 8; + } + else + { + /* 16-bit disp is known and not in range. Turn the JXX + into a sequence JXX +1; JA +1; JAL d32. */ + + char bytes[8]; + + /* First, set the 16-bit offset in the current + instruction to 1. */ + + if (target_big_endian) + bfd_putb16 (1, buf + 2); + else + bfd_putl16 (1, buf + 2); + buf += 8; + + /* Then, write the JA + 1 */ + + bytes[0] = 0x05; /* JA */ + bytes[1] = 0x0; + encode_int16 (1, bytes + 2); + bytes[4] = 0x0; + bytes[5] = 0x0; + bytes[6] = 0x0; + bytes[7] = 0x0; + write_insn_bytes (buf, bytes); + buf += 8; + + /* Finally, write the JAL to the target. */ + + bytes[0] = ((BPF_CLASS_JMP32|BPF_CODE_JA|BPF_SRC_K) >> 56) & 0xff; + bytes[1] = 0; + bytes[2] = 0; + bytes[3] = 0; + encode_int32 ((int32_t) disp_to_target, bytes + 4); + write_insn_bytes (buf, bytes); + buf += 8; + } + } + else + { + /* The displacement to the target is not known. Do not + relax. The linker will maybe do it if it chooses to. */ + + reloc_howto_type *reloc_howto = NULL; + + gas_assert (!RELAX_BRANCH_CONST (fragp->fr_subtype)); + + /* Install fixup for the conditional jump. */ + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort (); + + fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, + bfd_get_reloc_size (reloc_howto), + &exp, + reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + buf += 8; + } + } + + gas_assert (buf == (bfd_byte *)fragp->fr_literal + + fragp->fr_fix + fragp->fr_var); + + fragp->fr_fix += fragp->fr_var; } +/* Apply a fixS (fixup of an instruction or data that we didn't have + enough info to complete immediately) to the data in a frag. */ + void -md_apply_fix (fixS *fixP, valueT *valP, segT seg) +md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) { - /* Some fixups for instructions require special attention. This is - handled in the code block below. */ - if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) + char *where = fixP->fx_frag->fr_literal + fixP->fx_where; + + switch (fixP->fx_r_type) { - int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; - const CGEN_OPERAND *operand = cgen_operand_lookup_by_num (gas_cgen_cpu_desc, - opindex); - char *where; + case BFD_RELOC_BPF_DISP16: + /* Convert from bytes to number of 64-bit words to the target, + minus one. */ + *valP = (((long) (*valP)) - 8) / 8; + break; + case BFD_RELOC_BPF_DISPCALL32: + case BFD_RELOC_BPF_DISP32: + /* Convert from bytes to number of 64-bit words to the target, + minus one. */ + *valP = (((long) (*valP)) - 8) / 8; - switch (operand->type) + if (fixP->fx_r_type == BFD_RELOC_BPF_DISPCALL32) { - case BPF_OPERAND_DISP32: /* eBPF supports two kind of CALL instructions: the so called pseudo calls ("bpf to bpf") and external calls ("bpf to kernel"). @@ -396,1522 +790,852 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) Note that the CALL instruction has only one operand, so this code is executed only once per instruction. */ - where = fixP->fx_frag->fr_literal + fixP->fx_where + 1; - where[0] = target_big_endian ? 0x01 : 0x10; - /* Fallthrough. */ - case BPF_OPERAND_DISP16: - /* The PC-relative displacement fields in jump instructions - shouldn't be in bytes. Instead, they hold the number of - 64-bit words to the target, _minus one_. */ - *valP = (((long) (*valP)) - 8) / 8; - break; - default: - break; + md_number_to_chars (where + 1, target_big_endian ? 0x01 : 0x10, 1); } + break; + case BFD_RELOC_16_PCREL: + /* Convert from bytes to number of 64-bit words to the target, + minus one. */ + *valP = (((long) (*valP)) - 8) / 8; + break; + default: + break; } - /* And now invoke CGEN's handler, which will eventually install - *valP into the corresponding operand. */ - gas_cgen_md_apply_fix (fixP, valP, seg); -} - -/* - The BPF pseudo grammar: - - instruction : bpf_alu_insn - | bpf_alu32_insn - | bpf_jump_insn - | bpf_load_store_insn - | bpf_load_store32_insn - | bpf_non_generic_load - | bpf_endianness_conv_insn - | bpf_64_imm_load_insn - | bpf_atomic_insn - ; - - bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32 - ; - - bpf_alu32_insn : BPF_REG32 bpf_alu_operator register32_or_imm32 - ; - - bpf_jump_insn : BPF_JA offset - | IF BPF_REG bpf_jump_operator register_or_imm32 BPF_JA offset - | IF BPF_REG32 bpf_jump_operator register_or_imm32 BPF_JA offset - | BPF_CALL offset - | BPF_EXIT - ; - - bpf_load_store_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \ - register_and_offset BPF_CHR_CLSE_BR - | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG - ; - - bpf_load_store32_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \ - register32_and_offset BPF_CHR_CLSE_BR - | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG32 - ; - - bpf_non_generic_load : BPF_REG_R0 CHR_EQUAL bpf_size_cast BPF_LD BPF_CHR_OPEN_BR \ - imm32 BPF_CHR_CLSE_BR - ; - - bpf_endianness_conv_insn : BPF_REG_N bpf_endianness_mnem BPF_REG_N - ; - - bpf_64_imm_load_insn : BPF_REG imm64 BPF_LL - ; - - bpf_atomic_insn : BPF_LOCK bpf_size_cast_32_64 register_and_offset BPF_ADD BPF_REG - - register_and_offset : BPF_CHR_OPEN_BR BPF_REG offset BPF_CHR_CLSE_BR - ; - - register32_and_offset : BPF_CHR_OPEN_BR BPF_REG32 offset BPF_CHR_CLSE_BR - ; - - bpf_size_cast : CHR_START BPF_CHR_OPEN_BR bpf_size CHR_START BPF_CHR_CLSE_BR - ; - - bpf_size_cast_32_64 : CHR_START BPF_CHR_OPEN_BR bpf_size_cast_32_64 CHR_STAR BPF_CHR_CLSE_BR - ; - - bpf_size_32_64 : BPF_CAST_U32 - | BPF_CAST_U64 - ; - - bpf_size : BPF_CAST_U8 - | BPF_CAST_U16 - | BPF_CAST_U32 - | BPF_CAST_U64 - ; - - bpf_jump_operator : BPF_JEQ - | BPF_JGT - | BPF_JGE - | BPF_JNE - | BPF_JSGT - | BPF_JSGE - | BPF_JLT - | BPF_JLE - | BPF_JSLT - | BPF_JSLE - ; - - bpf_alu_operator : BPF_ADD - | BPF_SUB - | BPF_MUL - | BPF_DIV - | BPF_OR - | BPF_AND - | BPF_LSH - | BPF_RSH - | BPF_NEG - | BPF_MOD - | BPF_XOR - | BPF_ARSH - | CHR_EQUAL - ; - - bpf_endianness_mnem : BPF_LE16 - | BPF_LE32 - | BPF_LE64 - | BPF_BE16 - | BPF_BE32 - | BPF_BE64 - ; - - offset : BPF_EXPR - | BPF_SYMBOL - ; - - register_or_imm32 : BPF_REG - | expression - ; - - register32_or_imm32 : BPF_REG32 - | expression - ; - - imm32 : BPF_EXPR - | BPF_SYMBOL - ; - - imm64 : BPF_EXPR - | BPF_SYMBOL - ; - - register_or_expression : BPF_EXPR - | BPF_REG - ; - - BPF_EXPR : GAS_EXPR - -*/ - -enum bpf_token_type - { - /* Keep grouped to quickly access. */ - BPF_ADD, - BPF_SUB, - BPF_MUL, - BPF_DIV, - BPF_OR, - BPF_AND, - BPF_LSH, - BPF_RSH, - BPF_MOD, - BPF_XOR, - BPF_MOV, - BPF_ARSH, - BPF_NEG, - - BPF_REG, - - BPF_IF, - BPF_GOTO, - - /* Keep grouped to quickly access. */ - BPF_JEQ, - BPF_JGT, - BPF_JGE, - BPF_JLT, - BPF_JLE, - BPF_JSET, - BPF_JNE, - BPF_JSGT, - BPF_JSGE, - BPF_JSLT, - BPF_JSLE, - - BPF_SYMBOL, - BPF_CHR_CLSE_BR, - BPF_CHR_OPEN_BR, - - /* Keep grouped to quickly access. */ - BPF_CAST_U8, - BPF_CAST_U16, - BPF_CAST_U32, - BPF_CAST_U64, - - /* Keep grouped to quickly access. */ - BPF_LE16, - BPF_LE32, - BPF_LE64, - BPF_BE16, - BPF_BE32, - BPF_BE64, - - BPF_LOCK, - - BPF_IND_CALL, - BPF_LD, - BPF_LL, - BPF_EXPR, - BPF_UNKNOWN, - }; - -static int -valid_expr (const char *e, const char **end_expr) -{ - invalid_expression = NULL; - char *hold = input_line_pointer; - expressionS exp; + if (fixP->fx_addsy == (symbolS *) NULL) + fixP->fx_done = 1; - input_line_pointer = (char *) e; - deferred_expression (&exp); - *end_expr = input_line_pointer; - input_line_pointer = hold; + if (fixP->fx_done) + { + /* We're finished with this fixup. Install it because + bfd_install_relocation won't be called to do it. */ + switch (fixP->fx_r_type) + { + case BFD_RELOC_8: + md_number_to_chars (where, *valP, 1); + break; + case BFD_RELOC_16: + md_number_to_chars (where, *valP, 2); + break; + case BFD_RELOC_32: + md_number_to_chars (where, *valP, 4); + break; + case BFD_RELOC_64: + md_number_to_chars (where, *valP, 8); + break; + case BFD_RELOC_BPF_DISP16: + md_number_to_chars (where + 2, (uint16_t) *valP, 2); + break; + case BFD_RELOC_BPF_DISP32: + case BFD_RELOC_BPF_DISPCALL32: + md_number_to_chars (where + 4, (uint32_t) *valP, 4); + break; + case BFD_RELOC_16_PCREL: + md_number_to_chars (where + 2, (uint32_t) *valP, 2); + break; + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("internal error: can't install fix for reloc type %d (`%s')"), + fixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type)); + break; + } + } - return invalid_expression == NULL; + /* Tuck `value' away for use by tc_gen_reloc. + See the comment describing fx_addnumber in write.h. + This field is misnamed (or misused :-). */ + fixP->fx_addnumber = *valP; } -static char * -build_bpf_non_generic_load (char *src, enum bpf_token_type cast, - const char *imm32) -{ - char *bpf_insn; - static const char *cast_rw[] = {"b", "h", "w", "dw"}; - - bpf_insn = xasprintf ("%s%s%s %s%s%s%s", - "ld", - src ? "ind" : "abs", - cast_rw[cast - BPF_CAST_U8], - src ? "%" : "", - src ? src : "", - src ? "," : "", - imm32); - return bpf_insn; -} + +/* Instruction writing routines. */ -static char * -build_bpf_atomic_insn (char *dst, char *src, - enum bpf_token_type atomic_insn, - enum bpf_token_type cast, - const char *offset) -{ - char *bpf_insn; - static const char *cast_rw[] = {"w", "dw"}; - static const char *mnem[] = {"xadd"}; - - bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", mnem[atomic_insn - BPF_ADD], - cast_rw[cast - BPF_CAST_U32], dst, - *offset != '+' ? "+" : "", - offset, src); - return bpf_insn; -} +/* Encode a BPF instruction in the given buffer BYTES. Non-constant + immediates are encoded as zeroes. */ -static char * -build_bpf_jmp_insn (char *dst, char *src, - char *imm32, enum bpf_token_type op, - const char *sym, const char *offset) +static void +encode_insn (struct bpf_insn *insn, char *bytes, int relaxed) { - char *bpf_insn; - static const char *mnem[] = - { - "jeq", "jgt", "jge", "jlt", - "jle", "jset", "jne", "jsgt", - "jsge", "jslt", "jsle" - }; - - const char *in32 = (*dst == 'w' ? "32" : ""); - - *dst = 'r'; - if (src) - *src = 'r'; - - bpf_insn = xasprintf ("%s%s %%%s,%s%s,%s", - mnem[op - BPF_JEQ], in32, dst, - src ? "%" : "", - src ? src : imm32, - offset ? offset : sym); - return bpf_insn; -} + uint8_t src, dst; -static char * -build_bpf_arithm_insn (char *dst, char *src, - int load64, const char *imm32, - enum bpf_token_type type) -{ - char *bpf_insn; - static const char *mnem[] = + /* Zero all the bytes. */ + memset (bytes, 0, 16); + + /* First encode the opcodes. Note that we have to handle the + endianness groups of the BPF instructions: 8 | 4 | 4 | 16 | + 32. */ + if (target_big_endian) { - "add", "sub", "mul", "div", - "or", "and", "lsh", "rsh", - "mod", "xor", "mov", "arsh", - "neg", - }; - const char *in32 = (*dst == 'w' ? "32" : ""); - - *dst = 'r'; - if (src) - *src = 'r'; - - if (type == BPF_NEG) - bpf_insn = xasprintf ("%s%s %%%s", mnem[type - BPF_ADD], in32, dst); - else if (load64) - bpf_insn = xasprintf ("%s %%%s,%s", "lddw", dst, imm32); + /* code */ + bytes[0] = (insn->opcode >> 56) & 0xff; + /* regs */ + bytes[1] = (insn->opcode >> 48) & 0xff; + /* offset16 */ + bytes[2] = (insn->opcode >> 40) & 0xff; + bytes[3] = (insn->opcode >> 32) & 0xff; + /* imm32 */ + bytes[4] = (insn->opcode >> 24) & 0xff; + bytes[5] = (insn->opcode >> 16) & 0xff; + bytes[6] = (insn->opcode >> 8) & 0xff; + bytes[7] = insn->opcode & 0xff; + } else - bpf_insn = xasprintf ("%s%s %%%s,%s%s", mnem[type - BPF_ADD], - in32, dst, - src ? "%" : "", - src ? src: imm32); - return bpf_insn; -} + { + /* code */ + bytes[0] = (insn->opcode >> 56) & 0xff; + /* regs */ + bytes[1] = (((((insn->opcode >> 48) & 0xff) & 0xf) << 4) + | (((insn->opcode >> 48) & 0xff) & 0xf)); + /* offset16 */ + bytes[3] = (insn->opcode >> 40) & 0xff; + bytes[2] = (insn->opcode >> 32) & 0xff; + /* imm32 */ + bytes[7] = (insn->opcode >> 24) & 0xff; + bytes[6] = (insn->opcode >> 16) & 0xff; + bytes[5] = (insn->opcode >> 8) & 0xff; + bytes[4] = insn->opcode & 0xff; + } -static char * -build_bpf_endianness (char *dst, enum bpf_token_type endianness) -{ - char *bpf_insn; - static const char *size[] = {"16", "32", "64"}; - int be = 1; - - if (endianness == BPF_LE16 - || endianness == BPF_LE32 - || endianness == BPF_LE64) - be = 0; + /* Now the registers. */ + src = insn->has_src ? insn->src : 0; + dst = insn->has_dst ? insn->dst : 0; + + if (target_big_endian) + bytes[1] = ((dst & 0xf) << 4) | (src & 0xf); else - gas_assert (endianness == BPF_BE16 || endianness == BPF_BE32 || endianness == BPF_BE64); + bytes[1] = ((src & 0xf) << 4) | (dst & 0xf); - bpf_insn = xasprintf ("%s %%%s,%s", be ? "endbe" : "endle", - dst, be ? size[endianness - BPF_BE16] : size[endianness - BPF_LE16]); - return bpf_insn; -} + /* Now the immediates that are known to be constant. */ -static char * -build_bpf_load_store_insn (char *dst, char *src, - enum bpf_token_type cast, - const char *offset, int isload) -{ - char *bpf_insn; - static const char *cast_rw[] = {"b", "h", "w", "dw"}; - - *dst = *src = 'r'; - if (isload) - bpf_insn = xasprintf ("%s%s %%%s,[%%%s%s%s]", "ldx", - cast_rw[cast - BPF_CAST_U8], dst, src, - *offset != '+' ? "+" : "", - offset); - else - bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", "stx", - cast_rw[cast - BPF_CAST_U8], dst, - *offset != '+' ? "+" : "", - offset, src); - return bpf_insn; -} + if (insn->has_imm32 && insn->imm32.X_op == O_constant) + { + int64_t imm = insn->imm32.X_add_number; -static int -look_for_reserved_word (const char *token, enum bpf_token_type *type) -{ - int i; - static struct - { - const char *name; - enum bpf_token_type type; - } reserved_words[] = + if (signed_overflow (imm, 32)) + as_bad (_("signed immediate out of range, shall fit in 32 bits")); + else + encode_int32 (insn->imm32.X_add_number, bytes + 4); + } + + if (insn->has_disp32 && insn->disp32.X_op == O_constant) { - { - .name = "if", - .type = BPF_IF - }, - { - .name = "goto", - .type = BPF_GOTO - }, - { - .name = "le16", - .type = BPF_LE16 - }, - { - .name = "le32", - .type = BPF_LE32 - }, - { - .name = "le64", - .type = BPF_LE64 - }, - { - .name = "be16", - .type = BPF_BE16 - }, - { - .name = "be32", - .type = BPF_BE32 - }, - { - .name = "be64", - .type = BPF_BE64 - }, - { - .name = "lock", - .type = BPF_LOCK - }, - { - .name = "callx", - .type = BPF_IND_CALL - }, - { - .name = "skb", - .type = BPF_LD - }, - { - .name = "ll", - .type = BPF_LL - }, - { - .name = NULL, - } - }; - - for (i = 0; reserved_words[i].name; ++i) - if (*reserved_words[i].name == *token - && !strcmp (reserved_words[i].name, token)) - { - *type = reserved_words[i].type; - return 1; - } + int64_t disp = insn->disp32.X_add_number; - return 0; -} + if (signed_overflow (disp, 32)) + as_bad (_("signed pc-relative offset out of range, shall fit in 32 bits")); + else + encode_int32 (insn->disp32.X_add_number, bytes + 4); + } -static int -is_register (const char *token, int len) -{ - if (token[0] == 'r' || token[0] == 'w') - if ((len == 2 && isdigit (token[1])) - || (len == 3 && token[1] == '1' && token[2] == '0')) - return 1; + if (insn->has_offset16 && insn->offset16.X_op == O_constant) + { + int64_t offset = insn->offset16.X_add_number; - return 0; -} + if (signed_overflow (offset, 16)) + as_bad (_("signed pc-relative offset out of range, shall fit in 16 bits")); + else + encode_int16 (insn->offset16.X_add_number, bytes + 2); + } -static enum bpf_token_type -is_cast (const char *token) -{ - static const char *cast_rw[] = {"u8", "u16", "u32", "u64"}; - unsigned int i; + if (insn->has_disp16 && insn->disp16.X_op == O_constant) + { + int64_t disp = insn->disp16.X_add_number; + + if (!relaxed && signed_overflow (disp, 16)) + as_bad (_("signed pc-relative offset out of range, shall fit in 16 bits")); + else + encode_int16 (insn->disp16.X_add_number, bytes + 2); + } - for (i = 0; i < ARRAY_SIZE (cast_rw); ++i) - if (!strcmp (token, cast_rw[i])) - return BPF_CAST_U8 + i; + if (insn->has_imm64 && insn->imm64.X_op == O_constant) + { + uint64_t imm64 = insn->imm64.X_add_number; - return BPF_UNKNOWN; + if (target_big_endian) + { + bytes[12] = (imm64 >> 56) & 0xff; + bytes[13] = (imm64 >> 48) & 0xff; + bytes[14] = (imm64 >> 40) & 0xff; + bytes[15] = (imm64 >> 32) & 0xff; + bytes[4] = (imm64 >> 24) & 0xff; + bytes[5] = (imm64 >> 16) & 0xff; + bytes[6] = (imm64 >> 8) & 0xff; + bytes[7] = imm64 & 0xff; + } + else + { + bytes[15] = (imm64 >> 56) & 0xff; + bytes[14] = (imm64 >> 48) & 0xff; + bytes[13] = (imm64 >> 40) & 0xff; + bytes[12] = (imm64 >> 32) & 0xff; + bytes[7] = (imm64 >> 24) & 0xff; + bytes[6] = (imm64 >> 16) & 0xff; + bytes[5] = (imm64 >> 8) & 0xff; + bytes[4] = imm64 & 0xff; + } + } } -static enum bpf_token_type -get_token (const char **insn, char *token, size_t *tlen) +/* Install the fixups in INSN in their proper location in the + specified FRAG at the location pointed by WHERE. */ + +static void +install_insn_fixups (struct bpf_insn *insn, fragS *frag, long where) { -#define GET() \ - (*str == '\0' \ - ? EOF \ - : *(unsigned char *)(str++)) - -#define UNGET() (--str) - -#define START_EXPR() \ - do \ - { \ - if (expr == NULL) \ - expr = str - 1; \ - } while (0) - -#define SCANNER_SKIP_WHITESPACE() \ - do \ - { \ - do \ - ch = GET (); \ - while (ch != EOF \ - && ((ch) == ' ' || (ch) == '\t')); \ - if (ch != EOF) \ - UNGET (); \ - } while (0) - - const char *str = *insn; - int ch, ch2 = 0; - enum bpf_token_type ttype = BPF_UNKNOWN; - size_t len = 0; - const char *expr = NULL; - const char *end_expr = NULL; - int state = 0; - int return_token = 0; - - while (1) + if (insn->has_imm64) { - ch = GET (); - - if (ch == EOF || len > MAX_TOKEN_SZ) - break; - - switch (pseudoc_lex[(unsigned char) ch]) - { - case LEX_IS_WHITESPACE: - SCANNER_SKIP_WHITESPACE (); - return_token = 1; - - switch (state) - { - case 12: /* >' ' */ - ttype = BPF_JGT; - break; - - case 17: /* ==' ' */ - ttype = BPF_JEQ; - break; - - case 18: /* <' ' */ - ttype = BPF_JLT; - break; - - case 20: /* &' ' */ - ttype = BPF_JSET; - break; - - case 22: /* s<' '*/ - ttype = BPF_JSLT; - break; - - case 14: /* s> ' ' */ - ttype = BPF_JSGT; - break; - - case 16: /* =' ' */ - ttype = BPF_MOV; - break; - - default: - return_token = 0; - } - break; + switch (insn->imm64.X_op) + { + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_64); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag, where, + size, &insn->imm64, reloc_howto->pc_relative, + BFD_RELOC_BPF_64); + break; + } + case O_constant: + /* Already handled in encode_insn. */ + break; + default: + abort (); + } + } - case LEX_IS_EXCLA: - token[len++] = ch; - state = 21; - break; + if (insn->has_imm32) + { + switch (insn->imm32.X_op) + { + case O_symbol: + case O_subtract: + case O_add: + case O_uminus: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag, where + 4, + size, &insn->imm32, reloc_howto->pc_relative, + BFD_RELOC_32); + break; + } + case O_constant: + /* Already handled in encode_insn. */ + break; + default: + abort (); + } + } - case LEX_IS_ARITHM_OP: - if (state == 16) - { - /* ='-' is handle as '=' */ - UNGET (); - ttype = BPF_MOV; - return_token = 1; - break; - } - - START_EXPR(); - token[len++] = ch; - switch (ch) - { -#define BPF_ARITHM_OP(op, type) \ - case (op): \ - state = 6; \ - ttype = (type); \ - break; - - BPF_ARITHM_OP('+', BPF_ADD); - BPF_ARITHM_OP('-', BPF_SUB); - BPF_ARITHM_OP('*', BPF_MUL); - BPF_ARITHM_OP('/', BPF_DIV); - BPF_ARITHM_OP('|', BPF_OR); - BPF_ARITHM_OP('%', BPF_MOD); - BPF_ARITHM_OP('^', BPF_XOR); - - case '&': - state = 20; /* '&' */ - break; - - case '<': - switch (state) - { - case 0: - state = 18; /* '<' */ - break; - - case 18: - state = 19; /* <'<' */ - break; - - case 8: - state = 22; /* s'<' */ - break; - } - break; - - case '>': - switch (state) - { - case 0: - state = 12; /* '>' */ - break; - - case 12: - state = 13; /* >'>' */ - break; - - case 8: - state = 14; /* s'>' */ - break; - - case 14: - state = 15; /* s>'>' */ - break; - } - break; - } - break; + if (insn->has_disp32) + { + switch (insn->disp32.X_op) + { + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + unsigned int bfd_reloc + = (insn->id == BPF_INSN_CALL + ? BFD_RELOC_BPF_DISPCALL32 + : BFD_RELOC_BPF_DISP32); + + reloc_howto = bfd_reloc_type_lookup (stdoutput, bfd_reloc); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag, where, + size, &insn->disp32, reloc_howto->pc_relative, + bfd_reloc); + break; + } + case O_constant: + /* Already handled in encode_insn. */ + break; + default: + abort (); + } + } - case LEX_IS_STAR: - switch (state) - { - case 0: - token[len++] = ch; - START_EXPR (); - state = 2; /* '*', It could be the fist cast char. */ - break; - - case 16: /* ='*' Not valid token. */ - ttype = BPF_MOV; - return_token = 1; - UNGET (); - break; - - case 4: /* *(uXX'*' */ - token[len++] = ch; - state = 5; - break; - } - break; + if (insn->has_offset16) + { + switch (insn->offset16.X_op) + { + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + + /* XXX we really need a new pc-rel offset in bytes + relocation for this. */ + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag, where, + size, &insn->offset16, reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + break; + } + case O_constant: + /* Already handled in encode_insn. */ + break; + default: + abort (); + } + } - case LEX_IS_OPEN_BR: - START_EXPR (); - token[len++] = ch; - return_token = 1; - - switch (state) - { - case 2: - state = 3; /* *'(' second char of a cast or expr. */ - return_token = 0; - break; - - case 6: - if (valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - memcpy (token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - { - len = 0; - while (*invalid_expression) - token[len++] = *invalid_expression++; - - token[len] = 0; - ttype = BPF_UNKNOWN; - } - break; - - default: - ttype = BPF_CHR_OPEN_BR; - SCANNER_SKIP_WHITESPACE (); - ch2 = GET (); - - if ((isdigit (ch2) || ch2 == '(') - && valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - memcpy (token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - UNGET (); - } - break; + if (insn->has_disp16) + { + switch (insn->disp16.X_op) + { + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag, where, + size, &insn->disp16, reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + break; + } + case O_constant: + /* Already handled in encode_insn. */ + break; + default: + abort (); + } + } - case LEX_IS_CLSE_BR: - token[len++] = ch; +} - if (state == 0) - { - ttype = BPF_CHR_CLSE_BR; - return_token = 1; - } - else if (state == 5) /* *(uXX*')' */ - return_token = 1; - break; +/* Add a new insn to the list of instructions. */ - case LEX_IS_EQUAL: - token[len++] = ch; - return_token = 1; - - switch (state) - { - case 0: - state = 16; /* '=' */ - return_token = 0; - break; - - case 16: - state = 17; /* ='=' */ - return_token = 0; - break; - - case 2: /* *'=' */ - ttype = BPF_MUL; - break; - - case 10: /* s>>'=' */ - ttype = BPF_ARSH; - break; - - case 12: /* >'=' */ - ttype = BPF_JGE; - break; - - case 13: /* >>'=' */ - ttype = BPF_RSH; - break; - - case 14: /* s>'=' */ - ttype = BPF_JSGE; - break; - - case 15: /* s>>'=' */ - ttype = BPF_ARSH; - break; - - case 18: /* <'=' */ - ttype = BPF_JLE; - break; - - case 19: /* <<'=' */ - ttype = BPF_LSH; - break; - - case 20: /* &'=' */ - ttype = BPF_AND; - break; - - case 21: /* !'=' */ - ttype = BPF_JNE; - break; - - case 22: /* s<'=' */ - ttype = BPF_JSLE; - break; - } - break; +static void +add_fixed_insn (struct bpf_insn *insn) +{ + char *this_frag = frag_more (insn->size); + char bytes[16]; + int i; - case LEX_IS_SYMBOL_COMPONENT: - return_token = 1; - - switch (state) - { - case 17: /* =='sym' */ - ttype = BPF_JEQ; - break; - - case 12: /* >'sym' */ - ttype = BPF_JGT; - break; - - case 18: /* <'sym' */ - ttype = BPF_JLT; - break; - - case 20: /* &'sym' */ - ttype = BPF_JSET; - break; - - case 14: /*s>'sym' */ - ttype = BPF_JSGT; - break; - - case 22: /* s<'sym' */ - ttype = BPF_JSLT; - break; - - case 16: /* ='sym' */ - ttype = BPF_MOV; - break; - - default: - return_token = 0; - } - - if (return_token) - { - UNGET (); - break; - } - - START_EXPR (); - token[len++] = ch; - - while ((ch2 = GET ()) != EOF) - { - int type; - - type = pseudoc_lex[(unsigned char) ch2]; - if (type != LEX_IS_SYMBOL_COMPONENT) - break; - token[len++] = ch2; - } - - if (ch2 != EOF) - UNGET (); - - if (state == 0) - { - if (len == 1 && ch == 's') - state = 8; /* signed instructions: 's' */ - else - { - ttype = BPF_SYMBOL; - if (is_register (token, len)) - ttype = BPF_REG; - else if (look_for_reserved_word (token, &ttype)) - ; - else if ((pseudoc_lex[(unsigned char) *token] == LEX_IS_ARITHM_OP - || *token == '(' || isdigit(*token)) - && valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - token[len] = '\0'; - ttype = BPF_EXPR; - str = end_expr; - } - - return_token = 1; - } - } - else if (state == 3) /* *('sym' */ - { - if ((ttype = is_cast (&token[2])) != BPF_UNKNOWN) - state = 4; /* *('uXX' */ - else - { - ttype = BPF_EXPR; - return_token = 1; - } - } - else if (state == 6) - { - if (ttype == BPF_SUB) /* neg */ - { - if (is_register (&token[1], len - 1)) - ttype = BPF_NEG; - else if (valid_expr(expr, &end_expr)) - { - len = end_expr - expr; - memcpy(token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - { - len = 0; - while (*invalid_expression) - token[len++] = *invalid_expression++; - token[len] = 0; - ttype = BPF_UNKNOWN; - } - } - else if (valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - memcpy(token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - ttype = BPF_UNKNOWN; - - return_token = 1; - } - break; - } + /* First encode the known parts of the instruction, including + opcodes and constant immediates, and write them to the frag. */ + encode_insn (insn, bytes, 0 /* relax */); + for (i = 0; i < insn->size; ++i) + md_number_to_chars (this_frag + i, (valueT) bytes[i], 1); - if (return_token) - { - *tlen = len; - *insn = str; - break; - } - } + /* Now install the instruction fixups. */ + install_insn_fixups (insn, frag_now, + this_frag - frag_now->fr_literal); +} - return ttype; +/* Add a new relaxable to the list of instructions. */ -#undef GET -#undef UNGET -#undef START_EXPR -#undef SCANNER_SKIP_WHITESPACE -#undef BPF_ARITHM_OP +static void +add_relaxed_insn (struct bpf_insn *insn, expressionS *exp) +{ + char bytes[16]; + int i; + char *this_frag; + unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); + unsigned best_case = insn->size; + + /* We only support relaxing branches, for the moment. */ + relax_substateT subtype + = RELAX_BRANCH_ENCODE (insn->id == BPF_INSN_JAR, + exp->X_op == O_constant, + worst_case); + + frag_grow (worst_case); + this_frag = frag_more (0); + + /* First encode the known parts of the instruction, including + opcodes and constant immediates, and write them to the frag. */ + encode_insn (insn, bytes, 1 /* relax */); + for (i = 0; i < insn->size; ++i) + md_number_to_chars (this_frag + i, (valueT) bytes[i], 1); + + /* Note that instruction fixups will be applied once the frag is + relaxed, in md_convert_frag. */ + frag_var (rs_machine_dependent, + worst_case, best_case, + subtype, exp->X_add_symbol, exp->X_add_number /* offset */, + NULL); } -/* - The parser represent a FSM for the grammar described above. So for example - the following rule: + +/* Parse an operand expression. Returns the first character that is + not part of the expression, or NULL in case of parse error. - ` bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32' + See md_operand below to see how exp_parse_failed is used. */ - Is parser as follows: +static int exp_parse_failed = 0; - 1. It starts in state 0. +static char * +parse_expression (char *s, expressionS *exp) +{ + char *saved_input_line_pointer = input_line_pointer; + char *saved_s = s; - 2. Consumes next token, e.g: `BPF_REG' and set `state' variable to a - particular state to helps to identify, in this case, that a register - token has been read, a comment surrounded by a single quote in the - pseudo-c token is added along with the new `state' value to indicate - what the scanner has read, e.g.: + exp_parse_failed = 0; + input_line_pointer = s; + expression (exp); + s = input_line_pointer; + input_line_pointer = saved_input_line_pointer; - state = 6; // dst_reg = str_cast ( 'src_reg' + switch (exp->X_op == O_absent || exp_parse_failed) + return NULL; - So, in `state 6' the scanner has consumed: a destination register - (BPF_REG), an equal character (BPF_MOV), a cast token (BPF_CAST), an - open parenthesis (BPF_CHR_OPEN_BR) and the source register (BPF_REG). + /* The expression parser may consume trailing whitespaces. We have + to undo that since the instruction templates may be expecting + these whitespaces. */ + { + char *p; + for (p = s - 1; p >= saved_s && *p == ' '; --p) + --s; + } - 3. If the accumulated tokens represent a complete BPF pseudo-c syntax - instruction then, a validation of the terms is made, for example: if - the registers have the same sizes (32/64 bits), if a specific - destination register must be used, etc., after that, a builder: - build_bfp_{non_generic_load,atomic_insn,jmp_insn,arithm_insn,endianness,load_store_insn} - is invoked, internally, it translates the BPF pseudo-c instruction to - a BPF GAS instruction using the previous terms recollected by the - scanner. + return s; +} - 4. If a successful build of BPF GAS instruction was done, a final - state is set to `ST_EOI' (End Of Instruction) meaning that is not - expecting for more tokens in such instruction. Otherwise if the - conditions to calling builder are not satisfied an error is emitted - and `parse_err' is set. -*/ +/* Parse a BPF register name and return the corresponding register + number. Return NULL in case of parse error, or a pointer to the + first character in S that is not part of the register name. */ static char * -bpf_pseudoc_to_normal_syntax (const char *str, char **errmsg) +parse_bpf_register (char *s, char rw, uint8_t *regno) { -#define syntax_err(format, ...) \ - do \ - { \ - if (! parse_err) \ - { \ - parse_err = 1; \ - errbuf = xasprintf (format, ##__VA_ARGS__); \ - } \ - } while (0) - - enum bpf_token_type ttype; - enum bpf_token_type bpf_endianness = BPF_UNKNOWN, - bpf_atomic_insn; - enum bpf_token_type bpf_jmp_op = BPF_JEQ; /* Arbitrary. */ - enum bpf_token_type bpf_cast = BPF_CAST_U8; /* Arbitrary. */ - enum bpf_token_type bpf_arithm_op = BPF_ADD; /* Arbitrary. */ - char *bpf_insn = NULL; - char *errbuf = NULL; - char src_reg[3] = {0}; - char dst_reg[3] = {0}; - char str_imm32[40] = {0}; - char str_offset[40] = {0}; - char str_symbol[MAX_TOKEN_SZ] = {0}; - char token[MAX_TOKEN_SZ] = {0}; - int state = 0; - int parse_err = 0; - size_t tlen; - - while (*str) + if (asm_dialect == DIALECT_NORMAL) { - ttype = get_token (&str, token, &tlen); - if (ttype == BPF_UNKNOWN || state == ST_EOI) - { - syntax_err ("unexpected token: '%s'", token); - break; - } + rw = 'r'; + if (*s != '%') + return NULL; + s += 1; - switch (ttype) + if (*s == 'f' && *(s + 1) == 'p') { - case BPF_UNKNOWN: - case BPF_LL: - break; - - case BPF_REG: - switch (state) - { - case 0: - memcpy (dst_reg, token, tlen); - state = 1; /* 'dst_reg' */ - break; - - case 3: - /* dst_reg bpf_op 'src_reg' */ - memcpy (src_reg, token, tlen); - if (*dst_reg == *src_reg) - bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0, - NULL, bpf_arithm_op); - else - { - syntax_err ("different register sizes: '%s', '%s'", - dst_reg, src_reg); - break; - } - state = ST_EOI; - break; - - case 5: - memcpy (src_reg, token, tlen); - state = 6; /* dst_reg = str_cast ( 'src_reg' */ - break; - - case 9: - memcpy (dst_reg, token, tlen); - state = 10; /* str_cast ( 'dst_reg' */ - break; - - case 11: - /* str_cast ( dst_reg offset ) = 'src_reg' */ - memcpy (src_reg, token, tlen); - bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg, - bpf_cast, str_offset, 0); - state = ST_EOI; - break; - - case 14: - memcpy (dst_reg, token, tlen); - state = 15; /* if 'dst_reg' */ - break; - - case 16: - memcpy (src_reg, token, tlen); - state = 17; /* if dst_reg jmp_op 'src_reg' */ - break; - - case 24: - /* dst_reg = endianness src_reg */ - memcpy (src_reg, token, tlen); - if (*dst_reg == 'r' && !strcmp (dst_reg, src_reg)) - bpf_insn = build_bpf_endianness (dst_reg, bpf_endianness); - else - syntax_err ("invalid operand for instruction: '%s'", token); - - state = ST_EOI; - break; - - case 28: - memcpy (dst_reg, token, tlen); - state = 29; /* lock str_cast ( 'dst_reg' */ - break; - - case 32: - { - /* lock str_cast ( dst_reg offset ) atomic_insn 'src_reg' */ - int with_offset = *str_offset != '\0'; - - memcpy (src_reg, token, tlen); - if ((bpf_cast != BPF_CAST_U32 - && bpf_cast != BPF_CAST_U64) - || *dst_reg != 'r' - || *src_reg != 'r') - syntax_err ("invalid wide atomic instruction"); - else - bpf_insn = build_bpf_atomic_insn (dst_reg, src_reg, bpf_atomic_insn, - bpf_cast, with_offset ? str_offset : str_symbol); - } - - state = ST_EOI; - break; - - case 33: - /* callx 'dst_reg' */ - bpf_insn = xasprintf ("%s %%%s", "call", token); - state = ST_EOI; - break; - - case 35: - memcpy (src_reg, token, tlen); - state = 36; /* dst_reg = str_cast skb [ 'src_reg' */ - break; - } - break; - - case BPF_MOV: - case BPF_ADD: - case BPF_SUB: - case BPF_MUL: - case BPF_DIV: - case BPF_OR: - case BPF_AND: - case BPF_LSH: - case BPF_RSH: - case BPF_MOD: - case BPF_XOR: - case BPF_ARSH: - case BPF_NEG: - switch (state) - { - case 1: - state = 3; /* dst_reg 'arith_op' */ - bpf_arithm_op = ttype; - break; - - case 3: - if (ttype == BPF_NEG) - { - /* reg = -reg */ - bpf_arithm_op = ttype; - memcpy (src_reg, token + 1, tlen - 1); - if (strcmp (dst_reg, src_reg)) - { - syntax_err ("found: '%s', expected: -%s", token, dst_reg); - break; - } - - bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0, - NULL, bpf_arithm_op); - state = ST_EOI; - } - break; - - case 23: - memcpy (src_reg, token, tlen); - state = 11; /* str_cast ( dst_reg offset ) '=' */ - break; - - case 12: - if (ttype == BPF_MOV) - state = 13; /* str_cast ( dst_reg offset ) '=' */ - break; - - case 31: - bpf_atomic_insn = ttype; - state = 32; /* lock str_cast ( dst_reg offset ) 'atomic_insn' */ - break; - - default: - syntax_err ("unexpected '%s'", token); - state = ST_EOI; - } - break; - - case BPF_CAST_U8: - case BPF_CAST_U16: - case BPF_CAST_U32: - case BPF_CAST_U64: - bpf_cast = ttype; - switch (state) - { - case 3: - state = 4; /* dst_reg = 'str_cast' */ - break; - - case 0: - state = 8; /* 'str_cast' */ - break; - - case 26: - state = 27; /* lock 'str_cast' */ - break; - } - break; - - case BPF_CHR_OPEN_BR: - switch (state) - { - case 4: - state = 5; /* dst_reg = str_cast '(' */ - break; - - case 8: - state = 9; /* str_cast '(' */ - break; - - case 27: - state = 28; /* lock str_cast '(' */ - break; - - case 34: - state = 35; /* dst_reg = str_cast skb '[' */ - break; - } - break; - - case BPF_CHR_CLSE_BR: - switch (state) - { - case 7: - /* dst_reg = str_cast ( imm32 ')' */ - bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg, - bpf_cast, str_imm32, 1); - state = ST_EOI; - break; - - case 11: - state = 12; /* str_cast ( dst_reg imm32 ')' */ - break; - - case 21: - /* dst_reg = str_cast ( src_reg offset ')' */ - bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg, - bpf_cast, str_offset, 1); - state = ST_EOI; - break; - - case 22: - state = 23; /* str_cast ( dst_reg offset ')' */ - break; - - case 30: - state = 31; /* lock str_cast ( dst_reg offset ')' */ - break; - - case 37: - /* dst_reg = str_cast skb [ src_reg imm32 ']' */ - if (*dst_reg != 'w' && !strcmp ("r0", dst_reg)) - bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL, - bpf_cast, str_imm32); - else - syntax_err ("invalid register operand: '%s'", dst_reg); - - state = ST_EOI; - break; - } - break; + *regno = 10; + s += 2; + return s; + } + } - case BPF_EXPR: - switch (state) - { - case 3: - { - /* dst_reg bpf_arithm_op 'imm32' */ - int load64 = 0; - - memcpy (str_imm32, token, tlen); - memset (token, 0, tlen); - - if ((ttype = get_token (&str, token, &tlen)) == BPF_LL - && bpf_arithm_op == BPF_MOV) - load64 = 1; - else if (ttype != BPF_UNKNOWN) - syntax_err ("unexpected token: '%s'", token); - - if (load64 && *dst_reg == 'w') - syntax_err ("unexpected register size: '%s'", dst_reg); - - if (! parse_err) - bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64, - str_imm32, bpf_arithm_op); - state = ST_EOI; - } - break; - - case 18: - { - /* if dst_reg jmp_op src_reg goto 'offset' */ - int with_src = *src_reg != '\0'; - - memcpy (str_offset, token, tlen); - if (with_src && *dst_reg != *src_reg) - syntax_err ("different register size: '%s', '%s'", - dst_reg, src_reg); - else - bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL, - with_src ? NULL: str_imm32, - bpf_jmp_op, NULL, str_offset); - state = ST_EOI; - } - break; - - case 19: - /* goto 'offset' */ - memcpy (str_offset, token, tlen); - bpf_insn = xasprintf ("%s %s", "ja", str_offset); - state = ST_EOI; - break; - - case 6: - memcpy (str_offset, token, tlen); - state = 21; /* dst_reg = str_cast ( src_reg 'offset' */ - break; - - case 10: - memcpy (str_offset, token, tlen); - state = 22; /* str_cast ( dst_reg 'offset' */ - break; - - case 16: - memcpy (str_imm32, token, tlen); - state = 25; /* if dst_reg jmp_op 'imm32' */ - break; - - case 29: - memcpy (str_offset, token, tlen); - state = 30; /* lock str_cast ( dst_reg 'offset' */ - break; - - case 34: - /* dst_reg = str_cast skb 'imm32' */ - if (*dst_reg != 'w' && !strcmp ("r0", dst_reg)) - { - memcpy (str_imm32, token, tlen); - bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL, - bpf_cast, str_imm32); - } - else - syntax_err ("invalid register operand: '%s'", dst_reg); - - state = ST_EOI; - break; - - case 36: - memcpy (str_imm32, token, tlen); - state = 37; /* dst_reg = str_cast skb [ src_reg 'imm32' */ - break; - } - break; + if (*s != rw) + return NULL; + s += 1; - case BPF_IF: - if (state == 0) - state = 14; - break; + if (*s == '1') + { + if (*(s + 1) == '0') + { + *regno = 10; + s += 2; + } + else + { + *regno = 1; + s += 1; + } + } + else if (*s >= '0' && *s <= '9') + { + *regno = *s - '0'; + s += 1; + } - case BPF_JSGT: - case BPF_JSLT: - case BPF_JSLE: - case BPF_JSGE: - case BPF_JGT: - case BPF_JGE: - case BPF_JLE: - case BPF_JSET: - case BPF_JNE: - case BPF_JLT: - case BPF_JEQ: - if (state == 15) - { - bpf_jmp_op = ttype; - state = 16; /* if dst_reg 'jmp_op' */ - } - break; + return s; +} - case BPF_GOTO: - switch (state) - { - case 17: - case 25: - state = 18; /* if dst_reg jmp_op src_reg|imm32 'goto' */ - break; - - case 0: - state = 19; - break; - } - break; +/* Collect a parse error message. */ - case BPF_SYMBOL: - switch (state) - { - case 18: - { - /* if dst_reg jmp_op src_reg goto 'sym' */ - int with_src = *src_reg != '\0'; - - memcpy (str_symbol, token, tlen); - if (with_src && *dst_reg != *src_reg) - syntax_err ("different register size: '%s', '%s'", - dst_reg, src_reg); - else - bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL, - with_src ? NULL: str_imm32, - bpf_jmp_op, str_symbol, NULL); - state = ST_EOI; - } - break; - - case 19: - /* goto 'sym' */ - memcpy (str_symbol, token, tlen); - bpf_insn = xasprintf ("%s %s", "ja", str_symbol); - state = ST_EOI; - break; - - case 0: - state = ST_EOI; - break; - - case 3: - { - /* dst_reg arithm_op 'sym' */ - int load64 = 0; - - memcpy (str_symbol, token, tlen); - memset (token, 0, tlen); - - if ((ttype = get_token (&str, token, &tlen)) == BPF_LL - && bpf_arithm_op == BPF_MOV) - load64 = 1; - else if (ttype != BPF_UNKNOWN) - syntax_err ("unexpected token: '%s'", token); - - if (load64 && *dst_reg == 'w') - syntax_err ("unexpected register size: '%s'", dst_reg); - - if (! parse_err) - bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64, - str_symbol, bpf_arithm_op); - state = ST_EOI; - } - break; - } - break; +static int partial_match_length = 0; +static char *errmsg = NULL; - case BPF_LE16: - case BPF_LE32: - case BPF_LE64: - case BPF_BE16: - case BPF_BE32: - case BPF_BE64: - bpf_endianness = ttype; - state = 24; /* dst_reg = 'endianness' */ - break; +static void +parse_error (int length, const char *fmt, ...) +{ + if (length > partial_match_length) + { + va_list args; - case BPF_LOCK: - state = 26; - break; + free (errmsg); + va_start (args, fmt); + errmsg = xvasprintf (fmt, args); + va_end (args); + partial_match_length = length; + } +} - case BPF_IND_CALL: - state = 33; - break; +/* Assemble a machine instruction in STR and emit the frags/bytes it + assembles to. */ - case BPF_LD: - state = 34; /* dst_reg = str_cast 'skb' */ - break; - } +void +md_assemble (char *str ATTRIBUTE_UNUSED) +{ + /* There are two different syntaxes that can be used to write BPF + instructions. One is very conventional and like any other + assembly language where each instruction is conformed by an + instruction mnemonic followed by its operands. This is what we + call the "normal" syntax. The other syntax tries to look like C + statements. We have to support both syntaxes in this assembler. + + One of the many nuisances introduced by this eccentricity is that + in the pseudo-c syntax it is not possible to hash the opcodes + table by instruction mnemonic, because there is none. So we have + no other choice than to try to parse all instruction opcodes + until one matches. This is slow. + + Another problem is that emitting detailed diagnostics becomes + tricky, since the lack of mnemonic means it is not clear what + instruction was intended by the user, and we cannot emit + diagnostics for every attempted template. So if an instruction + is not parsed, we report the diagnostic corresponding to the + partially parsed instruction that was matched further. */ + + unsigned int idx = 0; + struct bpf_insn insn; + const struct bpf_opcode *opcode; + + /* Initialize the global diagnostic variables. See the parse_error + function above. */ + partial_match_length = 0; + errmsg = NULL; + +#define PARSE_ERROR(...) parse_error (s - str, __VA_ARGS__) + + while ((opcode = bpf_get_opcode (idx++)) != NULL) + { + const char *p; + char *s; + const char *template + = (asm_dialect == DIALECT_PSEUDOC ? opcode->pseudoc : opcode->normal); + + /* Do not try to match opcodes with a higher version than the + selected ISA spec. */ + if (opcode->version > isa_spec) + continue; + + memset (&insn, 0, sizeof (struct bpf_insn)); + insn.size = 8; + for (s = str, p = template; *p != '\0';) + { + if (*p == ' ') + { + /* Expect zero or more spaces. */ + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + p += 1; + } + else if (*p == '%') + { + if (*(p + 1) == '%') + { + if (*s != '%') + { + PARSE_ERROR ("expected '%%'"); + break; + } + p += 2; + s += 1; + } + else if (*(p + 1) == 'w') + { + /* Expect zero or more spaces. */ + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + p += 2; + } + else if (*(p + 1) == 'W') + { + /* Expect one or more spaces. */ + if (*s != ' ' && *s != '\t') + { + PARSE_ERROR ("expected white space, got '%s'", + s); + break; + } + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + p += 2; + } + else if (strncmp (p, "%dr", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'r', ®no); + + if (news == NULL || (insn.has_dst && regno != insn.dst)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.dst = regno; + insn.has_dst = 1; + p += 3; + } + else if (strncmp (p, "%sr", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'r', ®no); + + if (news == NULL || (insn.has_src && regno != insn.src)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.src = regno; + insn.has_src = 1; + p += 3; + } + else if (strncmp (p, "%dw", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'w', ®no); + + if (news == NULL || (insn.has_dst && regno != insn.dst)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.dst = regno; + insn.has_dst = 1; + p += 3; + } + else if (strncmp (p, "%sw", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'w', ®no); + + if (news == NULL || (insn.has_src && regno != insn.src)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.src = regno; + insn.has_src = 1; + p += 3; + } + else if (strncmp (p, "%i32", 4) == 0 + || strncmp (p, "%I32", 4) == 0) + { + if (p[1] == 'I') + { + while (*s == ' ' || *s == '\t') + s += 1; + if (*s != '+' && *s != '-') + { + PARSE_ERROR ("expected `+' or `-', got `%c'", *s); + break; + } + } + + s = parse_expression (s, &insn.imm32); + if (s == NULL) + { + PARSE_ERROR ("expected signed 32-bit immediate"); + break; + } + insn.has_imm32 = 1; + p += 4; + } + else if (strncmp (p, "%o16", 4) == 0) + { + while (*s == ' ' || *s == '\t') + s += 1; + if (*s != '+' && *s != '-') + { + PARSE_ERROR ("expected `+' or `-', got `%c'", *s); + break; + } + + s = parse_expression (s, &insn.offset16); + if (s == NULL) + { + PARSE_ERROR ("expected signed 16-bit offset"); + break; + } + insn.has_offset16 = 1; + p += 4; + } + else if (strncmp (p, "%d16", 4) == 0) + { + s = parse_expression (s, &insn.disp16); + if (s == NULL) + { + PARSE_ERROR ("expected signed 16-bit displacement"); + break; + } + insn.has_disp16 = 1; + insn.is_relaxable = 1; + p += 4; + } + else if (strncmp (p, "%d32", 4) == 0) + { + s = parse_expression (s, &insn.disp32); + if (s == NULL) + { + PARSE_ERROR ("expected signed 32-bit displacement"); + break; + } + insn.has_disp32 = 1; + p += 4; + } + else if (strncmp (p, "%i64", 4) == 0) + { + s = parse_expression (s, &insn.imm64); + if (s == NULL) + { + PARSE_ERROR ("expected signed 64-bit immediate"); + break; + } + insn.has_imm64 = 1; + insn.size = 16; + p += 4; + } + else + as_fatal (_("invalid %%-tag in BPF opcode '%s'\n"), template); + } + else + { + /* Match a literal character. */ + if (*s != *p) + { + if (*s == '\0') + PARSE_ERROR ("expected '%c'", *p); + else if (*s == '%') + { + /* This is to workaround a bug in as_bad. */ + char tmp[3]; + + tmp[0] = '%'; + tmp[1] = '%'; + tmp[2] = '\0'; + + PARSE_ERROR ("expected '%c', got '%s'", *p, tmp); + } + else + PARSE_ERROR ("expected '%c', got '%c'", *p, *s); + break; + } + p += 1; + s += 1; + } + } - memset (token, 0, tlen); + if (*p == '\0') + { + /* Allow white spaces at the end of the line. */ + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + if (*s == '\0') + /* We parsed an instruction successfully. */ + break; + PARSE_ERROR ("extra junk at end of line"); + } } - if (state != ST_EOI) - syntax_err ("incomplete instruction"); - - *errmsg = errbuf; - return bpf_insn; + if (opcode == NULL) + { + as_bad (_("unrecognized instruction `%s'"), str); + if (errmsg != NULL) + { + as_bad ("%s", errmsg); + free (errmsg); + } -#undef syntax_err -} + return; + } + insn.id = opcode->id; + insn.opcode = opcode->opcode; -void -md_assemble (char *str) -{ - const CGEN_INSN *insn; - char *errmsg; - char *a_errmsg; - CGEN_FIELDS fields; - char *normal; - -#if CGEN_INT_INSN_P - CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)]; -#else - unsigned char buffer[CGEN_MAX_INSN_SIZE]; -#endif +#undef PARSE_ERROR - gas_cgen_init_parse (); - insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, str, &fields, - buffer, &errmsg); - if (insn == NULL) + /* Generate the frags and fixups for the parsed instruction. */ + if (do_relax && isa_spec >= BPF_V4 && insn.is_relaxable) { - normal = bpf_pseudoc_to_normal_syntax (str, &a_errmsg); - if (normal) - { - insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, normal, &fields, - buffer, &a_errmsg); - xfree (normal); - } + expressionS *relaxable_exp = NULL; - if (insn == NULL) - { - as_bad ("%s", errmsg); - if (a_errmsg) - { - as_bad ("%s", a_errmsg); - xfree (a_errmsg); - } - return; - } + if (insn.has_disp16) + relaxable_exp = &insn.disp16; + else + abort (); + + add_relaxed_insn (&insn, relaxable_exp); } + else + add_fixed_insn (&insn); - gas_cgen_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields), - 0, /* zero to ban relaxable insns. */ - NULL); /* NULL so results not returned here. */ + /* Emit DWARF2 debugging information. */ + dwarf2_emit_insn (insn.size); } +/* Parse an operand that is machine-specific. */ + void md_operand (expressionS *expressionP) { - invalid_expression = input_line_pointer - 1; - gas_cgen_md_operand (expressionP); + /* If this hook is invoked it means GAS failed to parse a generic + expression. We should inhibit the as_bad in expr.c, so we can fail + while parsing instruction alternatives. To do that, we change the + expression to not have an O_absent. But then we also need to set + exp_parse_failed to parse_expression above does the right thing. */ + ++input_line_pointer; + expressionP->X_op = O_constant; + expressionP->X_add_number = 0; + exp_parse_failed = 1; } - symbolS * md_undefined_symbol (char *name ATTRIBUTE_UNUSED) { @@ -1929,3 +1653,38 @@ md_atof (int type, char *litP, int *sizeP) { return ieee_md_atof (type, litP, sizeP, false); } + + +/* Determine whether the equal sign in the given string corresponds to + a BPF instruction, i.e. when it is not to be considered a symbol + assignment. */ + +bool +bpf_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char *str ATTRIBUTE_UNUSED) +{ + uint8_t regno; + + /* Only pseudo-c instructions can have equal signs, and of these, + all that could be confused with a symbol assignment all start + with a register name. */ + if (asm_dialect == DIALECT_PSEUDOC) + { + char *w = parse_bpf_register (str, 'w', ®no); + char *r = parse_bpf_register (str, 'r', ®no); + + if ((w != NULL && *w == '\0') + || (r != NULL && *r == '\0')) + return 1; + } + + return 0; +} + +/* Some special processing for a BPF ELF file. */ + +void +bpf_elf_final_processing (void) +{ + /* Annotate the BPF ISA version in the ELF flag bits. */ + elf_elfheader (stdoutput)->e_flags |= (isa_spec & EF_BPF_CPUVER); +} diff --git a/gas/config/tc-bpf.h b/gas/config/tc-bpf.h index db604db..9fb71ed 100644 --- a/gas/config/tc-bpf.h +++ b/gas/config/tc-bpf.h @@ -37,7 +37,6 @@ /* .-foo gets turned into PC relative relocs. */ #define DIFF_EXPR_OK 1 -#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE) /* Call md_pcrel_from_section(), not md_pcrel_from(). */ #define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) @@ -52,4 +51,8 @@ a jump to offset 0 means jump to the next instruction. */ #define md_single_noop_insn "ja 0" -#define TC_EQUAL_IN_INSN(c, s) 1 +#define TC_EQUAL_IN_INSN(c, s) bpf_tc_equal_in_insn ((c), (s)) +extern bool bpf_tc_equal_in_insn (int, char *); + +#define elf_tc_final_processing bpf_elf_final_processing +extern void bpf_elf_final_processing (void); diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c index b09bbe1..7ca3b2c 100644 --- a/gas/config/tc-d10v.c +++ b/gas/config/tc-d10v.c @@ -1391,8 +1391,8 @@ find_opcode (struct d10v_opcode *opcode, expressionS myops[]) || myops[i].X_add_number == OPERAND_CONTROL + 12 || myops[i].X_add_number == OPERAND_CONTROL + 13 || myops[i].X_add_number == OPERAND_CONTROL + 15)) - as_warn (_("cr%ld is a reserved control register"), - myops[i].X_add_number - OPERAND_CONTROL); + as_warn (_("cr%d is a reserved control register"), + (int) myops[i].X_add_number - OPERAND_CONTROL); } return opcode; } diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index de35ee2..e35e266 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1151,6 +1151,11 @@ static const arch_entry cpu_arch[] = SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), SUBARCH (fred, FRED, ANY_FRED, false), SUBARCH (lkgs, LKGS, ANY_LKGS, false), + SUBARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, false), + SUBARCH (sha512, SHA512, ANY_SHA512, false), + SUBARCH (sm3, SM3, ANY_SM3, false), + SUBARCH (sm4, SM4, ANY_SM4, false), + SUBARCH (pbndkb, PBNDKB, PBNDKB, false), }; #undef SUBARCH @@ -4563,6 +4568,90 @@ optimize_encoding (void) i.types[j].bitfield.disp8 = fits_in_disp8 (i.op[j].disps->X_add_number); } + else if (optimize_for_space + && i.tm.base_opcode == 0x29 + && i.tm.opcode_space == SPACE_0F38 + && i.operands == i.reg_operands + && i.op[0].regs == i.op[1].regs + && (!i.tm.opcode_modifier.vex + || !(i.op[0].regs->reg_flags & RegRex)) + && !is_evex_encoding (&i.tm)) + { + /* Optimize: -Os: + pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN + vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8) + vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8) + */ + i.tm.opcode_space = SPACE_0F; + i.tm.base_opcode = 0x76; + } + else if (((i.tm.base_opcode >= 0x64 + && i.tm.base_opcode <= 0x66 + && i.tm.opcode_space == SPACE_0F) + || (i.tm.base_opcode == 0x37 + && i.tm.opcode_space == SPACE_0F38)) + && i.operands == i.reg_operands + && i.op[0].regs == i.op[1].regs + && !is_evex_encoding (&i.tm)) + { + /* Optimize: -O: + pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN + pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN + vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8) + vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7) + vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8) + vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7) + */ + i.tm.opcode_space = SPACE_0F; + i.tm.base_opcode = 0xef; + if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex)) + { + if (i.operands == 2) + { + gas_assert (i.tm.opcode_modifier.sse2avx); + + i.operands = 3; + i.reg_operands = 3; + i.tm.operands = 3; + + i.op[2].regs = i.op[0].regs; + i.types[2] = i.types[0]; + i.flags[2] = i.flags[0]; + i.tm.operand_types[2] = i.tm.operand_types[0]; + + i.tm.opcode_modifier.sse2avx = 0; + } + i.op[0].regs -= i.op[0].regs->reg_num + 8; + i.op[1].regs = i.op[0].regs; + } + } + else if (optimize_for_space + && i.tm.base_opcode == 0x59 + && i.tm.opcode_space == SPACE_0F38 + && i.operands == i.reg_operands + && i.tm.opcode_modifier.vex + && !(i.op[0].regs->reg_flags & RegRex) + && i.op[0].regs->reg_type.bitfield.xmmword + && i.vec_encoding != vex_encoding_vex3) + { + /* Optimize: -Os: + vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8) + */ + i.tm.opcode_space = SPACE_0F; + i.tm.base_opcode = 0x6c; + i.tm.opcode_modifier.vexvvvv = 1; + + ++i.operands; + ++i.reg_operands; + ++i.tm.operands; + + i.op[2].regs = i.op[0].regs; + i.types[2] = i.types[0]; + i.flags[2] = i.flags[0]; + i.tm.operand_types[2] = i.tm.operand_types[0]; + + swap_2_operands (1, 2); + } } /* Return non-zero for load instruction. */ diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c index 270ddf9..e187231 100644 --- a/gas/config/tc-m68hc11.c +++ b/gas/config/tc-m68hc11.c @@ -1574,7 +1574,8 @@ fixup8 (expressionS *oper, int mode, int opmode) { static char trap_id_warn_once = 0; - as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number); + as_bad (_("Trap id `%" PRId64 "' is out of range."), + (int64_t) oper->X_add_number); if (trap_id_warn_once == 0) { trap_id_warn_once = 1; @@ -1585,7 +1586,8 @@ fixup8 (expressionS *oper, int mode, int opmode) if (!(mode & M6812_OP_TRAP_ID) && !check_range (oper->X_add_number, mode)) { - as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number); + as_bad (_("Operand out of 8-bit range: `%" PRId64 "'."), + (int64_t) oper->X_add_number); } number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); } @@ -1641,8 +1643,8 @@ fixup16 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED) { if (!check_range (oper->X_add_number, mode)) { - as_bad (_("Operand out of 16-bit range: `%ld'."), - oper->X_add_number); + as_bad (_("Operand out of 16-bit range: `%" PRId64 "'."), + (int64_t) oper->X_add_number); } number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2); } @@ -1689,8 +1691,8 @@ fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED) { if (!check_range (oper->X_add_number, mode)) { - as_bad (_("Operand out of 16-bit range: `%ld'."), - oper->X_add_number); + as_bad (_("Operand out of 16-bit range: `%" PRId64 "'."), + (int64_t) oper->X_add_number); } number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFFFF, 3); } @@ -1736,8 +1738,8 @@ fixup8_xg (expressionS *oper, int mode, int opmode) else { if (!(check_range (oper->X_add_number, mode))) - as_bad (_("Operand out of 8-bit range: `%ld'."), - oper->X_add_number); + as_bad (_("Operand out of 8-bit range: `%" PRId64 "'."), + (int64_t) oper->X_add_number); number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); } } diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 297bb9b..aaf8b9b 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -337,7 +337,8 @@ riscv_set_arch (const char *s) riscv_reset_subsets_list_arch_str (); riscv_set_rvc (false); - if (riscv_subset_supports (&riscv_rps_as, "c")) + if (riscv_subset_supports (&riscv_rps_as, "c") + || riscv_subset_supports (&riscv_rps_as, "zca")) riscv_set_rvc (true); if (riscv_subset_supports (&riscv_rps_as, "ztso")) @@ -1425,6 +1426,18 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; + case 'c': + switch (*++oparg) + { + /* byte immediate operators, load/store byte insns. */ + case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; + /* halfword immediate operators, load/store halfword insns. */ + case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break; + case 'f': break; + default: + goto unknown_validate_operand; + } + break; default: goto unknown_validate_operand; } @@ -3558,6 +3571,47 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, goto unknown_riscv_ip_operand; } break; + + case 'c': + switch (*++oparg) + { + case 'h': /* Immediate field for c.lh/c.lhu/c.sh. */ + /* Handle cases, such as c.sh rs2', (rs1'). */ + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) + continue; + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant + || !VALID_ZCB_HALFWORD_UIMM ((valueT) imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_ZCB_HALFWORD_UIMM (imm_expr->X_add_number); + goto rvc_imm_done; + + case 'b': /* Immediate field for c.lbu/c.sb. */ + /* Handle cases, such as c.lbu rd', (rs1'). */ + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) + continue; + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant + || !VALID_ZCB_BYTE_UIMM ((valueT) imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); + goto rvc_imm_done; + + case 'f': /* Operand for matching immediate 255. */ + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant + || imm_expr->X_add_number != 255) + break; + /* This operand is used for matching immediate 255, and + we do not write anything to encoding by this operand. */ + asarg = expr_parse_end; + imm_expr->X_op = O_absent; + continue; + + default: + goto unknown_riscv_ip_operand; + } + break; default: goto unknown_riscv_ip_operand; } @@ -4322,7 +4376,8 @@ s_riscv_option (int x ATTRIBUTE_UNUSED) riscv_reset_subsets_list_arch_str (); riscv_set_rvc (false); - if (riscv_subset_supports (&riscv_rps_as, "c")) + if (riscv_subset_supports (&riscv_rps_as, "c") + || riscv_subset_supports (&riscv_rps_as, "zca")) riscv_set_rvc (true); if (riscv_subset_supports (&riscv_rps_as, "ztso")) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 9558519..765a9a2 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -2291,25 +2291,25 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) We are only prepared to turn a few of the operands into relocs. */ fixP->fx_offset = value; - if (operand->bits == 12 && operand->shift == 20) + if (operand->bits == 12 && operand->shift == 20 && !fixP->fx_pcrel) { fixP->fx_size = 2; fixP->fx_where += 2; fixP->fx_r_type = BFD_RELOC_390_12; } - else if (operand->bits == 12 && operand->shift == 36) + else if (operand->bits == 12 && operand->shift == 36 && !fixP->fx_pcrel) { fixP->fx_size = 2; fixP->fx_where += 4; fixP->fx_r_type = BFD_RELOC_390_12; } - else if (operand->bits == 20 && operand->shift == 20) + else if (operand->bits == 20 && operand->shift == 20 && !fixP->fx_pcrel) { fixP->fx_size = 4; fixP->fx_where += 2; fixP->fx_r_type = BFD_RELOC_390_20; } - else if (operand->bits == 8 && operand->shift == 8) + else if (operand->bits == 8 && operand->shift == 8 && !fixP->fx_pcrel) { fixP->fx_size = 1; fixP->fx_where += 1; @@ -2334,6 +2334,12 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) fixP->fx_offset += 2; fixP->fx_pcrel_adjust = 2; } + else if (fixP->fx_pcrel) + { + fixP->fx_r_type = BFD_RELOC_16_PCREL; + fixP->fx_offset += 2; + fixP->fx_pcrel_adjust = 2; + } else fixP->fx_r_type = BFD_RELOC_16; } diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c index bc0380a..634d5dc 100644 --- a/gas/config/tc-sh.c +++ b/gas/config/tc-sh.c @@ -1222,6 +1222,10 @@ static char * get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand) { char *ptr = args; + + operand[0].type = 0; + operand[1].type = 0; + operand[2].type = 0; if (info->arg[0]) { /* The pre-processor will eliminate whitespace in front of '@' @@ -1234,9 +1238,7 @@ get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand) if (info->arg[1]) { if (*ptr == ',') - { - ptr++; - } + ptr++; get_operand (&ptr, operand + 1); /* ??? Hack: psha/pshl have a varying operand number depending on the type of the first operand. We handle this by having the @@ -1247,28 +1249,11 @@ get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand) if (info->arg[2] && operand[0].type != A_IMM) { if (*ptr == ',') - { - ptr++; - } + ptr++; get_operand (&ptr, operand + 2); } - else - { - operand[2].type = 0; - } - } - else - { - operand[1].type = 0; - operand[2].type = 0; } } - else - { - operand[0].type = 0; - operand[1].type = 0; - operand[2].type = 0; - } return ptr; } diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c index eada5e5..c273bd7 100644 --- a/gas/config/tc-sparc.c +++ b/gas/config/tc-sparc.c @@ -4992,3 +4992,4 @@ sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) emit_expr_with_reloc (exp, nbytes, "disp"); sparc_no_align_cons = 0; } + diff --git a/gas/config/tc-vax.c b/gas/config/tc-vax.c index 36defe4..50adf53 100644 --- a/gas/config/tc-vax.c +++ b/gas/config/tc-vax.c @@ -2683,8 +2683,9 @@ md_assemble (char *instruction_string) } else { - as_warn (_("A bignum/flonum may not be a displacement: 0x%lx used"), - (expP->X_add_number = 0x80000000L)); + as_warn (_("A bignum/flonum may not be a displacement: 0x%" + PRIx64 " used"), + (uint64_t) (expP->X_add_number = 0x80000000L)); /* Chosen so luser gets the most offset bits to patch later. */ } expP->X_add_number = floatP->low[0] diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c index 550c825..fd3ed06 100644 --- a/gas/config/tc-xtensa.c +++ b/gas/config/tc-xtensa.c @@ -7869,8 +7869,9 @@ dump_litpools (void) count++; litfrag = litfrag->fr_next; } - printf(" %ld <%d:%d> (%d) [%d]: ", - lpf->addr, lpf->priority, lpf->original_priority, + printf(" %" PRId64 " <%d:%d> (%d) [%d]: ", + (int64_t) lpf->addr, + lpf->priority, lpf->original_priority, lpf->fragP->fr_line, count); /* dump_frag(lpf->fragP); */ } diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c index 577c584..398c7f3 100644 --- a/gas/config/tc-z80.c +++ b/gas/config/tc-z80.c @@ -1143,10 +1143,11 @@ emit_data_val (expressionS * val, int size) but it does help to maintain compatibility with earlier versions of the assembler. */ if (! val->X_extrabit - && is_overflow (val->X_add_number, size*8)) - as_warn ( _("%d-bit overflow (%+ld)"), size*8, val->X_add_number); + && is_overflow (val->X_add_number, size * 8)) + as_warn ( _("%d-bit overflow (%+" PRId64 ")"), size * 8, + (int64_t) val->X_add_number); for (i = 0; i < size; ++i) - p[i] = (char)(val->X_add_number >> (i*8)); + p[i] = (val->X_add_number >> (i * 8)) & 0xff; return; } @@ -1250,9 +1251,11 @@ emit_byte (expressionS * val, bfd_reloc_code_real_type r_type) if ((val->X_add_number < -128) || (val->X_add_number >= 128)) { if (r_type == BFD_RELOC_Z80_DISP8) - as_bad (_("index overflow (%+ld)"), val->X_add_number); + as_bad (_("index overflow (%+" PRId64 ")"), + (int64_t) val->X_add_number); else - as_bad (_("offset overflow (%+ld)"), val->X_add_number); + as_bad (_("offset overflow (%+" PRId64 ")"), + (int64_t) val->X_add_number); } } else diff --git a/gas/configure b/gas/configure index 1fc3a54..aff5aec 100755 --- a/gas/configure +++ b/gas/configure @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.69 for gas 2.41. +# Generated by GNU Autoconf 2.69 for gas 2.41.50. # # # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc. @@ -587,8 +587,8 @@ MAKEFLAGS= # Identity of this package. PACKAGE_NAME='gas' PACKAGE_TARNAME='gas' -PACKAGE_VERSION='2.41' -PACKAGE_STRING='gas 2.41' +PACKAGE_VERSION='2.41.50' +PACKAGE_STRING='gas 2.41.50' PACKAGE_BUGREPORT='' PACKAGE_URL='' @@ -1381,7 +1381,7 @@ if test "$ac_init_help" = "long"; then # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures gas 2.41 to adapt to many kinds of systems. +\`configure' configures gas 2.41.50 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1452,7 +1452,7 @@ fi if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of gas 2.41:";; + short | recursive ) echo "Configuration of gas 2.41.50:";; esac cat <<\_ACEOF @@ -1600,7 +1600,7 @@ fi test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -gas configure 2.41 +gas configure 2.41.50 generated by GNU Autoconf 2.69 Copyright (C) 2012 Free Software Foundation, Inc. @@ -2011,7 +2011,7 @@ cat >config.log <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by gas $as_me 2.41, which was +It was created by gas $as_me 2.41.50, which was generated by GNU Autoconf 2.69. Invocation command line was $ $0 $@ @@ -2990,7 +2990,7 @@ fi # Define the identity of the package. PACKAGE='gas' - VERSION='2.41' + VERSION='2.41.50' cat >>confdefs.h <<_ACEOF @@ -12107,6 +12107,8 @@ $as_echo "#define STRICTCOFF 1" >>confdefs.h microblaze*) ;; + ppc-*-aix5.[01]*) + ;; ppc-*-aix[5-9].*) $as_echo "#define AIX_WEAK_SUPPORT 1" >>confdefs.h @@ -12296,7 +12298,6 @@ cat >>confdefs.h <<_ACEOF _ACEOF fi - using_cgen=yes ;; epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k) using_cgen=yes @@ -14909,7 +14910,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by gas $as_me 2.41, which was +This file was extended by gas $as_me 2.41.50, which was generated by GNU Autoconf 2.69. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -14975,7 +14976,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" ac_cs_version="\\ -gas config.status 2.41 +gas config.status 2.41.50 configured by $0, generated by GNU Autoconf 2.69, with options \\"\$ac_cs_config\\" diff --git a/gas/configure.ac b/gas/configure.ac index b79586d..c3bd117 100644 --- a/gas/configure.ac +++ b/gas/configure.ac @@ -272,6 +272,8 @@ for this_target in $target $canon_targets ; do ;; changequote(,)dnl + ppc-*-aix5.[01]*) + ;; ppc-*-aix[5-9].*) changequote([,])dnl AC_DEFINE(AIX_WEAK_SUPPORT, 1, @@ -449,7 +451,6 @@ changequote([,])dnl if test $this_target = $target ; then AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.]) fi - using_cgen=yes ;; epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k) using_cgen=yes diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index 0756796..6b43c77 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -15,15 +15,15 @@ @cindex BPF support @menu -* BPF Options:: Options -* BPF Syntax:: Syntax -* BPF Directives:: Machine Directives -* BPF Opcodes:: Opcodes -* BPF Pseudo-C Syntax:: Alternative Pseudo-C Assembly Syntax +* BPF Options:: BPF specific command-line options. +* BPF Special Characters:: Comments and statements. +* BPF Registers:: Register names. +* BPF Directives:: Machine directives. +* BPF Instructions:: Machine instructions. @end menu @node BPF Options -@section Options +@section BPF Options @cindex BPF options (none) @cindex options for BPF (none) @@ -38,76 +38,85 @@ This option specifies that the assembler should emit big-endian eBPF. @item -EL This option specifies that the assembler should emit little-endian eBPF. + +@cindex @option{-mdialect} command-line options, BPF +@item -mdialect=@var{dialect} +This option specifies the assembly language dialect to recognize while +assembling. The assembler supports @option{normal} and +@option{pseudoc}. + +@cindex @option{-misa-spec} command-line options, BPF +@item -misa-spec=@var{spec} +This option specifies the version of the BPF instruction set to use +when assembling. The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}. + +The value @option{xbpf} can be specified to recognize extra +instructions that are used by GCC for testing purposes. But beware +this is not valid BPF. + +@cindex @option{-mno-relax} command-line options, BPF +@item -mno-relax +This option tells the assembler to not relax instructions. @end table Note that if no endianness option is specified in the command line, the host endianness is used. @c man end -@node BPF Syntax -@section Syntax -@menu -* BPF-Chars:: Special Characters -* BPF-Regs:: Register Names -* BPF-Pseudo-Maps:: Pseudo map fds -@end menu - -@node BPF-Chars -@subsection Special Characters +@node BPF Special Characters +@section BPF Special Characters @cindex line comment character, BPF @cindex BPF line comment character -The presence of a @samp{;} on a line indicates the start of a comment -that extends to the end of the current line. If a @samp{#} appears as -the first character of a line, the whole line is treated as a comment. +The presence of a @samp{;} or a @samp{#} on a line indicates the start +of a comment that extends to the end of the current line. @cindex statement separator, BPF Statements and assembly directives are separated by newlines. -@node BPF-Regs -@subsection Register Names +@node BPF Registers +@section BPF Registers @cindex BPF register names @cindex register names, BPF The eBPF processor provides ten general-purpose 64-bit registers, which are read-write, and a read-only frame pointer register: +@noindent +In normal syntax: + @table @samp @item %r0 .. %r9 General-purpose registers. @item %r10 -Frame pointer register. +@itemx %fp +Read-only frame pointer register. @end table -Some registers have additional names, to reflect their role in the -eBPF ABI: +All BPF registers are 64-bit long. However, in the Pseudo-C syntax +registers can be referred using different names, which actually +reflect the kind of instruction they appear on: + +@noindent +In pseudoc syntax: @table @samp -@item %a -This is @samp{%r0}. -@item %ctx -This is @samp{%r6}. -@item %fp -This is @samp{%r10}. +@item r0..r9 +General-purpose register in an instruction that operates on its value +as if it was a 64-bit value. +@item w0..w9 +General-purpose register in an instruction that operates on its value +as if it was a 32-bit value. +@item r10 +Read-only frame pointer register. @end table -@node BPF-Pseudo-Maps -@subsection Pseudo Maps - -@cindex pseudo map fd, BPF -The @samp{LDDW} instruction can take a literal pseudo map file -descriptor as its second argument. This uses the syntax -@samp{%map_fd(N)} where @samp{N} is a signed number. - -For example, to load the address of the pseudo map with file -descriptor @samp{2} in register @samp{r1} we would do: - -@smallexample - lddw %r1, %map_fd(2) -@end smallexample +@noindent +Note that in the Pseudo-C syntax register names are not preceded by +@code{%} characters. @node BPF Directives -@section Machine Directives +@section BPF Directives @cindex machine directives, BPF @@ -128,8 +137,8 @@ The @code{.word} directive produces a 32 bit value. The @code{.dword} directive produces a 64 bit value. @end table -@node BPF Opcodes -@section Opcodes +@node BPF Instructions +@section BPF Instructions @cindex BPF opcodes @cindex opcodes for BPF @@ -137,10 +146,10 @@ In the instruction descriptions below the following field descriptors are used: @table @code -@item %d -Destination general-purpose register whose role is to be destination -of an operation. -@item %s +@item rd +Destination general-purpose register whose role is to be the +destination of an operation. +@item rs Source general-purpose register whose role is to be the source of an operation. @item disp16 @@ -150,104 +159,284 @@ minus one. 32-bit signed PC-relative offset, measured in number of 64-bit words, minus one. @item offset16 -Signed 16-bit immediate. +Signed 16-bit immediate representing an offset in bytes. +@item disp16 +Signed 16-bit immediate representing a displacement to a target, +measured in number of 64-bit words @emph{minus one}. +@item disp32 +Signed 32-bit immediate representing a displacement to a target, +measured in number of 64-bit words @emph{minus one}. @item imm32 Signed 32-bit immediate. @item imm64 Signed 64-bit immediate. @end table -@subsubsection Arithmetic instructions +@subsection Arithmetic instructions The destination register in these instructions act like an accumulator. +Note that in pseudoc syntax these instructions should use @code{r} +registers. + @table @code -@item add %d, (%s|imm32) +@item add rd, rs +@itemx add rd, imm32 +@itemx rd += rs +@itemx rd += imm32 64-bit arithmetic addition. -@item sub %d, (%s|imm32) + +@item sub rd, rs +@itemx sub rd, rs +@itemx rd -= rs +@itemx rd -= imm32 64-bit arithmetic subtraction. -@item mul %d, (%s|imm32) + +@item mul rd, rs +@itemx mul rd, imm32 +@itemx rd *= rs +@itemx rd *= imm32 64-bit arithmetic multiplication. -@item div %d, (%s|imm32) + +@item div rd, rs +@itemx div rd, imm32 +@itemx rd /= rs +@itemx rd /= imm32 64-bit arithmetic integer division. -@item mod %d, (%s|imm32) + +@item mod rd, rs +@itemx mod rd, imm32 +@itemx rd %= rs +@itemx rd %= imm32 64-bit integer remainder. -@item and %d, (%s|imm32) + +@item and rd, rs +@itemx and rd, imm32 +@itemx rd &= rs +@itemx rd &= imm32 64-bit bit-wise ``and'' operation. -@item or %d, (%s|imm32) + +@item or rd, rs +@itemx or rd, imm32 +@itemx rd |= rs +@itemx rd |= imm32 64-bit bit-wise ``or'' operation. -@item xor %d, (%s|imm32) + +@item xor rd, imm32 +@itemx xor rd, rs +@itemx rd ^= rs +@itemx rd ^= imm32 64-bit bit-wise exclusive-or operation. -@item lsh %d, (%s|imm32) -64-bit left shift, by @code{%s} or @code{imm32} bits. -@item rsh %d, (%s|imm32) -64-bit right logical shift, by @code{%s} or @code{imm32} bits. -@item arsh %d, (%s|imm32) -64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits. -@item neg %d + +@item lsh rd, rs +@itemx ldh rd, imm32 +@itemx rd <<= rs +@itemx rd <<= imm32 +64-bit left shift, by @code{rs} or @code{imm32} bits. + +@item rsh %d, %s +@itemx rsh rd, imm32 +@itemx rd >>= rs +@itemx rd >>= imm32 +64-bit right logical shift, by @code{rs} or @code{imm32} bits. + +@item arsh rd, rs +@itemx arsh rd, imm32 +@itemx rd s>>= rs +@itemx rd s>>= imm32 +64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits. + +@item neg rd +@itemx neg rd, imm32 +@itemx rd = - rd +@itemx rd = - imm32 64-bit arithmetic negation. -@item mov %d, (%s|imm32) -Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32} -in @code{%d}. + +Note that in the @code{rd = - imm32} syntax there must be at least +one white space between @code{-} and @code{imm32}. Otherwise the +instruction is parsed as a @code{mov rd, imm32} instruction with a +negative 32-bit immediate. This is a consequence of a syntactic +ambiguity in the pseudoc syntax. + +@item mov rd, rs +@itemx mov rd, imm32 +@itemx rd = rs +@itemx rd = imm32 +Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32} +in @code{rd}. + +@item movs rd, rs, 8 +@itemx rd = (s8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 16 +@itemx rd = (s16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 32 +@itemx rd = (s32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table -@subsubsection 32-bit arithmetic instructions +@subsection 32-bit arithmetic instructions The destination register in these instructions act as an accumulator. +Note that in pseudoc syntax these instructions should use @code{w} +registers. It is not allowed to mix @code{w} and @code{r} registers +in the same instruction. + @table @code -@item add32 %d, (%s|imm32) +@item add32 rd, rs +@itemx add32 rd, imm32 +@itemx rd += rs +@itemx rd += imm32 32-bit arithmetic addition. -@item sub32 %d, (%s|imm32) + +@item sub32 rd, rs +@itemx sub32 rd, imm32 +@itemx rd -= rs +@itemx rd += imm32 32-bit arithmetic subtraction. -@item mul32 %d, (%s|imm32) + +@item mul32 rd, rs +@itemx mul32 rd, imm32 +@itemx rd *= rs +@itemx rd *= imm32 32-bit arithmetic multiplication. -@item div32 %d, (%s|imm32) + +@item div32 rd, rs +@itemx div32 rd, imm32 +@itemx rd /= rs +@itemx rd /= imm32 32-bit arithmetic integer division. -@item mod32 %d, (%s|imm32) + +@item mod32 rd, rs +@itemx mod32 rd, imm32 +@itemx rd %= rs +@itemx rd %= imm32 32-bit integer remainder. -@item and32 %d, (%s|imm32) + +@item and32 rd, rs +@itemx and32 rd, imm32 +@itemx rd &= rs +@itemx rd &= imm32 32-bit bit-wise ``and'' operation. -@item or32 %d, (%s|imm32) + +@item or32 rd, rs +@itemx or32 rd, imm32 +@itemx rd |= rs +@itemx rd |= imm32 32-bit bit-wise ``or'' operation. -@item xor32 %d, (%s|imm32) + +@item xor32 rd, rs +@itemx xor32 rd, imm32 +@itemx rd ^= rs +@itemx rd ^= imm32 32-bit bit-wise exclusive-or operation. -@item lsh32 %d, (%s|imm32) -32-bit left shift, by @code{%s} or @code{imm32} bits. -@item rsh32 %d, (%s|imm32) -32-bit right logical shift, by @code{%s} or @code{imm32} bits. -@item arsh32 %d, (%s|imm32) -32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits. -@item neg32 %d + +@item lsh32 rd, rs +@itemx lsh32 rd, imm32 +@itemx rd <<= rs +@itemx rd <<= imm32 +32-bit left shift, by @code{rs} or @code{imm32} bits. + +@item rsh32 rd, rs +@itemx rsh32 rd, imm32 +@itemx rd >>= rs +@itemx rd >>= imm32 +32-bit right logical shift, by @code{rs} or @code{imm32} bits. + +@item arsh32 rd, rs +@itemx arsh32 rd, imm32 +@itemx rd s>>= rs +@itemx rd s>>= imm32 +32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits. + +@item neg32 rd +@itemx neg32 rd, imm32 +@itemx rd = - rd +@itemx rd = - imm32 32-bit arithmetic negation. -@item mov32 %d, (%s|imm32) -Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32} -in @code{%d}. + +Note that in the @code{rd = - imm32} syntax there must be at least +one white space between @code{-} and @code{imm32}. Otherwise the +instruction is parsed as a @code{mov32 rd, imm32} instruction with a +negative 32-bit immediate. This is a consequence of a syntactic +ambiguity in the pseudoc syntax. + +@item mov32 rd, rs +@itemx mov32 rd, imm32 +@itemx rd = rs +@itemx rd = imm32 +Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32} +in @code{rd}. + +@item mov32s rd, rs, 8 +@itemx rd = (s8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 16 +@itemx rd = (s16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 32 +@itemx rd = (s32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. +@end table + +@subsection Endianness conversion instructions + +@table @code +@item endle rd, 16 +@itemx endle rd, 32 +@itemx endle rd, 64 +@itemx rd = le16 rd +@itemx rd = le32 rd +@itemx rd = le64 rd +Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to +little-endian and store it back in @code{rd}. +@item endbe %d, 16 +@itemx endbe %d, 32 +@itemx endbe %d, 64 +@itemx rd = be16 rd +@itemx rd = be32 rd +@itemx rd = be64 rd +Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian +and store it back in @code{rd}. @end table -@subsubsection Endianness conversion instructions +@subsection Byte swap instructions @table @code -@item endle %d, (16|32|64) -Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to -little-endian. -@item endbe %d, (16|32|64) -Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to big-endian. +@item bswap rd, 16 +@itemx rd = bswap16 rd +Swap the least-significant 16-bit word in @code{rd} with the +most-significant 16-bit word. + +@item bswap rd, 32 +@itemx rd = bswap32 rd +Swap the least-significant 32-bit word in @code{rd} with the +most-significant 32-bit word. + +@item bswap rd, 64 +@itemx rd = bswap64 rd +Swap the least-significant 64-bit word in @code{rd} with the +most-significant 64-bit word. @end table -@subsubsection 64-bit load and pseudo maps + +@subsection 64-bit load and pseudo maps @table @code -@item lddw %d, imm64 -Load the given signed 64-bit immediate, or pseudo map descriptor, to -the destination register @code{%d}. -@item lddw %d, %map_fd(N) -Load the address of the given pseudo map fd @emph{N} to the -destination register @code{%d}. +@item lddw rd, imm64 +@itemx rd = imm64 ll +Load the given signed 64-bit immediate to the destination register +@code{rd}. @end table -@subsubsection Load instructions for socket filters +@subsection Load instructions for socket filters The following instructions are intended to be used in socket filters, and are therefore not general-purpose: they make assumptions on the @@ -259,29 +448,43 @@ Absolute loads: @table @code @item ldabsdw imm32 +@itemx r0 = *(u64 *) skb[imm32] Absolute 64-bit load. + @item ldabsw imm32 +@itemx r0 = *(u32 *) skb[imm32] Absolute 32-bit load. + @item ldabsh imm32 +@itemx r0 = *(u16 *) skb[imm32] Absolute 16-bit load. + @item ldabsb imm32 +@itemx r0 = *(u8 *) skb[imm32] Absolute 8-bit load. @end table Indirect loads: @table @code -@item ldinddw %s, imm32 +@item ldinddw rs, imm32 +@itemx r0 = *(u64 *) skb[rs + imm32] Indirect 64-bit load. -@item ldindw %s, imm32 + +@item ldindw rs, imm32 +@itemx r0 = *(u32 *) skb[rs + imm32] Indirect 32-bit load. -@item ldindh %s, imm32 + +@item ldindh rs, imm32 +@itemx r0 = *(u16 *) skb[rs + imm32] Indirect 16-bit load. + @item ldindb %s, imm32 +@itemx r0 = *(u8 *) skb[rs + imm32] Indirect 8-bit load. @end table -@subsubsection Generic load/store instructions +@subsection Generic load/store instructions General-purpose load and store instructions are provided for several word sizes. @@ -289,43 +492,84 @@ word sizes. Load to register instructions: @table @code -@item ldxdw %d, [%s+offset16] +@item ldxdw rd, [rs + offset16] +@itemx rd = *(u64 *) (rs + offset16) Generic 64-bit load. -@item ldxw %d, [%s+offset16] + +@item ldxw rd, [rs + offset16] +@itemx rd = *(u32 *) (rs + offset16) Generic 32-bit load. -@item ldxh %d, [%s+offset16] + +@item ldxh rd, [rs + offset16] +@itemx rd = *(u16 *) (rs + offset16) Generic 16-bit load. -@item ldxb %d, [%s+offset16] + +@item ldxb rd, [rs + offset16] +@itemx rd = *(u8 *) (rs + offset16) Generic 8-bit load. @end table +Signed load to register instructions: + +@table @code +@item ldxsdw rd, [rs + offset16] +@itemx rd = *(s64 *) (rs + offset16) +Generic 64-bit signed load. + +@item ldxsw rd, [rs + offset16] +@itemx rd = *(s32 *) (rs + offset16) +Generic 32-bit signed load. + +@item ldxsh rd, [rs + offset16] +@itemx rd = *(s16 *) (rs + offset16) +Generic 16-bit signed load. + +@item ldxsb rd, [rs + offset16] +@itemx rd = *(s8 *) (rs + offset16) +Generic 8-bit signed load. +@end table + Store from register instructions: @table @code -@item stxdw [%d+offset16], %s +@item stxdw [rd + offset16], %s +@itemx *(u64 *) (rd + offset16) Generic 64-bit store. -@item stxw [%d+offset16], %s + +@item stxw [rd + offset16], %s +@itemx *(u32 *) (rd + offset16) Generic 32-bit store. -@item stxh [%d+offset16], %s + +@item stxh [rd + offset16], %s +@itemx *(u16 *) (rd + offset16) Generic 16-bit store. -@item stxb [%d+offset16], %s + +@item stxb [rd + offset16], %s +@itemx *(u8 *) (rd + offset16) Generic 8-bit store. @end table Store from immediates instructions: @table @code -@item stddw [%d+offset16], imm32 +@item stdw [rd + offset16], imm32 +@itemx *(u64 *) (rd + offset16) = imm32 Store immediate as 64-bit. -@item stdw [%d+offset16], imm32 + +@item stw [rd + offset16], imm32 +@itemx *(u32 *) (rd + offset16) = imm32 Store immediate as 32-bit. -@item stdh [%d+offset16], imm32 + +@item sth [rd + offset16], imm32 +@itemx *(u16 *) (rd + offset16) = imm32 Store immediate as 16-bit. -@item stdb [%d+offset16], imm32 + +@item stb [rd + offset16], imm32 +@itemx *(u8 *) (rd + offset16) = imm32 Store immediate as 8-bit. @end table -@subsubsection Jump instructions +@subsection Jump instructions eBPF provides the following compare-and-jump instructions, which compare the values of the two given registers, or the values of a @@ -333,29 +577,78 @@ register and an immediate, and perform a branch in case the comparison holds true. @table @code -@item ja %d,(%s|imm32),disp16 +@item ja disp16 +@itemx goto disp16 Jump-always. -@item jeq %d,(%s|imm32),disp16 + +@item jal disp32 +@itemx gotol disp32 +Jump-always, long range. + +@item jeq rd, rs, disp16 +@itemx jeq rd, imm32, disp16 +@itemx if rd == rs goto disp16 +@itemx if rd == imm32 goto disp16 Jump if equal, unsigned. -@item jgt %d,(%s|imm32),disp16 + +@item jgt rd, rs, disp16 +@itemx jgt rd, imm32, disp16 +@itemx if rd > rs goto disp16 +@itemx if rd > imm32 goto disp16 Jump if greater, unsigned. -@item jge %d,(%s|imm32),disp16 + +@item jge rd, rs, disp16 +@itemx jge rd, imm32, disp16 +@itemx if rd >= rs goto disp16 +@itemx if rd >= imm32 goto disp16 Jump if greater or equal. -@item jlt %d,(%s|imm32),disp16 + +@item jlt rd, rs, disp16 +@itemx jlt rd, imm32, disp16 +@itemx if rd < rs goto disp16 +@itemx if rd < imm32 goto disp16 Jump if lesser. -@item jle %d,(%s|imm32),disp16 + +@item jle rd , rs, disp16 +@itemx jle rd, imm32, disp16 +@itemx if rd <= rs goto disp16 +@itemx if rd <= imm32 goto disp16 Jump if lesser or equal. -@item jset %d,(%s|imm32),disp16 + +@item jset rd, rs, disp16 +@itemx jset rd, imm32, disp16 +@itemx if rd & rs goto disp16 +@itemx if rd & imm32 goto disp16 Jump if signed equal. -@item jne %d,(%s|imm32),disp16 + +@item jne rd, rs, disp16 +@itemx jne rd, imm32, disp16 +@itemx if rd != rs goto disp16 +@itemx if rd != imm32 goto disp16 Jump if not equal. -@item jsgt %d,(%s|imm32),disp16 + +@item jsgt rd, rs, disp16 +@itemx jsgt rd, imm32, disp16 +@itemx if rd s> rs goto disp16 +@itemx if rd s> imm32 goto disp16 Jump if signed greater. -@item jsge %d,(%s|imm32),disp16 + +@item jsge rd, rs, disp16 +@itemx jsge rd, imm32, disp16 +@itemx if rd s>= rd goto disp16 +@itemx if rd s>= imm32 goto disp16 Jump if signed greater or equal. -@item jslt %d,(%s|imm32),disp16 + +@item jslt rd, rs, disp16 +@itemx jslt rd, imm32, disp16 +@itemx if rd s< rs goto disp16 +@itemx if rd s< imm32 goto disp16 Jump if signed lesser. -@item jsle %d,(%s|imm32),disp16 + +@item jsle rd, rs, disp16 +@itemx jsle rd, imm32, disp16 +@itemx if rd s<= rs goto disp16 +@itemx if rd s<= imm32 goto disp16 Jump if signed lesser or equal. @end table @@ -363,7 +656,8 @@ A call instruction is provided in order to perform calls to other eBPF functions, or to external kernel helpers: @table @code -@item call (disp32|imm32) +@item call disp32 +@item call imm32 Jump and link to the offset @emph{disp32}, or to the kernel helper function identified by @emph{imm32}. @end table @@ -375,203 +669,221 @@ Finally: Terminate the eBPF program. @end table -@subsubsection Atomic instructions +@subsection 32-bit jump instructions + +eBPF provides the following compare-and-jump instructions, which +compare the 32-bit values of the two given registers, or the values of +a register and an immediate, and perform a branch in case the +comparison holds true. -Atomic exchange-and-add instructions are provided in two flavors: one -for swapping 64-bit quantities and another for 32-bit quantities. +These instructions are only available in BPF v3 or later. @table @code -@item xadddw [%d+offset16],%s -Exchange-and-add a 64-bit value at the specified location. -@item xaddw [%d+offset16],%s -Exchange-and-add a 32-bit value at the specified location. -@end table +@item jeq32 rd, rs, disp16 +@itemx jeq32 rd, imm32, disp16 +@itemx if rd == rs goto disp16 +@itemx if rd == imm32 goto disp16 +Jump if equal, unsigned. -@node BPF Pseudo-C Syntax -@section BPF Pseudo-C Syntax +@item jgt32 rd, rs, disp16 +@itemx jgt32 rd, imm32, disp16 +@itemx if rd > rs goto disp16 +@itemx if rd > imm32 goto disp16 +Jump if greater, unsigned. -This assembler supports another syntax to denote BPF instructions, -which is an alternative to the normal looking syntax documented above. -This alternatative syntax, which we call @dfn{pseudo-C syntax}, is -supported by the LLVM/clang integrated assembler. +@item jge32 rd, rs, disp16 +@itemx jge32 rd, imm32, disp16 +@itemx if rd >= rs goto disp16 +@itemx if rd >= imm32 goto disp16 +Jump if greater or equal. -This syntax is very unconventional, but we need to support it in order -to support inline assembly in existing BPF programs. +@item jlt32 rd, rs, disp16 +@itemx jlt32 rd, imm32, disp16 +@itemx if rd < rs goto disp16 +@itemx if rd < imm32 goto disp16 +Jump if lesser. -Note that the assembler is able to parse sources in which both -syntaxes coexist: some instructions can use the usual assembly like -syntax, whereas some other instructions in the same file can use the -pseudo-C syntax. +@item jle32 rd , rs, disp16 +@itemx jle32 rd, imm32, disp16 +@itemx if rd <= rs goto disp16 +@itemx if rd <= imm32 goto disp16 +Jump if lesser or equal. -@subsubsection Pseudo-C Register Names +@item jset32 rd, rs, disp16 +@itemx jset32 rd, imm32, disp16 +@itemx if rd & rs goto disp16 +@itemx if rd & imm32 goto disp16 +Jump if signed equal. -All BPF registers are 64-bit long. However, in the Pseudo-C syntax -registers can be referred using different names, which actually -reflect the kind of instruction they appear on: +@item jne32 rd, rs, disp16 +@itemx jne32 rd, imm32, disp16 +@itemx if rd != rs goto disp16 +@itemx if rd != imm32 goto disp16 +Jump if not equal. -@table @samp -@item r0..r9 -General-purpose register in an instruction that operates on its value -as if it was a 64-bit value. -@item w0..w9 -General-purpose register in an instruction that operates on its value -as if it was a 32-bit value. +@item jsgt32 rd, rs, disp16 +@itemx jsgt32 rd, imm32, disp16 +@itemx if rd s> rs goto disp16 +@itemx if rd s> imm32 goto disp16 +Jump if signed greater. + +@item jsge32 rd, rs, disp16 +@itemx jsge32 rd, imm32, disp16 +@itemx if rd s>= rd goto disp16 +@itemx if rd s>= imm32 goto disp16 +Jump if signed greater or equal. + +@item jslt32 rd, rs, disp16 +@itemx jslt32 rd, imm32, disp16 +@itemx if rd s< rs goto disp16 +@itemx if rd s< imm32 goto disp16 +Jump if signed lesser. + +@item jsle32 rd, rs, disp16 +@itemx jsle32 rd, imm32, disp16 +@itemx if rd s<= rs goto disp16 +@itemx if rd s<= imm32 goto disp16 +Jump if signed lesser or equal. @end table -@noindent -Note that in the Pseudo-C syntax register names are not preceded by -@code{%} characters. +@subsection Atomic instructions -@subsubsection Arithmetic instructions +Atomic exchange instructions are provided in two flavors: one for +compare-and-swap, one for unconditional exchange. + +@table @code +@item acmp [rd + offset16], rs +@itemx r0 = cmpxchg_64 (rd + offset16, r0, rs) +Atomic compare-and-swap. Compares value in @code{r0} to value +addressed by @code{rd + offset16}. On match, the value addressed by +@code{rd + offset16} is replaced with the value in @code{rs}. +Regardless, the value that was at @code{rd + offset16} is +zero-extended and loaded into @code{r0}. + +@item axchg [rd + offset16], rs +@itemx rs = xchg_64 (rd + offset16, rs) +Atomic exchange. Atomically exchanges the value in @code{rs} with +the value addressed by @code{rd + offset16}. +@end table -In all the instructions below, the operations are 64-bit or 32-bit -depending on the names used to refer to the registers. For example -@code{r3 += r2} will perform 64-bit addition, whereas @code{w3 += w2} -will perform 32-bit addition. Mixing register prefixes is an error, -for example @code{r3 += w2}. +@noindent +The following instructions provide atomic arithmetic operations. @table @code -@item dst_reg += (imm32|src_reg) -Arithmetic addition. -@item dst_reg -= (imm32|src_reg) -Arithmetic subtraction. -@item dst_reg *= (imm32|src_reg) -Arithmetic multiplication. -@item dst_reg /= (imm32|src_reg) -Arithmetic integer unsigned division. -@item dst_reg %= (imm32|src_reg) -Arithmetic integer unsigned remainder. -@item dst_reg &= (imm32|src_reg) -Bit-wise ``and'' operation. -@item dst_reg |= (imm32|src_reg) -Bit-wise ``or'' operation. -@item dst_reg ^= (imm32|src_reg) -Bit-wise exclusive-or operation. -@item dst_reg <<= (imm32|src_reg) -Left shift, by whatever specified number of bits. -@item dst_reg >>= (imm32|src_reg) -Right logical shift, by whatever specified number of bits. -@item dst_reg s>>= (imm32|src_reg) -Right arithmetic shift, by whatever specified number of bits. -@item dst_reg = (imm32|src_reg) -Move the value in @code{imm32} or @code{src_reg} in @code{dst_reg}. -@item dst_reg = -dst_reg -Arithmetic negation. +@item aadd [rd + offset16], rs +@itemx lock *(u64 *)(rd + offset16) = rs +Atomic add instruction. + +@item aor [rd + offset16], rs +@itemx lock *(u64 *) (rd + offset16) |= rs +Atomic or instruction. + +@item aand [rd + offset16], rs +@itemx lock *(u64 *) (rd + offset16) &= rs +Atomic and instruction. + +@item axor [rd + offset16], rs +@itemx lock *(u64 *) (rd + offset16) ^= rs +Atomic xor instruction. @end table -@subsubsection Endianness conversion instructions +@noindent +The following variants perform fetching before the atomic operation. @table @code -@item dst_reg = le16 src_reg -Convert the 16-bit value in @code{src_reg} to little-endian. -@item dst_reg = le32 src_reg -Convert the 32-bit value in @code{src_reg} to little-endian. -@item dst_reg = le64 src_reg -Convert the 64-bit value in @code{src_reg} to little-endian. -@item dst_reg = be16 src_reg -Convert the 16-bit value in @code{src_reg} to big-endian. -@item dst_reg = be32 src_reg -Convert the 32-bit value in @code{src_reg} to big-endian. -@item dst_reg = be64 src_reg -Convert the 64-bit value in @code{src_reg} to big-endian. +@item afadd [rd + offset16], rs +@itemx rs = atomic_fetch_add ((u64 *)(rd + offset16), rs) +Atomic fetch-and-add instruction. + +@item afor [rd + offset16], rs +@itemx rs = atomic_fetch_or ((u64 *)(rd + offset16), rs) +Atomic fetch-and-or instruction. + +@item afand [rd + offset16], rs +@itemx rs = atomic_fetch_and ((u64 *)(rd + offset16), rs) +Atomic fetch-and-and instruction. + +@item afxor [rd + offset16], rs +@itemx rs = atomic_fetch_xor ((u64 *)(rd + offset16), rs) +Atomic fetch-and-or instruction. @end table -@subsubsection 64-bit load and pseudo maps +The above instructions were introduced in the V3 of the BPF +instruction set. The following instruction is supported for backwards +compatibility: @table @code -@item dst_reg = imm64 ll -Load the given signed 64-bit immediate, or pseudo map descriptor, to -the destination register @code{dst_reg}. +@item xadddw [rd + offset16], rs +Alias to @code{aadd}. @end table -@subsubsection Load instructions for socket filters +@subsection 32-bit atomic instructions + +32-bit atomic exchange instructions are provided in two flavors: one +for compare-and-swap, one for unconditional exchange. @table @code -@item r0 = *(u8 *)skb[imm32] -Absolute 8-bit load. -@item r0 = *(u16 *)skb[imm32] -Absolute 16-bit load. -@item r0 = *(u32 *)skb[imm32] -Absolute 32-bit load. -@item r0 = *(u64 *)skb[imm32] -Absolute 64-bit load. -@item r0 = *(u8 *)skb[src_reg + imm32] -Indirect 8-bit load. -@item r0 = *(u16 *)skb[src_reg + imm32] -Indirect 16-bit load. -@item r0 = *(u32 *)skb[src_reg + imm32] -Indirect 32-bit load. -@item r0 = *(u64 *)skb[src_reg + imm32] -Indirect 64-bit load. +@item acmp32 [rd + offset16], rs +@itemx w0 = cmpxchg32_32 (rd + offset16, w0, ws) +Atomic compare-and-swap. Compares value in @code{w0} to value +addressed by @code{rd + offset16}. On match, the value addressed by +@code{rd + offset16} is replaced with the value in @code{ws}. +Regardless, the value that was at @code{rd + offset16} is +zero-extended and loaded into @code{w0}. + +@item axchg [rd + offset16], rs +@itemx ws = xchg32_32 (rd + offset16, ws) +Atomic exchange. Atomically exchanges the value in @code{ws} with +the value addressed by @code{rd + offset16}. @end table -@subsubsection Generic load/store instructions +@noindent +The following instructions provide 32-bit atomic arithmetic operations. @table @code -@item dst_reg = *(u8 *)(src_reg + offset16) -Generic 8-bit load. -@item dst_reg = *(u16 *)(src_reg + offset16) -Generic 16-bit load. -@item dst_reg = *(u32 *)(src_reg + offset16) -Generic 32-bit load. -@item dst_reg = *(u64 *)(src_reg + offset16) -Generic 64-bit load. -@c XXX stb -@c NO PSEUDOC-SYNTAX -@c XXX sth -@c NO PSEUDOC-SYNTAX -@c XXX stw -@c NO PSEUDOC-SYNTAX -@c XXX stdw -@c NO PSEUDOC-SYNTAX -@item *(u8 *)(dst_reg + offset16) = src_reg -Generic 8-bit store. -@item *(u16 *)(dst_reg + offset16) = src_reg -Generic 16-bit store. -@item *(u32 *)(dst_reg + offset16) = src_reg -Generic 32-bit store. -@item *(u64 *)(dst_reg + offset16) = src_reg -Generic 64-bit store. +@item aadd32 [rd + offset16], rs +@itemx lock *(u32 *)(rd + offset16) = rs +Atomic add instruction. + +@item aor32 [rd + offset16], rs +@itemx lock *(u32 *) (rd + offset16) |= rs +Atomic or instruction. + +@item aand32 [rd + offset16], rs +@itemx lock *(u32 *) (rd + offset16) &= rs +Atomic and instruction. + +@item axor32 [rd + offset16], rs +@itemx lock *(u32 *) (rd + offset16) ^= rs +Atomic xor instruction @end table -@subsubsection Jump instructions +@noindent +The following variants perform fetching before the atomic operation. @table @code -@item goto disp16 -Jump-always. -@item if dst_reg == (imm32|src_reg) goto disp16 -Jump if equal. -@item if dst_reg & (imm32|src_reg) goto disp16 -Jump if signed equal. -@item if dst_reg != (imm32|src_reg) goto disp16 -Jump if not equal. -@item if dst_reg > (imm32|src_reg) goto disp16 -Jump if bigger, unsigned. -@item if dst_reg < (imm32|src_reg) goto disp16 -Jump if smaller, unsigned. -@item if dst_reg >= (imm32|src_reg) goto disp16 -Jump if bigger or equal, unsigned. -@item if dst_reg <= (imm32|src_reg) goto disp16 -Jump if smaller or equal, unsigned. -@item if dst_reg s> (imm32|src_reg) goto disp16 -Jump if bigger, signed. -@item if dst_reg s< (imm32|src_reg) goto disp16 -Jump if smaller, signed. -@item if dst_reg s>= (imm32|src_reg) goto disp16 -Jump if bigger or equal, signed. -@item if dst_reg s<= (imm32|src_reg) goto disp16 -Jump if smaller or equal, signed. -@item call imm32 -Jump and link. -@item exit -Terminate the eBPF program. +@item afadd32 [dr + offset16], rs +@itemx ws = atomic_fetch_add ((u32 *)(rd + offset16), ws) +Atomic fetch-and-add instruction. + +@item afor32 [dr + offset16], rs +@itemx ws = atomic_fetch_or ((u32 *)(rd + offset16), ws) +Atomic fetch-and-or instruction. + +@item afand32 [dr + offset16], rs +@itemx ws = atomic_fetch_and ((u32 *)(rd + offset16), ws) +Atomic fetch-and-and instruction. + +@item afxor32 [dr + offset16], rs +@itemx ws = atomic_fetch_xor ((u32 *)(rd + offset16), ws) +Atomic fetch-and-or instruction @end table -@subsubsection Atomic instructions +The above instructions were introduced in the V3 of the BPF +instruction set. The following instruction is supported for backwards +compatibility: @table @code -@item lock *(u64 *)(dst_reg + offset16) += src_reg -Exchange-and-add a 64-bit value at the specified location. -@item lock *(u32 *)(dst_reg + offset16) += src_reg -Exchange-and-add a 32-bit value at the specified location. +@item xaddw [rd + offset16], rs +Alias to @code{aadd32}. @end table diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 49b6e3b..dd06282 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -207,6 +207,11 @@ accept various extension mnemonics. For example, @code{rao_int}, @code{fred}, @code{lkgs}, +@code{avx_vnni_int16}, +@code{sha512}, +@code{sm3}, +@code{sm4}, +@code{pbndkb}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1635,8 +1640,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} -@item @samp{.avx_ne_convert} @tab @samp{.rao_int} -@item @samp{.fred} @tab @samp{.lkgs} +@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} +@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} +@item @samp{.pbndkb} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/doc/local.mk b/gas/doc/local.mk index de13e3c..c48c711 100644 --- a/gas/doc/local.mk +++ b/gas/doc/local.mk @@ -41,7 +41,7 @@ TEXI2DVI = texi2dvi -I "$(srcdir)/%D%" -I %D% -I "$(srcdir)/../libiberty" \ %D%/asconfig.texi: %D%/$(CONFIG).texi %D%/$(am__dirstamp) $(AM_V_at)rm -f %D%/asconfig.texi - $(AM_V_GEN)cp -p $(srcdir)/%D%/$(CONFIG).texi %D%/asconfig.texi + $(AM_V_GEN)cp $(srcdir)/%D%/$(CONFIG).texi %D%/asconfig.texi && touch -m -r $(srcdir)/%D%/$(CONFIG).texi %D%/asconfig.texi $(AM_V_at)chmod u+w %D%/asconfig.texi CPU_DOCS = \ diff --git a/gas/po/gas.pot b/gas/po/gas.pot index bf47483..b10ed52 100644 --- a/gas/po/gas.pot +++ b/gas/po/gas.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: https://sourceware.org/bugzilla/\n" -"POT-Creation-Date: 2023-07-30 14:35+0100\n" +"POT-Creation-Date: 2023-07-03 11:41+0100\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" diff --git a/gas/symbols.c b/gas/symbols.c index a335c31..ea05801 100644 --- a/gas/symbols.c +++ b/gas/symbols.c @@ -3103,7 +3103,7 @@ symbol_begin (void) { symbol_lastP = NULL; symbol_rootP = NULL; /* In case we have 0 symbols (!!) */ - sy_hash = htab_create_alloc (16, hash_symbol_entry, eq_symbol_entry, + sy_hash = htab_create_alloc (1024, hash_symbol_entry, eq_symbol_entry, NULL, xcalloc, free); #if defined (EMIT_SECTION_SYMBOLS) || !defined (RELOC_REQUIRES_SYMBOL) diff --git a/gas/testsuite/gas/all/assign-bad-recursive.d b/gas/testsuite/gas/all/assign-bad-recursive.d index 678be3e..aeec5d5 100644 --- a/gas/testsuite/gas/all/assign-bad-recursive.d +++ b/gas/testsuite/gas/all/assign-bad-recursive.d @@ -1,5 +1,4 @@ #name: bad recursive assignments #source: assign-bad-recursive.s #xfail: bfin-*-* -#notarget: *bpf-*-* #error_output: assign-bad-recursive.l diff --git a/gas/testsuite/gas/all/eqv-dot.d b/gas/testsuite/gas/all/eqv-dot.d index d97db14..fc40b09 100644 --- a/gas/testsuite/gas/all/eqv-dot.d +++ b/gas/testsuite/gas/all/eqv-dot.d @@ -2,7 +2,7 @@ #name: eqv involving dot # bfin doesn't support 'symbol = expression' # tic30 and tic4x have 4 octets per byte, tic54x has 2 octets per byte -#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* *bpf-*-* +#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* # linkrelax targets don't handle equivalence expressions well (nor any # other forward expression). mep uses complex relocs #xfail: am33_2.0-*-* crx-*-* h8300-*-* mn10200-*-* mn10300-*-* mep-*-* diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index bab5a6c..007408f 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -105,7 +105,7 @@ if { [istarget "pdp11-*-*"] } then { run_dump_test eqv-dot } -if { ![istarget "bfin-*-*"] && ![istarget "bpf-*-*"] } then { +if { ![istarget "bfin-*-*"] } then { gas_test "assign-ok.s" "" "" "== assignment support" } gas_test_error "assign-bad.s" "" "== assignment for symbol already set" @@ -403,8 +403,7 @@ if { ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \ gas_test "fastcall.s" "" "" "fastcall labels" } -if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] \ - && ![istarget "bpf-*-*"] } then { +if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] } then { run_dump_test assign } run_dump_test sleb128 diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d index 0355d19..0e9df07 100644 --- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d @@ -1,5 +1,72 @@ -#as: --EB +#as: -EB -mdialect=pseudoc #source: alu-pseudoc.s -#objdump: -dr -#dump: alu-be.dump +#objdump: -dr -M hex,pseudoc #name: eBPF ALU64 instructions, big endian, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 20 00 00 00 00 02 9a r2\+=0x29a + 8: 07 30 00 00 ff ff fd 66 r3\+=0xfffffd66 + 10: 07 40 00 00 7e ad be ef r4\+=0x7eadbeef + 18: 0f 56 00 00 00 00 00 00 r5\+=r6 + 20: 17 20 00 00 00 00 02 9a r2-=0x29a + 28: 17 30 00 00 ff ff fd 66 r3-=0xfffffd66 + 30: 17 40 00 00 7e ad be ef r4-=0x7eadbeef + 38: 1f 56 00 00 00 00 00 00 r5-=r6 + 40: 27 20 00 00 00 00 02 9a r2\*=0x29a + 48: 27 30 00 00 ff ff fd 66 r3\*=0xfffffd66 + 50: 27 40 00 00 7e ad be ef r4\*=0x7eadbeef + 58: 2f 56 00 00 00 00 00 00 r5\*=r6 + 60: 37 20 00 00 00 00 02 9a r2/=0x29a + 68: 37 30 00 00 ff ff fd 66 r3/=0xfffffd66 + 70: 37 40 00 00 7e ad be ef r4/=0x7eadbeef + 78: 3f 56 00 00 00 00 00 00 r5/=r6 + 80: 47 20 00 00 00 00 02 9a r2|=0x29a + 88: 47 30 00 00 ff ff fd 66 r3|=0xfffffd66 + 90: 47 40 00 00 7e ad be ef r4|=0x7eadbeef + 98: 4f 56 00 00 00 00 00 00 r5|=r6 + a0: 57 20 00 00 00 00 02 9a r2&=0x29a + a8: 57 30 00 00 ff ff fd 66 r3&=0xfffffd66 + b0: 57 40 00 00 7e ad be ef r4&=0x7eadbeef + b8: 5f 56 00 00 00 00 00 00 r5&=r6 + c0: 67 20 00 00 00 00 02 9a r2<<=0x29a + c8: 67 30 00 00 ff ff fd 66 r3<<=0xfffffd66 + d0: 67 40 00 00 7e ad be ef r4<<=0x7eadbeef + d8: 6f 56 00 00 00 00 00 00 r5<<=r6 + e0: 77 20 00 00 00 00 02 9a r2>>=0x29a + e8: 77 30 00 00 ff ff fd 66 r3>>=0xfffffd66 + f0: 77 40 00 00 7e ad be ef r4>>=0x7eadbeef + f8: 7f 56 00 00 00 00 00 00 r5>>=r6 + 100: 97 20 00 00 00 00 02 9a r2%=0x29a + 108: 97 30 00 00 ff ff fd 66 r3%=0xfffffd66 + 110: 97 40 00 00 7e ad be ef r4%=0x7eadbeef + 118: 9f 56 00 00 00 00 00 00 r5%=r6 + 120: a7 20 00 00 00 00 02 9a r2\^=0x29a + 128: a7 30 00 00 ff ff fd 66 r3\^=0xfffffd66 + 130: a7 40 00 00 7e ad be ef r4\^=0x7eadbeef + 138: af 56 00 00 00 00 00 00 r5\^=r6 + 140: b7 20 00 00 00 00 02 9a r2=0x29a + 148: b7 30 00 00 ff ff fd 66 r3=0xfffffd66 + 150: b7 40 00 00 7e ad be ef r4=0x7eadbeef + 158: bf 56 00 00 00 00 00 00 r5=r6 + 160: c7 20 00 00 00 00 02 9a r2 s>>=0x29a + 168: c7 30 00 00 ff ff fd 66 r3 s>>=0xfffffd66 + 170: c7 40 00 00 7e ad be ef r4 s>>=0x7eadbeef + 178: cf 56 00 00 00 00 00 00 r5 s>>=r6 + 180: 8f 20 00 00 00 00 00 00 r2=-r2 + 188: d4 90 00 00 00 00 00 10 r9=le16 r9 + 190: d4 80 00 00 00 00 00 20 r8=le32 r8 + 198: d4 70 00 00 00 00 00 40 r7=le64 r7 + 1a0: dc 60 00 00 00 00 00 10 r6=be16 r6 + 1a8: dc 50 00 00 00 00 00 20 r5=be32 r5 + 1b0: dc 40 00 00 00 00 00 40 r4=be64 r4 + 1b8: bf 12 00 08 00 00 00 00 r1 = \(s8\) r2 + 1c0: bf 12 00 10 00 00 00 00 r1 = \(s16\) r2 + 1c8: bf 12 00 20 00 00 00 00 r1 = \(s32\) r2 + 1d0: d7 10 00 00 00 00 00 10 r1 = bswap16 r1 + 1d8: d7 20 00 00 00 00 00 20 r2 = bswap32 r2 + 1e0: d7 30 00 00 00 00 00 40 r3 = bswap64 r3 + 1e8: b7 10 00 00 ff ff f1 00 r1=0xfffff100
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d index afd2a6c..b961f3f 100644 --- a/gas/testsuite/gas/bpf/alu-be.d +++ b/gas/testsuite/gas/bpf/alu-be.d @@ -1,5 +1,72 @@ -#as: --EB +#as: -EB -mdialect=normal #source: alu.s -#objdump: -dr -#dump: alu-be.dump -#name: eBPF ALU64 instructions, big endian, normal syntax +#objdump: -dr -M hex +#name: eBPF ALU instructions, big endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 20 00 00 00 00 02 9a add %r2,0x29a + 8: 07 30 00 00 ff ff fd 66 add %r3,0xfffffd66 + 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef + 18: 0f 56 00 00 00 00 00 00 add %r5,%r6 + 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a + 28: 17 30 00 00 ff ff fd 66 sub %r3,0xfffffd66 + 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef + 38: 1f 56 00 00 00 00 00 00 sub %r5,%r6 + 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a + 48: 27 30 00 00 ff ff fd 66 mul %r3,0xfffffd66 + 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef + 58: 2f 56 00 00 00 00 00 00 mul %r5,%r6 + 60: 37 20 00 00 00 00 02 9a div %r2,0x29a + 68: 37 30 00 00 ff ff fd 66 div %r3,0xfffffd66 + 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef + 78: 3f 56 00 00 00 00 00 00 div %r5,%r6 + 80: 47 20 00 00 00 00 02 9a or %r2,0x29a + 88: 47 30 00 00 ff ff fd 66 or %r3,0xfffffd66 + 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef + 98: 4f 56 00 00 00 00 00 00 or %r5,%r6 + a0: 57 20 00 00 00 00 02 9a and %r2,0x29a + a8: 57 30 00 00 ff ff fd 66 and %r3,0xfffffd66 + b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef + b8: 5f 56 00 00 00 00 00 00 and %r5,%r6 + c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a + c8: 67 30 00 00 ff ff fd 66 lsh %r3,0xfffffd66 + d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef + d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6 + e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a + e8: 77 30 00 00 ff ff fd 66 rsh %r3,0xfffffd66 + f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef + f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6 + 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a + 108: 97 30 00 00 ff ff fd 66 mod %r3,0xfffffd66 + 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef + 118: 9f 56 00 00 00 00 00 00 mod %r5,%r6 + 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a + 128: a7 30 00 00 ff ff fd 66 xor %r3,0xfffffd66 + 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef + 138: af 56 00 00 00 00 00 00 xor %r5,%r6 + 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a + 148: b7 30 00 00 ff ff fd 66 mov %r3,0xfffffd66 + 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef + 158: bf 56 00 00 00 00 00 00 mov %r5,%r6 + 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a + 168: c7 30 00 00 ff ff fd 66 arsh %r3,0xfffffd66 + 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef + 178: cf 56 00 00 00 00 00 00 arsh %r5,%r6 + 180: 8f 20 00 00 00 00 00 00 neg %r2 + 188: d4 90 00 00 00 00 00 10 endle %r9,16 + 190: d4 80 00 00 00 00 00 20 endle %r8,32 + 198: d4 70 00 00 00 00 00 40 endle %r7,64 + 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16 + 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32 + 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64 + 1b8: bf 12 00 08 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 12 00 10 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 12 00 20 00 00 00 00 movs %r1,%r2,32 + 1d0: d7 10 00 00 00 00 00 10 bswap %r1,16 + 1d8: d7 20 00 00 00 00 00 20 bswap %r2,32 + 1e0: d7 30 00 00 00 00 00 40 bswap %r3,64 + 1e8: 87 10 00 00 00 00 0f 00 neg %r1,0xf00
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d index df13069..bbd222c 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-pseudoc.d @@ -1,5 +1,72 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: alu-pseudoc.s -#dump: alu.dump -#name: eBPF ALU64 instructions, pseudo-c syntax +#name: eBPF ALU instructions, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 02 00 00 9a 02 00 00 r2\+=0x29a + 8: 07 03 00 00 66 fd ff ff r3\+=0xfffffd66 + 10: 07 04 00 00 ef be ad 7e r4\+=0x7eadbeef + 18: 0f 65 00 00 00 00 00 00 r5\+=r6 + 20: 17 02 00 00 9a 02 00 00 r2-=0x29a + 28: 17 03 00 00 66 fd ff ff r3-=0xfffffd66 + 30: 17 04 00 00 ef be ad 7e r4-=0x7eadbeef + 38: 1f 65 00 00 00 00 00 00 r5-=r6 + 40: 27 02 00 00 9a 02 00 00 r2\*=0x29a + 48: 27 03 00 00 66 fd ff ff r3\*=0xfffffd66 + 50: 27 04 00 00 ef be ad 7e r4\*=0x7eadbeef + 58: 2f 65 00 00 00 00 00 00 r5\*=r6 + 60: 37 02 00 00 9a 02 00 00 r2/=0x29a + 68: 37 03 00 00 66 fd ff ff r3/=0xfffffd66 + 70: 37 04 00 00 ef be ad 7e r4/=0x7eadbeef + 78: 3f 65 00 00 00 00 00 00 r5/=r6 + 80: 47 02 00 00 9a 02 00 00 r2|=0x29a + 88: 47 03 00 00 66 fd ff ff r3|=0xfffffd66 + 90: 47 04 00 00 ef be ad 7e r4|=0x7eadbeef + 98: 4f 65 00 00 00 00 00 00 r5|=r6 + a0: 57 02 00 00 9a 02 00 00 r2&=0x29a + a8: 57 03 00 00 66 fd ff ff r3&=0xfffffd66 + b0: 57 04 00 00 ef be ad 7e r4&=0x7eadbeef + b8: 5f 65 00 00 00 00 00 00 r5&=r6 + c0: 67 02 00 00 9a 02 00 00 r2<<=0x29a + c8: 67 03 00 00 66 fd ff ff r3<<=0xfffffd66 + d0: 67 04 00 00 ef be ad 7e r4<<=0x7eadbeef + d8: 6f 65 00 00 00 00 00 00 r5<<=r6 + e0: 77 02 00 00 9a 02 00 00 r2>>=0x29a + e8: 77 03 00 00 66 fd ff ff r3>>=0xfffffd66 + f0: 77 04 00 00 ef be ad 7e r4>>=0x7eadbeef + f8: 7f 65 00 00 00 00 00 00 r5>>=r6 + 100: 97 02 00 00 9a 02 00 00 r2%=0x29a + 108: 97 03 00 00 66 fd ff ff r3%=0xfffffd66 + 110: 97 04 00 00 ef be ad 7e r4%=0x7eadbeef + 118: 9f 65 00 00 00 00 00 00 r5%=r6 + 120: a7 02 00 00 9a 02 00 00 r2\^=0x29a + 128: a7 03 00 00 66 fd ff ff r3\^=0xfffffd66 + 130: a7 04 00 00 ef be ad 7e r4\^=0x7eadbeef + 138: af 65 00 00 00 00 00 00 r5\^=r6 + 140: b7 02 00 00 9a 02 00 00 r2=0x29a + 148: b7 03 00 00 66 fd ff ff r3=0xfffffd66 + 150: b7 04 00 00 ef be ad 7e r4=0x7eadbeef + 158: bf 65 00 00 00 00 00 00 r5=r6 + 160: c7 02 00 00 9a 02 00 00 r2 s>>=0x29a + 168: c7 03 00 00 66 fd ff ff r3 s>>=0xfffffd66 + 170: c7 04 00 00 ef be ad 7e r4 s>>=0x7eadbeef + 178: cf 65 00 00 00 00 00 00 r5 s>>=r6 + 180: 8f 02 00 00 00 00 00 00 r2=-r2 + 188: d4 09 00 00 10 00 00 00 r9=le16 r9 + 190: d4 08 00 00 20 00 00 00 r8=le32 r8 + 198: d4 07 00 00 40 00 00 00 r7=le64 r7 + 1a0: dc 06 00 00 10 00 00 00 r6=be16 r6 + 1a8: dc 05 00 00 20 00 00 00 r5=be32 r5 + 1b0: dc 04 00 00 40 00 00 00 r4=be64 r4 + 1b8: bf 21 08 00 00 00 00 00 r1 = \(s8\) r2 + 1c0: bf 21 10 00 00 00 00 00 r1 = \(s16\) r2 + 1c8: bf 21 20 00 00 00 00 00 r1 = \(s32\) r2 + 1d0: d7 01 00 00 10 00 00 00 r1 = bswap16 r1 + 1d8: d7 02 00 00 20 00 00 00 r2 = bswap32 r2 + 1e0: d7 03 00 00 40 00 00 00 r3 = bswap64 r3 + 1e8: b7 01 00 00 00 f1 ff ff r1=0xfffff100 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s index 0f79929..abd8ddc 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu-pseudoc.s @@ -48,4 +48,20 @@ r3 s>>= -666 r4 s>>= 2125315823 r5 s>>= r6 - r2 = -r2 + r2 = - r2 + r9 = le16 r9 + r8 = le32 r8 + r7 = le64 r7 + r6 = be16 r6 + r5 = be32 r5 + r4 = be64 r4 + r1 = (s8) r2 + r1 = (s16) r2 + r1 = (s32) r2 + r1 = bswap16 r1 + r2 = bswap32 r2 + r3 = bswap64 r3 + ;; Note that the next instruction gets processed by the GAS + ;; preprocessor into r1 =-0xf00, which parses into a %dr = %i32 + ;; instruction instead of a neg :/ + r1 = - 0xf00 diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d index 764ae44..e4afdab 100644 --- a/gas/testsuite/gas/bpf/alu.d +++ b/gas/testsuite/gas/bpf/alu.d @@ -1,5 +1,72 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: alu.s -#dump: alu.dump -#name: eBPF ALU64 instructions, normal syntax +#name: eBPF ALU instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a + 8: 07 03 00 00 66 fd ff ff add %r3,0xfffffd66 + 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef + 18: 0f 65 00 00 00 00 00 00 add %r5,%r6 + 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a + 28: 17 03 00 00 66 fd ff ff sub %r3,0xfffffd66 + 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef + 38: 1f 65 00 00 00 00 00 00 sub %r5,%r6 + 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a + 48: 27 03 00 00 66 fd ff ff mul %r3,0xfffffd66 + 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef + 58: 2f 65 00 00 00 00 00 00 mul %r5,%r6 + 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a + 68: 37 03 00 00 66 fd ff ff div %r3,0xfffffd66 + 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef + 78: 3f 65 00 00 00 00 00 00 div %r5,%r6 + 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a + 88: 47 03 00 00 66 fd ff ff or %r3,0xfffffd66 + 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef + 98: 4f 65 00 00 00 00 00 00 or %r5,%r6 + a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a + a8: 57 03 00 00 66 fd ff ff and %r3,0xfffffd66 + b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef + b8: 5f 65 00 00 00 00 00 00 and %r5,%r6 + c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a + c8: 67 03 00 00 66 fd ff ff lsh %r3,0xfffffd66 + d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef + d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6 + e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a + e8: 77 03 00 00 66 fd ff ff rsh %r3,0xfffffd66 + f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef + f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6 + 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a + 108: 97 03 00 00 66 fd ff ff mod %r3,0xfffffd66 + 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef + 118: 9f 65 00 00 00 00 00 00 mod %r5,%r6 + 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a + 128: a7 03 00 00 66 fd ff ff xor %r3,0xfffffd66 + 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef + 138: af 65 00 00 00 00 00 00 xor %r5,%r6 + 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a + 148: b7 03 00 00 66 fd ff ff mov %r3,0xfffffd66 + 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef + 158: bf 65 00 00 00 00 00 00 mov %r5,%r6 + 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a + 168: c7 03 00 00 66 fd ff ff arsh %r3,0xfffffd66 + 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef + 178: cf 65 00 00 00 00 00 00 arsh %r5,%r6 + 180: 8f 02 00 00 00 00 00 00 neg %r2 + 188: d4 09 00 00 10 00 00 00 endle %r9,16 + 190: d4 08 00 00 20 00 00 00 endle %r8,32 + 198: d4 07 00 00 40 00 00 00 endle %r7,64 + 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16 + 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32 + 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64 + 1b8: bf 21 08 00 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 21 10 00 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 21 20 00 00 00 00 00 movs %r1,%r2,32 + 1d0: d7 01 00 00 10 00 00 00 bswap %r1,16 + 1d8: d7 02 00 00 20 00 00 00 bswap %r2,32 + 1e0: d7 03 00 00 40 00 00 00 bswap %r3,64 + 1e8: 87 01 00 00 00 0f 00 00 neg %r1,0xf00
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s index 18e60d5..d0bf560 100644 --- a/gas/testsuite/gas/bpf/alu.s +++ b/gas/testsuite/gas/bpf/alu.s @@ -49,3 +49,16 @@ arsh %r4, 0x7eadbeef arsh %r5, %r6 neg %r2 + endle %r9,16 + endle %r8,32 + endle %r7,64 + endbe %r6,16 + endbe %r5,32 + endbe %r4,64 + movs %r1,%r2,8 + movs %r1,%r2,16 + movs %r1,%r2,32 + bswap %r1, 16 + bswap %r2, 32 + bswap %r3, 64 + neg %r1, 0xf00 diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d index 396d7d4..7f5e700 100644 --- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d @@ -1,5 +1,63 @@ -#as: --EB -#objdump: -dr +#as: -EB -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: alu32-pseudoc.s -#dump: alu32-be.dump -#name: eBPF ALU instructions, big-endian, pseudo-c syntax +#name: eBPF ALU32 instructions, big-endian, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 20 00 00 00 00 02 9a w2\+=0x29a + 8: 04 30 00 00 ff ff fd 66 w3\+=0xfffffd66 + 10: 04 40 00 00 7e ad be ef w4\+=0x7eadbeef + 18: 0c 56 00 00 00 00 00 00 w5\+=w6 + 20: 14 20 00 00 00 00 02 9a w2-=0x29a + 28: 14 30 00 00 ff ff fd 66 w3-=0xfffffd66 + 30: 14 40 00 00 7e ad be ef w4-=0x7eadbeef + 38: 1c 56 00 00 00 00 00 00 w5-=w6 + 40: 24 20 00 00 00 00 02 9a w2\*=0x29a + 48: 24 30 00 00 ff ff fd 66 w3\*=0xfffffd66 + 50: 24 40 00 00 7e ad be ef w4\*=0x7eadbeef + 58: 2c 56 00 00 00 00 00 00 w5\*=w6 + 60: 34 20 00 00 00 00 02 9a w2/=0x29a + 68: 34 30 00 00 ff ff fd 66 w3/=0xfffffd66 + 70: 34 40 00 00 7e ad be ef w4/=0x7eadbeef + 78: 3c 56 00 00 00 00 00 00 w5/=w6 + 80: 44 20 00 00 00 00 02 9a w2|=0x29a + 88: 44 30 00 00 ff ff fd 66 w3|=0xfffffd66 + 90: 44 40 00 00 7e ad be ef w4|=0x7eadbeef + 98: 4c 56 00 00 00 00 00 00 w5|=w6 + a0: 54 20 00 00 00 00 02 9a w2&=0x29a + a8: 54 30 00 00 ff ff fd 66 w3&=0xfffffd66 + b0: 54 40 00 00 7e ad be ef w4&=0x7eadbeef + b8: 5c 56 00 00 00 00 00 00 w5&=w6 + c0: 64 20 00 00 00 00 02 9a w2<<=0x29a + c8: 64 30 00 00 ff ff fd 66 w3<<=0xfffffd66 + d0: 64 40 00 00 7e ad be ef w4<<=0x7eadbeef + d8: 6c 56 00 00 00 00 00 00 w5<<=w6 + e0: 74 20 00 00 00 00 02 9a w2>>=0x29a + e8: 74 30 00 00 ff ff fd 66 w3>>=0xfffffd66 + f0: 74 40 00 00 7e ad be ef w4>>=0x7eadbeef + f8: 7c 56 00 00 00 00 00 00 w5>>=w6 + 100: 94 20 00 00 00 00 02 9a w2%=0x29a + 108: 94 30 00 00 ff ff fd 66 w3%=0xfffffd66 + 110: 94 40 00 00 7e ad be ef w4%=0x7eadbeef + 118: 9c 56 00 00 00 00 00 00 w5%=w6 + 120: a4 20 00 00 00 00 02 9a w2\^=0x29a + 128: a4 30 00 00 ff ff fd 66 w3\^=0xfffffd66 + 130: a4 40 00 00 7e ad be ef w4\^=0x7eadbeef + 138: ac 56 00 00 00 00 00 00 w5\^=w6 + 140: b4 20 00 00 00 00 02 9a w2=0x29a + 148: b4 30 00 00 ff ff fd 66 w3=0xfffffd66 + 150: b4 40 00 00 7e ad be ef w4=0x7eadbeef + 158: bc 56 00 00 00 00 00 00 w5=w6 + 160: c4 20 00 00 00 00 02 9a w2 s>>=0x29a + 168: c4 30 00 00 ff ff fd 66 w3 s>>=0xfffffd66 + 170: c4 40 00 00 7e ad be ef w4 s>>=0x7eadbeef + 178: cc 56 00 00 00 00 00 00 w5 s>>=w6 + 180: 8c 20 00 00 00 00 00 00 w2=-w2 + 188: bc 12 00 08 00 00 00 00 w1 = \(s8\) w2 + 190: bc 12 00 10 00 00 00 00 w1 = \(s16\) w2 + 198: bc 12 00 20 00 00 00 00 w1 = \(s32\) w2 + 1a0: b4 10 00 00 ff ff f1 00 w1=0xfffff100
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d index 6ed9e55..9799664 100644 --- a/gas/testsuite/gas/bpf/alu32-be.d +++ b/gas/testsuite/gas/bpf/alu32-be.d @@ -1,5 +1,63 @@ -#as: --EB -#objdump: -dr -#source: alu32-pseudoc.s -#dump: alu32-be.dump -#name: eBPF ALU instructions, big-endian, normal syntax +#as: -EB -mdialect=normal +#objdump: -dr -M hex +#source: alu32.s +#name: eBPF ALU32 instructions, big-endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a + 8: 04 30 00 00 ff ff fd 66 add32 %r3,0xfffffd66 + 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef + 18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6 + 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a + 28: 14 30 00 00 ff ff fd 66 sub32 %r3,0xfffffd66 + 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef + 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6 + 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a + 48: 24 30 00 00 ff ff fd 66 mul32 %r3,0xfffffd66 + 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef + 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6 + 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a + 68: 34 30 00 00 ff ff fd 66 div32 %r3,0xfffffd66 + 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef + 78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6 + 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a + 88: 44 30 00 00 ff ff fd 66 or32 %r3,0xfffffd66 + 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef + 98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6 + a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a + a8: 54 30 00 00 ff ff fd 66 and32 %r3,0xfffffd66 + b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef + b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6 + c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a + c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,0xfffffd66 + d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef + d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6 + e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a + e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,0xfffffd66 + f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef + f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6 + 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a + 108: 94 30 00 00 ff ff fd 66 mod32 %r3,0xfffffd66 + 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef + 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6 + 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a + 128: a4 30 00 00 ff ff fd 66 xor32 %r3,0xfffffd66 + 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef + 138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6 + 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a + 148: b4 30 00 00 ff ff fd 66 mov32 %r3,0xfffffd66 + 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef + 158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6 + 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a + 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,0xfffffd66 + 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef + 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6 + 180: 8c 20 00 00 00 00 00 00 neg32 %r2 + 188: bc 12 00 08 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 12 00 10 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 12 00 20 00 00 00 00 movs32 %r1,%r2,32 + 1a0: 84 10 00 00 00 00 0f 00 neg32 %r1,0xf00 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d index 98b9921..cc4e010 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d @@ -1,5 +1,63 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: alu32-pseudoc.s -#dump: alu32.dump -#name: eBPF ALU instructions, pseudo-c syntax +#name: eBPF ALU32 instructions, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 02 00 00 9a 02 00 00 w2\+=0x29a + 8: 04 03 00 00 66 fd ff ff w3\+=0xfffffd66 + 10: 04 04 00 00 ef be ad 7e w4\+=0x7eadbeef + 18: 0c 65 00 00 00 00 00 00 w5\+=w6 + 20: 14 02 00 00 9a 02 00 00 w2-=0x29a + 28: 14 03 00 00 66 fd ff ff w3-=0xfffffd66 + 30: 14 04 00 00 ef be ad 7e w4-=0x7eadbeef + 38: 1c 65 00 00 00 00 00 00 w5-=w6 + 40: 24 02 00 00 9a 02 00 00 w2\*=0x29a + 48: 24 03 00 00 66 fd ff ff w3\*=0xfffffd66 + 50: 24 04 00 00 ef be ad 7e w4\*=0x7eadbeef + 58: 2c 65 00 00 00 00 00 00 w5\*=w6 + 60: 34 02 00 00 9a 02 00 00 w2/=0x29a + 68: 34 03 00 00 66 fd ff ff w3/=0xfffffd66 + 70: 34 04 00 00 ef be ad 7e w4/=0x7eadbeef + 78: 3c 65 00 00 00 00 00 00 w5/=w6 + 80: 44 02 00 00 9a 02 00 00 w2|=0x29a + 88: 44 03 00 00 66 fd ff ff w3|=0xfffffd66 + 90: 44 04 00 00 ef be ad 7e w4|=0x7eadbeef + 98: 4c 65 00 00 00 00 00 00 w5|=w6 + a0: 54 02 00 00 9a 02 00 00 w2&=0x29a + a8: 54 03 00 00 66 fd ff ff w3&=0xfffffd66 + b0: 54 04 00 00 ef be ad 7e w4&=0x7eadbeef + b8: 5c 65 00 00 00 00 00 00 w5&=w6 + c0: 64 02 00 00 9a 02 00 00 w2<<=0x29a + c8: 64 03 00 00 66 fd ff ff w3<<=0xfffffd66 + d0: 64 04 00 00 ef be ad 7e w4<<=0x7eadbeef + d8: 6c 65 00 00 00 00 00 00 w5<<=w6 + e0: 74 02 00 00 9a 02 00 00 w2>>=0x29a + e8: 74 03 00 00 66 fd ff ff w3>>=0xfffffd66 + f0: 74 04 00 00 ef be ad 7e w4>>=0x7eadbeef + f8: 7c 65 00 00 00 00 00 00 w5>>=w6 + 100: 94 02 00 00 9a 02 00 00 w2%=0x29a + 108: 94 03 00 00 66 fd ff ff w3%=0xfffffd66 + 110: 94 04 00 00 ef be ad 7e w4%=0x7eadbeef + 118: 9c 65 00 00 00 00 00 00 w5%=w6 + 120: a4 02 00 00 9a 02 00 00 w2\^=0x29a + 128: a4 03 00 00 66 fd ff ff w3\^=0xfffffd66 + 130: a4 04 00 00 ef be ad 7e w4\^=0x7eadbeef + 138: ac 65 00 00 00 00 00 00 w5\^=w6 + 140: b4 02 00 00 9a 02 00 00 w2=0x29a + 148: b4 03 00 00 66 fd ff ff w3=0xfffffd66 + 150: b4 04 00 00 ef be ad 7e w4=0x7eadbeef + 158: bc 65 00 00 00 00 00 00 w5=w6 + 160: c4 02 00 00 9a 02 00 00 w2 s>>=0x29a + 168: c4 03 00 00 66 fd ff ff w3 s>>=0xfffffd66 + 170: c4 04 00 00 ef be ad 7e w4 s>>=0x7eadbeef + 178: cc 65 00 00 00 00 00 00 w5 s>>=w6 + 180: 8c 02 00 00 00 00 00 00 w2=-w2 + 188: bc 21 08 00 00 00 00 00 w1 = \(s8\) w2 + 190: bc 21 10 00 00 00 00 00 w1 = \(s16\) w2 + 198: bc 21 20 00 00 00 00 00 w1 = \(s32\) w2 + 1a0: b4 01 00 00 00 f1 ff ff w1=0xfffff100 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s index a29f6ea..98d586a 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s @@ -1,16 +1,16 @@ # Tests for the ALU eBPF pseudo-C instructions .text - W2 += 666 - W3 += -666 - W4 += 2125315823 - W5 += w6 - W2 -= 666 - W3 -= -666 - W4 -= 2125315823 - W5 -= w6 - W2 *= 666 - W3 *= -666 - W4 *= 2125315823 + w2 += 666 + w3 += -666 + w4 += 2125315823 + w5 += w6 + w2 -= 666 + w3 -= -666 + w4 -= 2125315823 + w5 -= w6 + w2 *= 666 + w3 *= -666 + w4 *= 2125315823 w5 *= w6 w2 /= 666 w3 /= -666 @@ -48,10 +48,11 @@ w3 s>>= -666 w4 s>>= 2125315823 w5 s>>= w6 - w2 = -w2 - r9 = le16 r9 - r8 = le32 r8 - r7 = le64 r7 - r6 = be16 r6 - r5 = be32 r5 - r4 = be64 r4 + w2 = - w2 + w1 = (s8) w2 + w1 = (s16) w2 + w1 = (s32) w2 + ;; Note that the next instruction gets processed by the GAS + ;; preprocessor into w1 =-0xf00, which parses into a %dw = %i32 + ;; instruction instead of a neg :/ + w1 = - 0xf00 diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d index 87efc20..2548438 100644 --- a/gas/testsuite/gas/bpf/alu32.d +++ b/gas/testsuite/gas/bpf/alu32.d @@ -1,5 +1,63 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: alu32.s -#dump: alu32.dump -#name: eBPF ALU instructions, normal syntax +#name: eBPF ALU32 instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a + 8: 04 03 00 00 66 fd ff ff add32 %r3,0xfffffd66 + 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef + 18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6 + 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a + 28: 14 03 00 00 66 fd ff ff sub32 %r3,0xfffffd66 + 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef + 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6 + 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a + 48: 24 03 00 00 66 fd ff ff mul32 %r3,0xfffffd66 + 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef + 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6 + 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a + 68: 34 03 00 00 66 fd ff ff div32 %r3,0xfffffd66 + 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef + 78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6 + 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a + 88: 44 03 00 00 66 fd ff ff or32 %r3,0xfffffd66 + 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef + 98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6 + a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a + a8: 54 03 00 00 66 fd ff ff and32 %r3,0xfffffd66 + b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef + b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6 + c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a + c8: 64 03 00 00 66 fd ff ff lsh32 %r3,0xfffffd66 + d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef + d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6 + e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a + e8: 74 03 00 00 66 fd ff ff rsh32 %r3,0xfffffd66 + f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef + f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6 + 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a + 108: 94 03 00 00 66 fd ff ff mod32 %r3,0xfffffd66 + 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef + 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6 + 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a + 128: a4 03 00 00 66 fd ff ff xor32 %r3,0xfffffd66 + 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef + 138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6 + 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a + 148: b4 03 00 00 66 fd ff ff mov32 %r3,0xfffffd66 + 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef + 158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6 + 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a + 168: c4 03 00 00 66 fd ff ff arsh32 %r3,0xfffffd66 + 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef + 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6 + 180: 8c 02 00 00 00 00 00 00 neg32 %r2 + 188: bc 21 08 00 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 21 10 00 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 21 20 00 00 00 00 00 movs32 %r1,%r2,32 + 1a0: 84 01 00 00 00 0f 00 00 neg32 %r1,0xf00
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s index 7b6f014..fd1d528 100644 --- a/gas/testsuite/gas/bpf/alu32.s +++ b/gas/testsuite/gas/bpf/alu32.s @@ -49,9 +49,7 @@ arsh32 %r4, 0x7eadbeef arsh32 %r5, %r6 neg32 %r2 - endle %r9,16 - endle %r8,32 - endle %r7,64 - endbe %r6,16 - endbe %r5,32 - endbe %r4,64 + movs32 %r1,%r2,8 + movs32 %r1,%r2,16 + movs32 %r1,%r2,32 + neg32 %r1, 0xf00 diff --git a/gas/testsuite/gas/bpf/atomic-be.d b/gas/testsuite/gas/bpf/atomic-be.d index b252571..7a04753 100644 --- a/gas/testsuite/gas/bpf/atomic-be.d +++ b/gas/testsuite/gas/bpf/atomic-be.d @@ -1,7 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: atomic.s -#source: atomic-pseudoc.s -#objdump: -dr +#objdump: -dr -M hex #name: eBPF atomic instructions, big endian .*: +file format .*bpf.* @@ -9,5 +8,23 @@ Disassembly of section .text: 0+ <.text>: - 0: db 12 1e ef 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2 - 8: c3 12 1e ef 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2 + 0: db 12 1e ef 00 00 00 00 aadd \[%r1\+0x1eef\],%r2 + 8: c3 12 1e ef 00 00 00 00 aadd32 \[%r1\+0x1eef\],%r2 + 10: db 12 1e ef 00 00 00 50 aand \[%r1\+0x1eef\],%r2 + 18: c3 12 1e ef 00 00 00 50 aand32 \[%r1\+0x1eef\],%r2 + 20: db 12 1e ef 00 00 00 40 aor \[%r1\+0x1eef\],%r2 + 28: c3 12 1e ef 00 00 00 40 aor32 \[%r1\+0x1eef\],%r2 + 30: db 12 1e ef 00 00 00 a0 axor \[%r1\+0x1eef\],%r2 + 38: c3 12 1e ef 00 00 00 a0 axor32 \[%r1\+0x1eef\],%r2 + 40: db 12 1e ef 00 00 00 01 afadd \[%r1\+0x1eef\],%r2 + 48: c3 12 1e ef 00 00 00 01 afadd32 \[%r1\+0x1eef\],%r2 + 50: db 12 1e ef 00 00 00 51 afand \[%r1\+0x1eef\],%r2 + 58: c3 12 1e ef 00 00 00 51 afand32 \[%r1\+0x1eef\],%r2 + 60: db 12 1e ef 00 00 00 41 afor \[%r1\+0x1eef\],%r2 + 68: c3 12 1e ef 00 00 00 41 afor32 \[%r1\+0x1eef\],%r2 + 70: db 12 1e ef 00 00 00 a1 afxor \[%r1\+0x1eef\],%r2 + 78: c3 12 1e ef 00 00 00 a1 afxor32 \[%r1\+0x1eef\],%r2 + 80: db 12 00 04 00 00 00 f1 acmp \[%r1\+0x4\],%r2 + 88: c3 23 00 04 00 00 00 f1 acmp32 \[%r2\+0x4\],%r3 + 90: db 12 00 08 00 00 00 e1 axchg \[%r1\+0x8\],%r2 + 98: c3 13 00 08 00 00 00 e1 axchg32 \[%r1\+0x8\],%r3 diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.d b/gas/testsuite/gas/bpf/atomic-pseudoc.d index 3b0e5c5..2b3739e 100644 --- a/gas/testsuite/gas/bpf/atomic-pseudoc.d +++ b/gas/testsuite/gas/bpf/atomic-pseudoc.d @@ -1,5 +1,32 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: atomic-pseudoc.s -#dump: atomic.dump -#name: eBPF atomic instructions, normal syntax +#name: eBPF atomic instructions, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: db 21 ef 1e 00 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2 + 8: c3 21 ef 1e 00 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2 + 10: db 21 ef 1e 00 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2 + 18: c3 21 ef 1e 00 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2 + 20: db 21 ef 1e 50 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\&=r2 + 28: c3 21 ef 1e 50 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\&=r2 + 30: db 21 ef 1e 40 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\|=r2 + 38: c3 21 ef 1e 40 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\|=r2 + 40: db 21 ef 1e a0 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\^=r2 + 48: c3 21 ef 1e a0 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\^=r2 + 50: db 21 ef 1e 01 00 00 00 r2=atomic_fetch_add\(\(u64\*\)\(r1\+0x1eef\),r2\) + 58: c3 21 ef 1e 01 00 00 00 w2=atomic_fetch_add\(\(u32\*\)\(r1\+0x1eef\),w2\) + 60: db 21 ef 1e 51 00 00 00 r2=atomic_fetch_and\(\(u64\*\)\(r1\+0x1eef\),r2\) + 68: c3 21 ef 1e 51 00 00 00 w2=atomic_fetch_and\(\(u32\*\)\(r1\+0x1eef\),w2\) + 70: db 21 ef 1e 41 00 00 00 r2=atomic_fetch_or\(\(u64\*\)\(r1\+0x1eef\),r2\) + 78: c3 21 ef 1e 41 00 00 00 w2=atomic_fetch_or\(\(u32\*\)\(r1\+0x1eef\),w2\) + 80: db 21 ef 1e a1 00 00 00 r2=atomic_fetch_xor\(\(u64\*\)\(r1\+0x1eef\),r2\) + 88: c3 21 ef 1e a1 00 00 00 w2=atomic_fetch_xor\(\(u32\*\)\(r1\+0x1eef\),w2\) + 90: db 21 04 00 f1 00 00 00 r0=cmpxchg_64\(r1\+0x4,r0,r2\) + 98: c3 32 04 00 f1 00 00 00 w0=cmpxchg32_32\(r2\+0x4,w0,w3\) + a0: db 21 08 00 e1 00 00 00 r2=xchg_64\(r1\+0x8,r2\) + a8: c3 31 08 00 e1 00 00 00 w3=xchg32_32\(r1\+0x8,w3\) diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.s b/gas/testsuite/gas/bpf/atomic-pseudoc.s index 1a4f218..6994fd1 100644 --- a/gas/testsuite/gas/bpf/atomic-pseudoc.s +++ b/gas/testsuite/gas/bpf/atomic-pseudoc.s @@ -1,4 +1,24 @@ - # Test for eBPF ADDW and ADDDW pseudo-C instructions + # Test for eBPF atomic pseudo-C instructions. .text - lock *(u64 *)(r1 + 7919) += r2 - lock *(u32 *)(r1 + 7919) += r2 + lock *(u64 *)(r1 + 0x1eef) += r2 + lock *(u32 *)(r1 + 0x1eef) += r2 + lock *(u64*)(r1+0x1eef)+=r2 + lock *(u32*)(r1+0x1eef)+=r2 + lock *(u64*)(r1+0x1eef)&=r2 + lock *(u32*)(r1+0x1eef)&=r2 + lock *(u64*)(r1+0x1eef)|=r2 + lock *(u32*)(r1+0x1eef)|=r2 + lock *(u64*)(r1+0x1eef)^=r2 + lock *(u32*)(r1+0x1eef)^=r2 + r2 = atomic_fetch_add((u64*)(r1+0x1eef),r2) + w2 = atomic_fetch_add((u32*)(r1+0x1eef),w2) + r2 = atomic_fetch_and((u64*)(r1+0x1eef),r2) + w2 = atomic_fetch_and((u32*)(r1+0x1eef),w2) + r2 = atomic_fetch_or((u64*)(r1+0x1eef),r2) + w2 = atomic_fetch_or((u32*)(r1+0x1eef),w2) + r2 = atomic_fetch_xor((u64*)(r1+0x1eef),r2) + w2 = atomic_fetch_xor((u32*)(r1+0x1eef),w2) + r0 = cmpxchg_64(r1+0x4,r0,r2) + w0 = cmpxchg32_32(r2+0x4,w0,w3) + r2 = xchg_64(r1+0x8,r2) + w3 = xchg32_32(r1+0x8,w3) diff --git a/gas/testsuite/gas/bpf/atomic.d b/gas/testsuite/gas/bpf/atomic.d index c48ba9a..121ab35 100644 --- a/gas/testsuite/gas/bpf/atomic.d +++ b/gas/testsuite/gas/bpf/atomic.d @@ -1,5 +1,30 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: atomic.s -#dump: atomic.dump #name: eBPF atomic instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: db 21 ef 1e 00 00 00 00 aadd \[%r1\+0x1eef\],%r2 + 8: c3 21 ef 1e 00 00 00 00 aadd32 \[%r1\+0x1eef\],%r2 + 10: db 21 ef 1e 50 00 00 00 aand \[%r1\+0x1eef\],%r2 + 18: c3 21 ef 1e 50 00 00 00 aand32 \[%r1\+0x1eef\],%r2 + 20: db 21 ef 1e 40 00 00 00 aor \[%r1\+0x1eef\],%r2 + 28: c3 21 ef 1e 40 00 00 00 aor32 \[%r1\+0x1eef\],%r2 + 30: db 21 ef 1e a0 00 00 00 axor \[%r1\+0x1eef\],%r2 + 38: c3 21 ef 1e a0 00 00 00 axor32 \[%r1\+0x1eef\],%r2 + 40: db 21 ef 1e 01 00 00 00 afadd \[%r1\+0x1eef\],%r2 + 48: c3 21 ef 1e 01 00 00 00 afadd32 \[%r1\+0x1eef\],%r2 + 50: db 21 ef 1e 51 00 00 00 afand \[%r1\+0x1eef\],%r2 + 58: c3 21 ef 1e 51 00 00 00 afand32 \[%r1\+0x1eef\],%r2 + 60: db 21 ef 1e 41 00 00 00 afor \[%r1\+0x1eef\],%r2 + 68: c3 21 ef 1e 41 00 00 00 afor32 \[%r1\+0x1eef\],%r2 + 70: db 21 ef 1e a1 00 00 00 afxor \[%r1\+0x1eef\],%r2 + 78: c3 21 ef 1e a1 00 00 00 afxor32 \[%r1\+0x1eef\],%r2 + 80: db 21 04 00 f1 00 00 00 acmp \[%r1\+0x4\],%r2 + 88: c3 32 04 00 f1 00 00 00 acmp32 \[%r2\+0x4\],%r3 + 90: db 21 08 00 e1 00 00 00 axchg \[%r1\+0x8\],%r2 + 98: c3 31 08 00 e1 00 00 00 axchg32 \[%r1\+0x8\],%r3 diff --git a/gas/testsuite/gas/bpf/atomic.s b/gas/testsuite/gas/bpf/atomic.s index 0119b24..39ad5ce 100644 --- a/gas/testsuite/gas/bpf/atomic.s +++ b/gas/testsuite/gas/bpf/atomic.s @@ -1,5 +1,24 @@ - # Test for eBPF ADDW and ADDDW instructions + # Test for eBPF atomic instructions .text - xadddw [%r1+0x1eef], %r2 - xaddw [%r1+0x1eef], %r2 - + aadd [%r1+0x1eef], %r2 + aadd32 [%r1+0x1eef], %r2 + aand [%r1+0x1eef], %r2 + aand32 [%r1+0x1eef], %r2 + aor [%r1+0x1eef], %r2 + aor32 [%r1+0x1eef], %r2 + axor [%r1+0x1eef], %r2 + axor32 [%r1+0x1eef], %r2 + + afadd [%r1+0x1eef], %r2 + afadd32 [%r1+0x1eef], %r2 + afand [%r1+0x1eef], %r2 + afand32 [%r1+0x1eef], %r2 + afor [%r1+0x1eef], %r2 + afor32 [%r1+0x1eef], %r2 + afxor [%r1+0x1eef], %r2 + afxor32 [%r1+0x1eef], %r2 + + acmp [%r1+4], %r2 + acmp32 [%r2+4], %r3 + axchg [%r1+8], %r2 + axchg32 [%r1+8], %r3 diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp index 5d91805..80f5a1d 100644 --- a/gas/testsuite/gas/bpf/bpf.exp +++ b/gas/testsuite/gas/bpf/bpf.exp @@ -18,6 +18,10 @@ # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. if {[istarget bpf*-*-*]} { + # Little-endian BPF tests + run_dump_test call + run_dump_test exit + run_dump_test data run_dump_test lddw run_dump_test lddw-pseudoc run_dump_test alu @@ -30,13 +34,19 @@ if {[istarget bpf*-*-*]} { run_dump_test jump-pseudoc run_dump_test jump32 run_dump_test jump32-pseudoc - run_dump_test call - run_dump_test exit + run_dump_test atomic-v1 run_dump_test atomic run_dump_test atomic-pseudoc - run_dump_test data - run_dump_test pseudoc-normal + run_dump_test indcall-1 + run_dump_test indcall-1-pseudoc + + run_dump_test jump-relax-ja + run_dump_test jump-relax-jump + # Big-endian BPF tests + run_dump_test call-be + run_dump_test exit-be + run_dump_test data-be run_dump_test lddw-be run_dump_test lddw-be-pseudoc run_dump_test alu-be @@ -44,17 +54,22 @@ if {[istarget bpf*-*-*]} { run_dump_test alu32-be run_dump_test alu32-be-pseudoc run_dump_test mem-be + run_dump_test mem-be-pseudoc run_dump_test jump-be - run_dump_test call-be - run_dump_test exit-be + run_dump_test jump-be-pseudoc + run_dump_test jump32-be + run_dump_test jump32-be-pseudoc + run_dump_test atomic-v1-be run_dump_test atomic-be - run_dump_test data-be - run_dump_test pseudoc-normal-be + run_dump_test atomic-be-pseudoc - run_dump_test indcall-1 - run_dump_test indcall-1-pseudoc - run_list_test indcall-bad-1 + run_dump_test jump-relax-ja-be + run_dump_test jump-relax-jump-be - run_dump_test alu-xbpf - run_dump_test alu32-xbpf + # Overflow tests + run_dump_test offset16-overflow + run_dump_test disp16-overflow + run_dump_test disp16-overflow-relax + run_dump_test disp32-overflow + run_dump_test imm32-overflow } diff --git a/gas/testsuite/gas/bpf/call-be.d b/gas/testsuite/gas/bpf/call-be.d index bd3b50f..55e4e70 100644 --- a/gas/testsuite/gas/bpf/call-be.d +++ b/gas/testsuite/gas/bpf/call-be.d @@ -1,6 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: call.s -#objdump: -dr +#objdump: -dr -M dec #name: eBPF CALL instruction, big endian .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/call.d b/gas/testsuite/gas/bpf/call.d index daefbd0..a85cb7f 100644 --- a/gas/testsuite/gas/bpf/call.d +++ b/gas/testsuite/gas/bpf/call.d @@ -1,5 +1,5 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M dec #name: eBPF CALL instruction .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/data-be.d b/gas/testsuite/gas/bpf/data-be.d index 010f08f..3a8b68b 100644 --- a/gas/testsuite/gas/bpf/data-be.d +++ b/gas/testsuite/gas/bpf/data-be.d @@ -1,4 +1,4 @@ -#as: --EB +#as: -EB -mdialect=normal #source: data.s #objdump: -s -j .data #name: eBPF data directives, big endian diff --git a/gas/testsuite/gas/bpf/data.d b/gas/testsuite/gas/bpf/data.d index 6824e8b..9fa108b6 100644 --- a/gas/testsuite/gas/bpf/data.d +++ b/gas/testsuite/gas/bpf/data.d @@ -1,4 +1,4 @@ -#as: --EL +#as: -EL -mdialect=normal #objdump: -s -j .data #name: eBPF data directives diff --git a/gas/testsuite/gas/bpf/exit-be.d b/gas/testsuite/gas/bpf/exit-be.d index d3b88c7..b83af3e 100644 --- a/gas/testsuite/gas/bpf/exit-be.d +++ b/gas/testsuite/gas/bpf/exit-be.d @@ -1,6 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: exit.s -#objdump: -dr +#objdump: -dr -M hex #name: eBPF EXIT instruction, big endian .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/exit.d b/gas/testsuite/gas/bpf/exit.d index 87bc91b..68ef902 100644 --- a/gas/testsuite/gas/bpf/exit.d +++ b/gas/testsuite/gas/bpf/exit.d @@ -1,5 +1,5 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #name: eBPF EXIT instruction .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d index b04e656..7a95bad 100644 --- a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d +++ b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d @@ -1,5 +1,23 @@ -#as: -mxbpf --EL -#objdump: -mxbpf -dr +#as: -EL -mdialect=pseudoc -misa-spec=xbpf +#objdump: -M xbpf,pseudoc,dec -dr #source: indcall-1-pseudoc.s -#dump: indcall-1.dump #name: BPF indirect call 1, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section \.text: + +0000000000000000 <main>: + 0: b7 00 00 00 01 00 00 00 r0=1 + 8: b7 01 00 00 01 00 00 00 r1=1 + 10: b7 02 00 00 02 00 00 00 r2=2 + 18: 18 06 00 00 38 00 00 00 r6=56 ll + 20: 00 00 00 00 00 00 00 00[ ]* + 18: R_BPF_64_64 .text + 28: 8d 06 00 00 00 00 00 00 callx r6 + 30: 95 00 00 00 00 00 00 00 exit + +0000000000000038 <bar>: + 38: b7 00 00 00 00 00 00 00 r0=0 + 40: 95 00 00 00 00 00 00 00 exit +#pass diff --git a/gas/testsuite/gas/bpf/indcall-1.d b/gas/testsuite/gas/bpf/indcall-1.d index e04b98b..51103bb 100644 --- a/gas/testsuite/gas/bpf/indcall-1.d +++ b/gas/testsuite/gas/bpf/indcall-1.d @@ -1,5 +1,23 @@ -#as: -mxbpf --EL -#objdump: -mxbpf -dr +#as: -EL -misa-spec=xbpf +#objdump: -dr -M xbpf,dec #source: indcall-1.s -#dump: indcall-1.dump #name: BPF indirect call 1, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section \.text: + +0000000000000000 <main>: + 0: b7 00 00 00 01 00 00 00 mov %r0,1 + 8: b7 01 00 00 01 00 00 00 mov %r1,1 + 10: b7 02 00 00 02 00 00 00 mov %r2,2 + 18: 18 06 00 00 38 00 00 00 lddw %r6,56 + 20: 00 00 00 00 00 00 00 00[ ]* + 18: R_BPF_64_64 .text + 28: 8d 06 00 00 00 00 00 00 call %r6 + 30: 95 00 00 00 00 00 00 00 exit + +0000000000000038 <bar>: + 38: b7 00 00 00 00 00 00 00 mov %r0,0 + 40: 95 00 00 00 00 00 00 00 exit +#pass diff --git a/gas/testsuite/gas/bpf/jump-be.d b/gas/testsuite/gas/bpf/jump-be.d index 7e235e6..fffe1e9 100644 --- a/gas/testsuite/gas/bpf/jump-be.d +++ b/gas/testsuite/gas/bpf/jump-be.d @@ -1,7 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: jump.s -#source: jump-pseudoc.s -#objdump: -dr +#objdump: -dr -M dec #name: eBPF JUMP instructions, big endian .*: +file format .*bpf.* @@ -31,3 +30,5 @@ Disassembly of section .text: 98: cd 34 00 00 00 00 00 00 jslt %r3,%r4,0 a0: d5 30 00 01 00 00 00 03 jsle %r3,3,1 a8: dd 34 00 00 00 00 00 00 jsle %r3,%r4,0 + b0: 06 00 00 00 00 00 00 01 jal 1 + b8: 06 00 00 00 00 00 00 00 jal 0 diff --git a/gas/testsuite/gas/bpf/jump-pseudoc.d b/gas/testsuite/gas/bpf/jump-pseudoc.d index bc17266..9b68108 100644 --- a/gas/testsuite/gas/bpf/jump-pseudoc.d +++ b/gas/testsuite/gas/bpf/jump-pseudoc.d @@ -1,5 +1,34 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M dec,pseudoc #source: jump-pseudoc.s -#dump: jump.dump #name: eBPF JUMP instructions, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 goto 3 + 8: 0f 11 00 00 00 00 00 00 r1\+=r1 + 10: 15 03 01 00 03 00 00 00 if r3==3 goto 1 + 18: 1d 43 00 00 00 00 00 00 if r3==r4 goto 0 + 20: 35 03 fd ff 03 00 00 00 if r3>=3 goto -3 + 28: 3d 43 fc ff 00 00 00 00 if r3>=r4 goto -4 + 30: a5 03 01 00 03 00 00 00 if r3<3 goto 1 + 38: ad 43 00 00 00 00 00 00 if r3<r4 goto 0 + 40: b5 03 01 00 03 00 00 00 if r3<=3 goto 1 + 48: bd 43 00 00 00 00 00 00 if r3<=r4 goto 0 + 50: 45 03 01 00 03 00 00 00 if r3&3 goto 1 + 58: 4d 43 00 00 00 00 00 00 if r3&r4 goto 0 + 60: 55 03 01 00 03 00 00 00 if r3!=3 goto 1 + 68: 5d 43 00 00 00 00 00 00 if r3!=r4 goto 0 + 70: 65 03 01 00 03 00 00 00 if r3s>3 goto 1 + 78: 6d 43 00 00 00 00 00 00 if r3s>r4 goto 0 + 80: 75 03 01 00 03 00 00 00 if r3s>=3 goto 1 + 88: 7d 43 00 00 00 00 00 00 if r3s>=r4 goto 0 + 90: c5 03 01 00 03 00 00 00 if r3s<3 goto 1 + 98: cd 43 00 00 00 00 00 00 if r3s<r4 goto 0 + a0: d5 03 01 00 03 00 00 00 if r3s<=3 goto 1 + a8: dd 43 00 00 00 00 00 00 if r3s<=r4 goto 0 + b0: 06 00 00 00 01 00 00 00 gotol 1 + b8: 06 00 00 00 00 00 00 00 gotol 0
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/jump-pseudoc.s b/gas/testsuite/gas/bpf/jump-pseudoc.s index 1331bda..9f86080 100644 --- a/gas/testsuite/gas/bpf/jump-pseudoc.s +++ b/gas/testsuite/gas/bpf/jump-pseudoc.s @@ -22,4 +22,6 @@ if r3 s< r4 goto 1f 1: if r3 s<= 3 goto 1f if r3 s<= r4 goto 1f +1: gotol 1f + gotol 1f 1: diff --git a/gas/testsuite/gas/bpf/jump.d b/gas/testsuite/gas/bpf/jump.d index 082b3c3..4da3727 100644 --- a/gas/testsuite/gas/bpf/jump.d +++ b/gas/testsuite/gas/bpf/jump.d @@ -1,5 +1,34 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M dec #source: jump.s -#dump: jump.dump #name: eBPF JUMP instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 ja 3 + 8: 0f 11 00 00 00 00 00 00 add %r1,%r1 + 10: 15 03 01 00 03 00 00 00 jeq %r3,3,1 + 18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0 + 20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3 + 28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4 + 30: a5 03 01 00 03 00 00 00 jlt %r3,3,1 + 38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0 + 40: b5 03 01 00 03 00 00 00 jle %r3,3,1 + 48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0 + 50: 45 03 01 00 03 00 00 00 jset %r3,3,1 + 58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0 + 60: 55 03 01 00 03 00 00 00 jne %r3,3,1 + 68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0 + 70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1 + 78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0 + 80: 75 03 01 00 03 00 00 00 jsge %r3,3,1 + 88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0 + 90: c5 03 01 00 03 00 00 00 jslt %r3,3,1 + 98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0 + a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1 + a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0 + b0: 06 00 00 00 01 00 00 00 jal 1 + b8: 06 00 00 00 00 00 00 00 jal 0
\ No newline at end of file diff --git a/gas/testsuite/gas/bpf/jump.s b/gas/testsuite/gas/bpf/jump.s index aae4295..c3d36bd 100644 --- a/gas/testsuite/gas/bpf/jump.s +++ b/gas/testsuite/gas/bpf/jump.s @@ -22,4 +22,6 @@ jslt %r3,%r4,1f 1: jsle %r3,3,1f jsle %r3,%r4,1f -1: +1: jal 1f + jal 1f +1: diff --git a/gas/testsuite/gas/bpf/jump32-pseudoc.d b/gas/testsuite/gas/bpf/jump32-pseudoc.d index 55fb97b..27367d3 100644 --- a/gas/testsuite/gas/bpf/jump32-pseudoc.d +++ b/gas/testsuite/gas/bpf/jump32-pseudoc.d @@ -1,5 +1,32 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M dec,pseudoc #source: jump32-pseudoc.s -#dump: jump32.dump #name: eBPF JUMP32 instructions, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 goto 3 + 8: 0f 11 00 00 00 00 00 00 r1\+=r1 + 10: 16 03 01 00 03 00 00 00 if w3==3 goto 1 + 18: 1e 43 00 00 00 00 00 00 if w3==w4 goto 0 + 20: 36 03 fd ff 03 00 00 00 if w3>=3 goto -3 + 28: 3e 43 fc ff 00 00 00 00 if w3>=w4 goto -4 + 30: a6 03 01 00 03 00 00 00 if w3<3 goto 1 + 38: ae 43 00 00 00 00 00 00 if w3<w4 goto 0 + 40: b6 03 01 00 03 00 00 00 if w3<=3 goto 1 + 48: be 43 00 00 00 00 00 00 if w3<=w4 goto 0 + 50: 46 03 01 00 03 00 00 00 if w3&3 goto 1 + 58: 4e 43 00 00 00 00 00 00 if w3&w4 goto 0 + 60: 56 03 01 00 03 00 00 00 if w3!=3 goto 1 + 68: 5e 43 00 00 00 00 00 00 if w3!=w4 goto 0 + 70: 66 03 01 00 03 00 00 00 if w3s>3 goto 1 + 78: 6e 43 00 00 00 00 00 00 if w3s>w4 goto 0 + 80: 76 03 01 00 03 00 00 00 if w3s>=3 goto 1 + 88: 7e 43 00 00 00 00 00 00 if w3s>=w4 goto 0 + 90: c6 03 01 00 03 00 00 00 if w3s<3 goto 1 + 98: ce 43 00 00 00 00 00 00 if w3s<w4 goto 0 + a0: d6 03 01 00 03 00 00 00 if w3s<=3 goto 1 + a8: de 43 00 00 00 00 00 00 if w3s<=w4 goto 0 diff --git a/gas/testsuite/gas/bpf/jump32.d b/gas/testsuite/gas/bpf/jump32.d index c5efb41..e39dc38 100644 --- a/gas/testsuite/gas/bpf/jump32.d +++ b/gas/testsuite/gas/bpf/jump32.d @@ -1,5 +1,32 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M dec #source: jump32.s -#dump: jump32.dump #name: eBPF JUMP32 instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 ja 3 + 8: 0f 11 00 00 00 00 00 00 add %r1,%r1 + 10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1 + 18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0 + 20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3 + 28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4 + 30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1 + 38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0 + 40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1 + 48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0 + 50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1 + 58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0 + 60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1 + 68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0 + 70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1 + 78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0 + 80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1 + 88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0 + 90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1 + 98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0 + a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1 + a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0 diff --git a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d index e7b477a..940780b 100644 --- a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d @@ -1,5 +1,18 @@ -#as: --EB +#as: -EB -mdialect=pseudoc #source: lddw-pseudoc.s -#objdump: -dr -#dump: lddw-be.dump +#objdump: -dr -M hex,pseudoc #name: eBPF LDDW, big-endian, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 30 00 00 00 00 00 01 r3=0x1 ll + 8: 00 00 00 00 00 00 00 00 + 10: 18 40 00 00 de ad be ef r4=0xdeadbeef ll + 18: 00 00 00 00 00 00 00 00 + 20: 18 50 00 00 55 66 77 88 r5=0x1122334455667788 ll + 28: 00 00 00 00 11 22 33 44 + 30: 18 60 00 00 ff ff ff fe r6=0xfffffffffffffffe ll + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw-be.d b/gas/testsuite/gas/bpf/lddw-be.d index cf1bfba..c104378 100644 --- a/gas/testsuite/gas/bpf/lddw-be.d +++ b/gas/testsuite/gas/bpf/lddw-be.d @@ -1,5 +1,18 @@ -#as: --EB +#as: -EB -mdialect=normal #source: lddw.s -#objdump: -dr -#dump: lddw-be.dump +#objdump: -dr -M hex #name: eBPF LDDW, big-endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 30 00 00 00 00 00 01 lddw %r3,0x1 + 8: 00 00 00 00 00 00 00 00 + 10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef + 18: 00 00 00 00 00 00 00 00 + 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788 + 28: 00 00 00 00 11 22 33 44 + 30: 18 60 00 00 ff ff ff fe lddw %r6,0xfffffffffffffffe + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw-pseudoc.d b/gas/testsuite/gas/bpf/lddw-pseudoc.d index 838e012..3a5ce86 100644 --- a/gas/testsuite/gas/bpf/lddw-pseudoc.d +++ b/gas/testsuite/gas/bpf/lddw-pseudoc.d @@ -1,5 +1,18 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: lddw-pseudoc.s -#dump: lddw.dump #name: eBPF LDDW, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 03 00 00 01 00 00 00 r3=0x1 ll + 8: 00 00 00 00 00 00 00 00 + 10: 18 04 00 00 ef be ad de r4=0xdeadbeef ll + 18: 00 00 00 00 00 00 00 00 + 20: 18 05 00 00 88 77 66 55 r5=0x1122334455667788 ll + 28: 00 00 00 00 44 33 22 11 + 30: 18 06 00 00 fe ff ff ff r6=0xfffffffffffffffe ll + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw.d b/gas/testsuite/gas/bpf/lddw.d index 82ff1b4..c7a0809 100644 --- a/gas/testsuite/gas/bpf/lddw.d +++ b/gas/testsuite/gas/bpf/lddw.d @@ -1,5 +1,18 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: lddw.s -#dump: lddw.dump #name: eBPF LDDW, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 03 00 00 01 00 00 00 lddw %r3,0x1 + 8: 00 00 00 00 00 00 00 00 + 10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef + 18: 00 00 00 00 00 00 00 00 + 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788 + 28: 00 00 00 00 44 33 22 11 + 30: 18 06 00 00 fe ff ff ff lddw %r6,0xfffffffffffffffe + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/mem-be.d b/gas/testsuite/gas/bpf/mem-be.d index 148c55a..cd7b35c 100644 --- a/gas/testsuite/gas/bpf/mem-be.d +++ b/gas/testsuite/gas/bpf/mem-be.d @@ -1,7 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: mem.s -#source: mem-pseudoc.s -#objdump: -dr +#objdump: -dr -M hex #name: eBPF MEM instructions, modulus lddw, big endian .*: +file format .*bpf.* @@ -20,12 +19,18 @@ Disassembly of section .text: 40: 61 21 7e ef 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\] 48: 69 21 7e ef 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\] 50: 71 21 7e ef 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\] - 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+-2\] + 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\] 60: 63 12 7e ef 00 00 00 00 stxw \[%r1\+0x7eef\],%r2 68: 6b 12 7e ef 00 00 00 00 stxh \[%r1\+0x7eef\],%r2 70: 73 12 7e ef 00 00 00 00 stxb \[%r1\+0x7eef\],%r2 - 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+-2\],%r2 + 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2 80: 72 10 7e ef 11 22 33 44 stb \[%r1\+0x7eef\],0x11223344 88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344 90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344 - 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+-2\],0x11223344 + 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+0xfffe\],0x11223344 + a0: 81 21 7e ef 00 00 00 00 ldxsw %r2,\[%r1\+0x7eef\] + a8: 89 21 7e ef 00 00 00 00 ldxsh %r2,\[%r1\+0x7eef\] + b0: 91 21 7e ef 00 00 00 00 ldxsb %r2,\[%r1\+0x7eef\] + b8: 99 21 7e ef 00 00 00 00 ldxsdw %r2,\[%r1\+0x7eef\] + c0: 79 21 00 00 00 00 00 00 ldxdw %r2,\[%r1\+0x0\] + c8: 40 03 00 00 00 00 00 00 ldindw %r3,0x0 diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d index ef5b895..7c37c16 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-pseudoc.d @@ -1,5 +1,36 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: mem-pseudoc.s -#dump: mem.dump #name: eBPF MEM instructions, modulus lddw, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 20 00 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[0xbeef\] + 8: 28 00 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[0xbeef\] + 10: 30 00 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[0xbeef\] + 18: 38 00 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[0xbeef\] + 20: 40 30 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[r3\+0xbeef\] + 28: 48 50 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[r5\+0xbeef\] + 30: 50 70 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[r7\+0xbeef\] + 38: 58 90 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[r9\+0xbeef\] + 40: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\) + 48: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) + 50: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) + 58: 79 12 fe ff 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\) + 60: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + 68: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + 70: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + 78: 7b 21 fe ff 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2 + 80: 72 01 ef 7e 44 33 22 11 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344 + 88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 + 90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 + 98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 + a0: 81 12 ef 7e 00 00 00 00 r2=\*\(s32\*\)\(r1\+0x7eef\) + a8: 89 12 ef 7e 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\) + b0: 91 12 ef 7e 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\) + b8: 99 12 ef 7e 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\) + c0: 58 50 00 00 00 00 00 00 r0=\*\(u64\*\)skb\[r5\+0x0\] + c8: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s index 06c2cfc..823083d 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.s +++ b/gas/testsuite/gas/bpf/mem-pseudoc.s @@ -17,7 +17,13 @@ *(u16 *)(r1 + 32495) = r2 *(u8 *)(r1 + 32495) = r2 *(u64 *)(r1 - 2) = r2 - stb [%r1+0x7eef], 0x11223344 - sth [%r1+0x7eef], 0x11223344 - stw [%r1+0x7eef], 0x11223344 - stdw [%r1+-2], 0x11223344 + *(u8 *)(r1 + 0x7eef) = 0x11223344 + *(u16 *)(r1 + 0x7eef) = 0x11223344 + *(u32 *)(r1 + 0x7eef) = 0x11223344 + *(u64 *)(r1 + -2) = 0x11223344 + r2 = *(s32*)(r1+0x7eef) + r2 = *(s16*)(r1+0x7eef) + r2 = *(s8*)(r1+0x7eef) + r2 = *(s64*)(r1+0x7eef) + r0 = *(u64 *)skb[r5 + 0] + r2 = *(u32 *)(r1 + 0) diff --git a/gas/testsuite/gas/bpf/mem.d b/gas/testsuite/gas/bpf/mem.d index b01bdaa..9a1e709 100644 --- a/gas/testsuite/gas/bpf/mem.d +++ b/gas/testsuite/gas/bpf/mem.d @@ -1,5 +1,36 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: mem.s -#dump: mem.dump #name: eBPF MEM instructions, modulus lddw, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef + 8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef + 10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef + 18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef + 20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef + 28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef + 30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef + 38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef + 40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\] + 48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\] + 50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\] + 58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\] + 60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2 + 68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2 + 70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2 + 78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2 + 80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344 + 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344 + 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344 + 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+0xfffe\],0x11223344 + a0: 81 12 ef 7e 00 00 00 00 ldxsw %r2,\[%r1\+0x7eef\] + a8: 89 12 ef 7e 00 00 00 00 ldxsh %r2,\[%r1\+0x7eef\] + b0: 91 12 ef 7e 00 00 00 00 ldxsb %r2,\[%r1\+0x7eef\] + b8: 99 12 ef 7e 00 00 00 00 ldxsdw %r2,\[%r1\+0x7eef\] + c0: 79 12 00 00 00 00 00 00 ldxdw %r2,\[%r1\+0x0\] + c8: 40 30 00 00 00 00 00 00 ldindw %r3,0x0 diff --git a/gas/testsuite/gas/bpf/mem.s b/gas/testsuite/gas/bpf/mem.s index af6f41b..adeda47 100644 --- a/gas/testsuite/gas/bpf/mem.s +++ b/gas/testsuite/gas/bpf/mem.s @@ -21,4 +21,10 @@ stb [%r1+0x7eef], 0x11223344 sth [%r1+0x7eef], 0x11223344 stw [%r1+0x7eef], 0x11223344 - stdw [%r1+-2], 0x11223344 + stdw [%r1-2], 0x11223344 + ldxsw %r2, [%r1+0x7eef] + ldxsh %r2, [%r1+0x7eef] + ldxsb %r2, [%r1+0x7eef] + ldxsdw %r2, [%r1+0x7eef] + ldxdw %r2, [%r1+0] + ldindw %r3, 0 diff --git a/gas/testsuite/gas/i386/avx512f-nondef.d b/gas/testsuite/gas/i386/avx512f-nondef.d index a062fe3..6aae6a5 100644 --- a/gas/testsuite/gas/i386/avx512f-nondef.d +++ b/gas/testsuite/gas/i386/avx512f-nondef.d @@ -15,10 +15,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f2 55 1f 3b f4 vpminud \{rn-bad\},%zmm4,%zmm5,%zmm6\{%k7\} [ ]*[a-f0-9]+: 62 f2 7e 48 31 72 7f vpmovdb %zmm6,0x7f0\(%edx\) [ ]*[a-f0-9]+: 62 f2 7e 58 31 72 7f vpmovdb %zmm6,0x7f0\(%edx\)\{bad\} -[ ]*[a-f0-9]+: 62 f1 7c 88 58 \(bad\) -[ ]*[a-f0-9]+: c3 ret +[ ]*[a-f0-9]+: 62 f1 7c 88 58 c3 (\{evex\} )?vaddps %xmm3,%xmm0,%xmm0\{bad\} [ ]*[a-f0-9]+: 62 f2 7d 4f 92 01 vgatherdps \(bad\),%zmm0\{%k7\} [ ]*[a-f0-9]+: 67 62 f2 7d 4f 92 01 addr16 vgatherdps \(bad\),%zmm0\{%k7\} [ ]*[a-f0-9]+: 62 f2 7d cf 92 04 08 vgatherdps \(%eax,%zmm1(,1)?\),%zmm0\{%k7\}\{z\}/\(bad\) [ ]*[a-f0-9]+: 62 f2 7d 48 92 04 08 vgatherdps \(%eax,%zmm1(,1)?\),%zmm0/\(bad\) +[ ]*[a-f0-9]+: 62 f1 7c cf c2 c0 00 vcmpeqps %zmm0,%zmm0,%k0\{%k7\}\{z\}/\(bad\) +[ ]*[a-f0-9]+: 62 f1 7c cf 29 00 vmovaps %zmm0,\(%eax\)\{%k7\}\{z\}/\(bad\) +[ ]*[a-f0-9]+: 62 f1 7d 0a c5 c8 00 vpextrw \$(0x)?0,%xmm0,%ecx\{%k2\}/\(bad\) +[ ]*[a-f0-9]+: 62 f3 7d 0a 16 01 00 vpextrd \$(0x)?0,%xmm0,\(%ecx\)\{%k2\}/\(bad\) +[ ]*[a-f0-9]+: 62 f2 7d 4a 2a 01 vmovntdqa \(%ecx\),%zmm0\{%k2\}/\(bad\) #pass diff --git a/gas/testsuite/gas/i386/avx512f-nondef.s b/gas/testsuite/gas/i386/avx512f-nondef.s index a117592..3c4cdff 100644 --- a/gas/testsuite/gas/i386/avx512f-nondef.s +++ b/gas/testsuite/gas/i386/avx512f-nondef.s @@ -26,3 +26,18 @@ .insn EVEX.66.0F38.W0 0x92, (%eax,%zmm1), %zmm0{%k7}{z} # vgatherdps (%eax,%zmm1), %zmm0 # without actual mask register .insn EVEX.66.0F38.W0 0x92, (%eax,%zmm1), %zmm0 + + # vcmpeqps %zmm0, %zmm0, %k0{%k7} with EVEX.z set + .insn EVEX.0f 0xc2, $0, %zmm0, %zmm0, %k0{%k7}{z} + + # vmovaps %zmm0, (%eax){%k7} with EVEX.z set + .insn EVEX.0f 0x29, %zmm0, (%eax){%k7}{z} + + # vpextrw $0, %xmm0, %ecx with non-zero EVEX.aaa + .insn EVEX.66.0f 0xc5, $0, %xmm0, %ecx{%k2} + + # vpextrd $0, %xmm0, (%ecx) with non-zero EVEX.aaa + .insn EVEX.66.0f3a 0x16, $0, %xmm0, (%ecx){%k2} + + # vmovntdqa (%ecx), %zmm0 with non-zero EVEX.aaa + .insn EVEX.66.0f38.W0 0x2a, (%ecx), %zmm0{%k2} diff --git a/gas/testsuite/gas/i386/disassem.d b/gas/testsuite/gas/i386/disassem.d index 7e414a5..eae69db 100644 --- a/gas/testsuite/gas/i386/disassem.d +++ b/gas/testsuite/gas/i386/disassem.d @@ -8,309 +8,309 @@ Disassembly of section \.text: 0+ <\.text>: -[ ]*[a-f0-9]+:[ ]*ff[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*ff[ ]+ljmp[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*ef[ ]*out %eax,\(%dx\) -[ ]*[a-f0-9]+:[ ]*ff[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*ff[ ]+lcall[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*d8 90 90 90 90 90[ ]*fcoms -0x6f6f6f70\(%eax\) -[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%ecx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30 8f[ ]+kshiftrw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30 6a[ ]+kshiftrw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30 04[ ]+kshiftrw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 30 8f[ ]+kshiftrb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 30 6a[ ]+kshiftrb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 30 04[ ]+kshiftrb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31 8f[ ]+kshiftrq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31 6a[ ]+kshiftrq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31 04[ ]+kshiftrq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 31 8f[ ]+kshiftrd[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 31 6a[ ]+kshiftrd[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 31 04[ ]+kshiftrd[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32 8f[ ]+kshiftlw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32 6a[ ]+kshiftlw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32 04[ ]+kshiftlw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 32 8f[ ]+kshiftlb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 32 6a[ ]+kshiftlb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 32 04[ ]+kshiftlb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33 8f[ ]+kshiftlq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33 6a[ ]+kshiftlq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33 04[ ]+kshiftlq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 33 8f[ ]+kshiftld[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 33 6a[ ]+kshiftld[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c4 e3 79 33 04[ ]+kshiftld[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]+pop[ ]+%es +[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas [ ]*[a-f0-9]+:[ ]*c4 e1 f9 92[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait @@ -318,23 +318,23 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 92[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas -[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*aas [ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait @@ -345,6 +345,12 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*c4 e2 01 1c[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*41[ ]*inc[ ]*%ecx [ ]*[a-f0-9]+:[ ]*37[ ]*aaa +[ ]*[a-f0-9]+:[ ]*c4 e2 7f cc[ ]+vsha512msg1[ ]*\(bad\),.* +[ ]*[a-f0-9]+:[ ]*71 20[ ]+jno.* +[ ]*[a-f0-9]+:[ ]*c4 e2 7f cd[ ]+vsha512msg2[ ]*\(bad\),.* +[ ]*[a-f0-9]+:[ ]*71 20[ ]+jno.* +[ ]*[a-f0-9]+:[ ]*c4 e2 6f cb[ ]+vsha512rnds2[ ]*\(bad\),.* +[ ]*[a-f0-9]+:[ ]*71 20[ ]+jno.* [ ]*[a-f0-9]+:[ ]*62 f2 ad 08 1c[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*01 01[ ]*add[ ]*%eax,\(%ecx\) [ ]*[a-f0-9]+:[ ]*62 f3 7d 28 1b[ ]*\(bad\) diff --git a/gas/testsuite/gas/i386/disassem.s b/gas/testsuite/gas/i386/disassem.s index 7c09fad..0fb0dd4 100644 --- a/gas/testsuite/gas/i386/disassem.s +++ b/gas/testsuite/gas/i386/disassem.s @@ -119,30 +119,30 @@ .byte 0xC4, 0xE1, 0xF9, 0x99, 0x9B .byte 0xC4, 0xE1, 0xF9, 0x99, 0x6F .insn VEX.L0.66.0f.W1 0x99, (%edi), %k7 -.byte 0xC4, 0xE3, 0xF9, 0x30, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x30, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x30, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x30, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x30, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x30, 0x04, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x31, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x31, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x31, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x31, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x31, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x31, 0x04, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x32, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x32, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x32, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x32, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x32, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x32, 0x04, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x33, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x33, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x33, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x33, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x33, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x33, 0x04, 0x01 +.byte 0xC4, 0xE3, 0xF9, 0x30, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x30, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x30, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x30, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x30, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x30, 0x04, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x31, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x31, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x31, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x31, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x31, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x31, 0x04, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x32, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x32, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x32, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x32, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x32, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x32, 0x04, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x33, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x33, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x33, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x33, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x33, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x33, 0x04, 0x07 .byte 0xC5, 0xF8, 0x92, 0x9B .byte 0xC5, 0xF8, 0x92, 0x6F .insn VEX.L0.NP.0f.W0 0x92, (%edi), %k7 @@ -168,6 +168,9 @@ .byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F .insn VEX.L0.66.0f.W1 0x93, (%edi), %k7 .byte 0xc4, 0xe2, 0x1, 0x1c, 0x41, 0x37 + .insn VEX.L1.F2.0f38.W0 0xCC, 32(%ecx), %ymm6 + .insn VEX.L1.F2.0f38.W0 0xCD, 32(%ecx), %ymm6 + .insn VEX.L1.F2.0f38.W0 0xCB, 32(%ecx), %ymm2, %ymm6 .byte 0x62, 0xf2, 0xad, 0x08, 0x1c, 0x01 .byte 0x1 .insn EVEX.66.0f3a.W0 0x1b, $0x25, %ymm0, %xmm1 diff --git a/gas/testsuite/gas/i386/i386-intel.d b/gas/testsuite/gas/i386/i386-intel.d index a65c12e..12c0500 100644 --- a/gas/testsuite/gas/i386/i386-intel.d +++ b/gas/testsuite/gas/i386/i386-intel.d @@ -62,45 +62,45 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f b7 00 movzx eax,WORD PTR \[eax\] [ ]*[a-f0-9]+: 0f c3 00 movnti DWORD PTR \[eax\],eax -[ ]*[a-f0-9]+: 63 ca arpl dx,cx -[ ]*[a-f0-9]+: 63 ca arpl dx,cx -[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx -[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx +[ ]*[a-f0-9]+: 63 ca arpl edx,ecx +[ ]*[a-f0-9]+: 63 ca arpl edx,ecx +[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],ecx +[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],ecx [ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx [ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx [ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx [ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\] [ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\] -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx [ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\] [ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx [ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx [ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx [ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\] [ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\] -[ ]*[a-f0-9]+: 0f 00 da ltr dx -[ ]*[a-f0-9]+: 0f 00 da ltr dx +[ ]*[a-f0-9]+: 0f 00 da ltr edx +[ ]*[a-f0-9]+: 0f 00 da ltr edx [ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\] -[ ]*[a-f0-9]+: 0f 00 e2 verr dx -[ ]*[a-f0-9]+: 0f 00 e2 verr dx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx [ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\] -[ ]*[a-f0-9]+: 0f 00 ea verw dx -[ ]*[a-f0-9]+: 0f 00 ea verw dx +[ ]*[a-f0-9]+: 0f 00 ea verw edx +[ ]*[a-f0-9]+: 0f 00 ea verw edx [ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\] -[ ]*[a-f0-9]+: 63 d1 arpl cx,dx -[ ]*[a-f0-9]+: 63 d1 arpl cx,dx -[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx -[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx -[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx -[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx +[ ]*[a-f0-9]+: 63 d1 arpl ecx,edx +[ ]*[a-f0-9]+: 63 d1 arpl ecx,edx +[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx +[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx +[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx +[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx [ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx [ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx [ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx [ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\] [ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\] -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx [ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\] [ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\] [ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx @@ -108,16 +108,16 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx [ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\] [ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\] -[ ]*[a-f0-9]+: 0f 00 da ltr dx -[ ]*[a-f0-9]+: 0f 00 da ltr dx +[ ]*[a-f0-9]+: 0f 00 da ltr edx +[ ]*[a-f0-9]+: 0f 00 da ltr edx [ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\] [ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\] -[ ]*[a-f0-9]+: 0f 00 e2 verr dx -[ ]*[a-f0-9]+: 0f 00 e2 verr dx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx [ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\] [ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\] -[ ]*[a-f0-9]+: 0f 00 ea verw dx -[ ]*[a-f0-9]+: 0f 00 ea verw dx +[ ]*[a-f0-9]+: 0f 00 ea verw edx +[ ]*[a-f0-9]+: 0f 00 ea verw edx [ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\] [ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\] #pass diff --git a/gas/testsuite/gas/i386/i386.d b/gas/testsuite/gas/i386/i386.d index 54e19e8..a77d9f4 100644 --- a/gas/testsuite/gas/i386/i386.d +++ b/gas/testsuite/gas/i386/i386.d @@ -61,45 +61,45 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax [ ]*[a-f0-9]+: 0f b7 00 movzwl \(%eax\),%eax [ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%eax\) -[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx -[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx -[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\) -[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\) +[ ]*[a-f0-9]+: 63 ca arpl %ecx,%edx +[ ]*[a-f0-9]+: 63 ca arpl %ecx,%edx +[ ]*[a-f0-9]+: 63 0a arpl %ecx,\(%edx\) +[ ]*[a-f0-9]+: 63 0a arpl %ecx,\(%edx\) [ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx [ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx [ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx [ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx [ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx [ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\) [ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx [ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx [ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx [ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx [ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx [ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\) -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx [ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\) -[ ]*[a-f0-9]+: 0f 00 ea verw %dx -[ ]*[a-f0-9]+: 0f 00 ea verw %dx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx [ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\) -[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx -[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx -[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\) -[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\) -[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\) -[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\) +[ ]*[a-f0-9]+: 63 d1 arpl %edx,%ecx +[ ]*[a-f0-9]+: 63 d1 arpl %edx,%ecx +[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\) +[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\) +[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\) +[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\) [ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx [ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx [ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx [ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx [ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx [ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\) [ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\) [ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx @@ -107,16 +107,16 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx [ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx [ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx [ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\) [ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\) -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx [ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\) [ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\) -[ ]*[a-f0-9]+: 0f 00 ea verw %dx -[ ]*[a-f0-9]+: 0f 00 ea verw %dx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx [ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\) [ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\) #pass diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index d78f193..90819d8 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -496,6 +496,16 @@ if [gas_32_check] then { run_dump_test "raoint" run_dump_test "raoint-intel" run_list_test "amx-complex-inval" + run_dump_test "avx-vnni-int16" + run_dump_test "avx-vnni-int16-intel" + run_dump_test "sha512" + run_dump_test "sha512-intel" + run_list_test "sha512-inval" + run_dump_test "sm3" + run_dump_test "sm3-intel" + run_dump_test "sm4" + run_dump_test "sm4-intel" + run_list_test "pbndkb-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/intel-intel.d b/gas/testsuite/gas/i386/intel-intel.d index 73fbdf8..4e96969 100644 --- a/gas/testsuite/gas/i386/intel-intel.d +++ b/gas/testsuite/gas/i386/intel-intel.d @@ -103,7 +103,7 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 60 + pusha [ ]*[a-f0-9]+: 61 + popa [ ]*[a-f0-9]+: 62 90 90 90 90 90 + bound edx,QWORD PTR \[eax-0x6f6f6f70\] -[ ]*[a-f0-9]+: 63 90 90 90 90 90 + arpl WORD PTR \[eax-0x6f6f6f70\],dx +[ ]*[a-f0-9]+: 63 90 90 90 90 90 + arpl WORD PTR \[eax-0x6f6f6f70\],edx [ ]*[a-f0-9]+: 68 90 90 90 90 + push 0x90909090 [ ]*[a-f0-9]+: 69 90 90 90 90 90 90 90 90 90 imul edx,DWORD PTR \[eax-0x6f6f6f70\],0x90909090 [ ]*[a-f0-9]+: 6a 90 + push 0xffffff90 diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d index 374f875..bc21289 100644 --- a/gas/testsuite/gas/i386/intel.d +++ b/gas/testsuite/gas/i386/intel.d @@ -102,7 +102,7 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 60 [ ]*pusha [ ]*[a-f0-9]+: 61 [ ]*popa [ ]*[a-f0-9]+: 62 90 90 90 90 90 [ ]*bound %edx,-0x6f6f6f70\(%eax\) -[ ]*[a-f0-9]+: 63 90 90 90 90 90 [ ]*arpl %dx,-0x6f6f6f70\(%eax\) +[ ]*[a-f0-9]+: 63 90 90 90 90 90 [ ]*arpl %edx,-0x6f6f6f70\(%eax\) [ ]*[a-f0-9]+: 68 90 90 90 90 [ ]*push \$0x90909090 [ ]*[a-f0-9]+: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,-0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 6a 90 [ ]*push \$0xffffff90 diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d index 7f641db..c3c920f 100644 --- a/gas/testsuite/gas/i386/opcode-intel.d +++ b/gas/testsuite/gas/i386/opcode-intel.d @@ -102,7 +102,7 @@ Disassembly of section .text: *[0-9a-f]+: 60[ ]+pusha *[0-9a-f]+: 61[ ]+popa *[0-9a-f]+: 62 90 90 90 90 90[ ]+bound[ ]+edx,(QWORD PTR )?\[eax-0x6f6f6f70\] - *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],edx *[0-9a-f]+: 68 90 90 90 90[ ]+push[ ]+0x90909090 *[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imul[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\],0x90909090 *[0-9a-f]+: 6a 90[ ]+push[ ]+0xffffff90 diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d index 152c3b8..946a0a4 100644 --- a/gas/testsuite/gas/i386/opcode-suffix.d +++ b/gas/testsuite/gas/i386/opcode-suffix.d @@ -102,7 +102,7 @@ Disassembly of section .text: *[0-9a-f]+: 60[ ]+pushal *[0-9a-f]+: 61[ ]+popal *[0-9a-f]+: 62 90 90 90 90 90[ ]+boundl %edx,-0x6f6f6f70\(%eax\) - *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpll[ ]+%edx,-0x6f6f6f70\(%eax\) *[0-9a-f]+: 68 90 90 90 90[ ]+pushl[ ]+\$0x90909090 *[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imull[ ]+\$0x90909090,-0x6f6f6f70\(%eax\),%edx *[0-9a-f]+: 6a 90[ ]+pushl[ ]+\$0xffffff90 @@ -248,7 +248,7 @@ Disassembly of section .text: *[0-9a-f]+: fc[ ]+cld *[0-9a-f]+: fd[ ]+std *[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\) - *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldtw[ ]+-0x6f6f6f70\(%eax\) *[0-9a-f]+: 0f 01 90 90 90 90 90[ ]+lgdtl[ ]+-0x6f6f6f70\(%eax\) *[0-9a-f]+: 0f 02 90 90 90 90 90[ ]+larl[ ]+-0x6f6f6f70\(%eax\),%edx *[0-9a-f]+: 0f 03 90 90 90 90 90[ ]+lsll[ ]+-0x6f6f6f70\(%eax\),%edx diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d index c6ffb01..7631195 100644 --- a/gas/testsuite/gas/i386/opcode.d +++ b/gas/testsuite/gas/i386/opcode.d @@ -101,7 +101,7 @@ Disassembly of section .text: 123: 60 [ ]*pusha 124: 61 [ ]*popa 125: 62 90 90 90 90 90 [ ]*bound %edx,-0x6f6f6f70\(%eax\) - 12b: 63 90 90 90 90 90 [ ]*arpl %dx,-0x6f6f6f70\(%eax\) + 12b: 63 90 90 90 90 90 [ ]*arpl %edx,-0x6f6f6f70\(%eax\) 131: 68 90 90 90 90 [ ]*push \$0x90909090 136: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,-0x6f6f6f70\(%eax\),%edx 140: 6a 90 [ ]*push \$0xffffff90 diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d index f6c54b7..23d715c 100644 --- a/gas/testsuite/gas/i386/optimize-1.d +++ b/gas/testsuite/gas/i386/optimize-1.d @@ -147,6 +147,21 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax diff --git a/gas/testsuite/gas/i386/optimize-1.s b/gas/testsuite/gas/i386/optimize-1.s index 53a0dd7..e253142 100644 --- a/gas/testsuite/gas/i386/optimize-1.s +++ b/gas/testsuite/gas/i386/optimize-1.s @@ -171,6 +171,25 @@ _start: vpxord 128(%eax), %ymm2, %ymm3 vpxorq 128(%eax), %ymm2, %ymm3 + pcmpgtb %mm2, %mm2 + pcmpgtb %xmm2, %xmm2 + vpcmpgtb %xmm2, %xmm2, %xmm0 + vpcmpgtb %ymm2, %ymm2, %ymm0 + + pcmpgtw %mm2, %mm2 + pcmpgtw %xmm2, %xmm2 + vpcmpgtw %xmm2, %xmm2, %xmm0 + vpcmpgtw %ymm2, %ymm2, %ymm0 + + pcmpgtd %mm2, %mm2 + pcmpgtd %xmm2, %xmm2 + vpcmpgtd %xmm2, %xmm2, %xmm0 + vpcmpgtd %ymm2, %ymm2, %ymm0 + + pcmpgtq %xmm2, %xmm2 + vpcmpgtq %xmm2, %xmm2, %xmm0 + vpcmpgtq %ymm2, %ymm2, %ymm0 + bt $15, %ax bt $16, %ax btc $15, %ax diff --git a/gas/testsuite/gas/i386/optimize-1a.d b/gas/testsuite/gas/i386/optimize-1a.d index d0bf1b4..33c647b 100644 --- a/gas/testsuite/gas/i386/optimize-1a.d +++ b/gas/testsuite/gas/i386/optimize-1a.d @@ -148,6 +148,21 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax diff --git a/gas/testsuite/gas/i386/optimize-2.d b/gas/testsuite/gas/i386/optimize-2.d index 571059e..41056fb 100644 --- a/gas/testsuite/gas/i386/optimize-2.d +++ b/gas/testsuite/gas/i386/optimize-2.d @@ -161,4 +161,8 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq \(%eax\)\{1to2\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxord \(%eax\)\{1to4\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxorq \(%eax\)\{1to4\},%ymm2,%ymm3 + +[a-f0-9]+: 66 .* pcmpeqd %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpcmpeqd %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpcmpeqd %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: c5 .* vpunpcklqdq %xmm2,%xmm2,%xmm0 #pass diff --git a/gas/testsuite/gas/i386/optimize-2.s b/gas/testsuite/gas/i386/optimize-2.s index 43af945..29399ae 100644 --- a/gas/testsuite/gas/i386/optimize-2.s +++ b/gas/testsuite/gas/i386/optimize-2.s @@ -180,3 +180,9 @@ _start: vporq (%eax){1to2}, %xmm2, %xmm3 vpxord (%eax){1to4}, %xmm2, %xmm3 vpxorq (%eax){1to4}, %ymm2, %ymm3 + + pcmpeqq %xmm2, %xmm2 + vpcmpeqq %xmm2, %xmm2, %xmm0 + vpcmpeqq %ymm2, %ymm2, %ymm0 + + vpbroadcastq %xmm2, %xmm0 diff --git a/gas/testsuite/gas/i386/optimize-2b.d b/gas/testsuite/gas/i386/optimize-2b.d index 5863688..d9e8319 100644 --- a/gas/testsuite/gas/i386/optimize-2b.d +++ b/gas/testsuite/gas/i386/optimize-2b.d @@ -162,4 +162,8 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq \(%eax\)\{1to2\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxord \(%eax\)\{1to4\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxorq \(%eax\)\{1to4\},%ymm2,%ymm3 + +[a-f0-9]+: 66 .* pcmpeqq %xmm2,%xmm2 + +[a-f0-9]+: c4 .* vpcmpeqq %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c4 .* vpcmpeqq %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: c4 .* vpbroadcastq %xmm2,%xmm0 #pass diff --git a/gas/testsuite/gas/i386/optimize-4.d b/gas/testsuite/gas/i386/optimize-4.d index 092d078..fa9b95f 100644 --- a/gas/testsuite/gas/i386/optimize-4.d +++ b/gas/testsuite/gas/i386/optimize-4.d @@ -147,6 +147,21 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax diff --git a/gas/testsuite/gas/i386/optimize-5.d b/gas/testsuite/gas/i386/optimize-5.d index 1d1397b..36d0ba9 100644 --- a/gas/testsuite/gas/i386/optimize-5.d +++ b/gas/testsuite/gas/i386/optimize-5.d @@ -147,6 +147,21 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0 +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax diff --git a/gas/testsuite/gas/i386/x86-64-disassem.d b/gas/testsuite/gas/i386/x86-64-disassem.d index 6e4dd91..2de30e2 100644 --- a/gas/testsuite/gas/i386/x86-64-disassem.d +++ b/gas/testsuite/gas/i386/x86-64-disassem.d @@ -8,309 +8,309 @@ Disassembly of section \.text: 0+ <\.text>: -[ ]*[a-f0-9]+:[ ]*ff[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*ff[ ]+ljmp[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*ef[ ]*out %eax,\(%dx\) -[ ]*[a-f0-9]+:[ ]*ff[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*ff[ ]+lcall[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*d8 90 90 90 90 90[ ]*fcoms -0x6f6f6f70\(%rax\) -[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 30[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 31[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 32[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c4 e3 79 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*8f 01[ ]*pop \(%rcx\) -[ ]*[a-f0-9]+:[ ]*c4 e3 79 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6a 01[ ]*push \$0x1 -[ ]*[a-f0-9]+:[ ]*c4 e3 79 33[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*04 01[ ]*add \$0x1,%al -[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30 8f[ ]+kshiftrw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30 6a[ ]+kshiftrw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 30 04[ ]+kshiftrw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 30 8f[ ]+kshiftrb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 30 6a[ ]+kshiftrb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 30 04[ ]+kshiftrb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31 8f[ ]+kshiftrq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31 6a[ ]+kshiftrq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 31 04[ ]+kshiftrq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 31 8f[ ]+kshiftrd[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 31 6a[ ]+kshiftrd[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 31 04[ ]+kshiftrd[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32 8f[ ]+kshiftlw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32 6a[ ]+kshiftlw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 32 04[ ]+kshiftlw[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 32 8f[ ]+kshiftlb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 32 6a[ ]+kshiftlb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 32 04[ ]+kshiftlb[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33 8f[ ]+kshiftlq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33 6a[ ]+kshiftlq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 f9 33 04[ ]+kshiftlq[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 33 8f[ ]+kshiftld[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 33 6a[ ]+kshiftld[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c4 e3 79 33 04[ ]+kshiftld[ ]*\$0x[0-9a-f]*,\(bad\),.* +[ ]*[a-f0-9]+:[ ]*07[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 92[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait @@ -318,23 +318,23 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 92[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait -[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) -[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]*\(bad\) +[ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait diff --git a/gas/testsuite/gas/i386/x86-64-disassem.s b/gas/testsuite/gas/i386/x86-64-disassem.s index ff04904..4f151bf 100644 --- a/gas/testsuite/gas/i386/x86-64-disassem.s +++ b/gas/testsuite/gas/i386/x86-64-disassem.s @@ -119,30 +119,30 @@ .byte 0xC4, 0xE1, 0xF9, 0x99, 0x9B .byte 0xC4, 0xE1, 0xF9, 0x99, 0x6F .insn VEX.L0.66.0f.W1 0x99, (%rdi), %k7 -.byte 0xC4, 0xE3, 0xF9, 0x30, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x30, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x30, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x30, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x30, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x30, 0x04, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x31, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x31, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x31, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x31, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x31, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x31, 0x04, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x32, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x32, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x32, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x32, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x32, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x32, 0x04, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x33, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x33, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0xF9, 0x33, 0x04, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x33, 0x8F, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x33, 0x6A, 0x01 -.byte 0xC4, 0xE3, 0x79, 0x33, 0x04, 0x01 +.byte 0xC4, 0xE3, 0xF9, 0x30, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x30, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x30, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x30, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x30, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x30, 0x04, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x31, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x31, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x31, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x31, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x31, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x31, 0x04, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x32, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x32, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x32, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x32, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x32, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x32, 0x04, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x33, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x33, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0xF9, 0x33, 0x04, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x33, 0x8F, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x33, 0x6A, 0x07 +.byte 0xC4, 0xE3, 0x79, 0x33, 0x04, 0x07 .byte 0xC5, 0xF8, 0x92, 0x9B .byte 0xC5, 0xF8, 0x92, 0x6F .insn VEX.L0.NP.0f.W0 0x92, (%rdi), %k7 diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-intel.d b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d index 0f4a6fb..b981ad5 100644 --- a/gas/testsuite/gas/i386/x86-64-lkgs-intel.d +++ b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d @@ -8,16 +8,16 @@ Disassembly of section \.text: 0+ <_start>: -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d \s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\] \s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\] \s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\] \s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs WORD PTR \[rdx-0x100\] -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d \s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\] \s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\] \s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\] diff --git a/gas/testsuite/gas/i386/x86-64-lkgs.d b/gas/testsuite/gas/i386/x86-64-lkgs.d index 207143d..60af3c4 100644 --- a/gas/testsuite/gas/i386/x86-64-lkgs.d +++ b/gas/testsuite/gas/i386/x86-64-lkgs.d @@ -8,16 +8,16 @@ Disassembly of section \.text: 0+ <_start>: -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d \s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\) \s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\) \s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\) \s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs -0x100\(%rdx\) -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w -\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d \s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\) \s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\) \s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\) diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.d b/gas/testsuite/gas/i386/x86-64-optimize-2.d index cb6b815..87bf3ed 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-2.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d @@ -203,4 +203,23 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 #pass diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.s b/gas/testsuite/gas/i386/x86-64-optimize-2.s index 22dbd1c..3d16a78 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-2.s +++ b/gas/testsuite/gas/i386/x86-64-optimize-2.s @@ -226,3 +226,26 @@ _start: vporq 128(%rax), %ymm2, %ymm3 vpxord 128(%rax), %ymm2, %ymm3 vpxorq 128(%rax), %ymm2, %ymm3 + + pcmpgtb %mm2, %mm2 + pcmpgtb %xmm2, %xmm2 + pcmpgtb %xmm12, %xmm12 + vpcmpgtb %xmm2, %xmm2, %xmm8 + vpcmpgtb %ymm12, %ymm12, %ymm1 + + pcmpgtw %mm2, %mm2 + pcmpgtw %xmm2, %xmm2 + pcmpgtw %xmm12, %xmm12 + vpcmpgtw %xmm2, %xmm2, %xmm8 + vpcmpgtw %ymm12, %ymm12, %ymm1 + + pcmpgtd %mm2, %mm2 + pcmpgtd %xmm2, %xmm2 + pcmpgtd %xmm12, %xmm12 + vpcmpgtd %xmm2, %xmm2, %xmm8 + vpcmpgtd %ymm12, %ymm12, %ymm1 + + pcmpgtq %xmm2, %xmm2 + pcmpgtq %xmm12, %xmm12 + vpcmpgtq %xmm2, %xmm2, %xmm8 + vpcmpgtq %ymm12, %ymm12, %ymm1 diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2a.d b/gas/testsuite/gas/i386/x86-64-optimize-2a.d index 70a8ff3..f12507b 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-2a.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-2a.d @@ -204,4 +204,23 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 #pass diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2b.d b/gas/testsuite/gas/i386/x86-64-optimize-2b.d index 1d81569..e572491 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-2b.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-2b.d @@ -203,4 +203,23 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 #pass diff --git a/gas/testsuite/gas/i386/x86-64-optimize-3.d b/gas/testsuite/gas/i386/x86-64-optimize-3.d index 26122dd..23b9305 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-3.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-3.d @@ -199,4 +199,12 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq \(%rax\)\{1to2\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxord \(%rax\)\{1to4\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxorq \(%rax\)\{1to4\},%ymm2,%ymm3 + +[a-f0-9]+: 66 .* pcmpeqd %xmm2,%xmm2 + +[a-f0-9]+: c5 .* vpcmpeqd %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c5 .* vpcmpeqd %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 66 .* pcmpeqd %xmm12,%xmm12 + +[a-f0-9]+: c4 .* vpcmpeqq %xmm12,%xmm12,%xmm0 + +[a-f0-9]+: c4 .* vpcmpeqq %ymm12,%ymm12,%ymm0 + +[a-f0-9]+: c5 .* vpunpcklqdq %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c4 .* vpbroadcastq %xmm12,%xmm0 #pass diff --git a/gas/testsuite/gas/i386/x86-64-optimize-3.s b/gas/testsuite/gas/i386/x86-64-optimize-3.s index cbfed3b..bab99cf 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-3.s +++ b/gas/testsuite/gas/i386/x86-64-optimize-3.s @@ -221,3 +221,14 @@ _start: vporq (%rax){1to2}, %xmm2, %xmm3 vpxord (%rax){1to4}, %xmm2, %xmm3 vpxorq (%rax){1to4}, %ymm2, %ymm3 + + pcmpeqq %xmm2, %xmm2 + vpcmpeqq %xmm2, %xmm2, %xmm0 + vpcmpeqq %ymm2, %ymm2, %ymm0 + + pcmpeqq %xmm12, %xmm12 + vpcmpeqq %xmm12, %xmm12, %xmm0 + vpcmpeqq %ymm12, %ymm12, %ymm0 + + vpbroadcastq %xmm2, %xmm0 + vpbroadcastq %xmm12, %xmm0 diff --git a/gas/testsuite/gas/i386/x86-64-optimize-3b.d b/gas/testsuite/gas/i386/x86-64-optimize-3b.d index 00b65f3..929c6f7 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-3b.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-3b.d @@ -200,4 +200,12 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq \(%rax\)\{1to2\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxord \(%rax\)\{1to4\},%xmm2,%xmm3 +[a-f0-9]+: 62 .* vpxorq \(%rax\)\{1to4\},%ymm2,%ymm3 + +[a-f0-9]+: 66 .* pcmpeqq %xmm2,%xmm2 + +[a-f0-9]+: c4 .* vpcmpeqq %xmm2,%xmm2,%xmm0 + +[a-f0-9]+: c4 .* vpcmpeqq %ymm2,%ymm2,%ymm0 + +[a-f0-9]+: 66 .* pcmpeqq %xmm12,%xmm12 + +[a-f0-9]+: c4 .* vpcmpeqq %xmm12,%xmm12,%xmm0 + +[a-f0-9]+: c4 .* vpcmpeqq %ymm12,%ymm12,%ymm0 + +[a-f0-9]+: c4 .* vpbroadcastq %xmm2,%xmm0 + +[a-f0-9]+: c4 .* vpbroadcastq %xmm12,%xmm0 #pass diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.d b/gas/testsuite/gas/i386/x86-64-optimize-5.d index 9fd0ec2..5b272aa 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-5.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d @@ -203,6 +203,25 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2 diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.d b/gas/testsuite/gas/i386/x86-64-optimize-6.d index 6cacaf9..48105c3 100644 --- a/gas/testsuite/gas/i386/x86-64-optimize-6.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d @@ -203,6 +203,25 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 0f .* pxor %mm2,%mm2 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 + +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2 + +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12 + +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8 + +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1 +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 48ec9c2..52711cd 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -437,7 +437,19 @@ run_dump_test "x86-64-amx-complex-bad" run_list_test "x86-64-amx-complex-inval" run_dump_test "x86-64-fred" run_dump_test "x86-64-lkgs" +run_dump_test "x86-64-lkgs-intel" run_list_test "x86-64-lkgs-inval" +run_dump_test "x86-64-avx-vnni-int16" +run_dump_test "x86-64-avx-vnni-int16-intel" +run_dump_test "x86-64-sha512" +run_dump_test "x86-64-sha512-intel" +run_list_test "x86-64-sha512-inval" +run_dump_test "x86-64-sm3" +run_dump_test "x86-64-sm3-intel" +run_dump_test "x86-64-sm4" +run_dump_test "x86-64-sm4-intel" +run_dump_test "x86-64-pbndkb" +run_dump_test "x86-64-pbndkb-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" @@ -520,6 +532,7 @@ run_dump_test "x86-64-optimize-1" run_dump_test "x86-64-optimize-2" run_dump_test "x86-64-optimize-2a" run_dump_test "x86-64-optimize-2b" +run_dump_test "x86-64-optimize-2c" run_dump_test "x86-64-optimize-3" run_dump_test "x86-64-optimize-3b" run_dump_test "x86-64-optimize-4" diff --git a/gas/testsuite/gas/i386/x86_64-intel.d b/gas/testsuite/gas/i386/x86_64-intel.d index 6b74ae6..2a9b7d4 100644 --- a/gas/testsuite/gas/i386/x86_64-intel.d +++ b/gas/testsuite/gas/i386/x86_64-intel.d @@ -266,9 +266,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\] -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx [ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\] [ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx [ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx @@ -278,17 +278,17 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\] -[ ]*[a-f0-9]+: 0f 00 da ltr dx -[ ]*[a-f0-9]+: 0f 00 da ltr dx -[ ]*[a-f0-9]+: 0f 00 da ltr dx +[ ]*[a-f0-9]+: 0f 00 da ltr edx +[ ]*[a-f0-9]+: 0f 00 da ltr edx +[ ]*[a-f0-9]+: 0f 00 da ltr edx [ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\] -[ ]*[a-f0-9]+: 0f 00 e2 verr dx -[ ]*[a-f0-9]+: 0f 00 e2 verr dx -[ ]*[a-f0-9]+: 0f 00 e2 verr dx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx [ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\] -[ ]*[a-f0-9]+: 0f 00 ea verw dx -[ ]*[a-f0-9]+: 0f 00 ea verw dx -[ ]*[a-f0-9]+: 0f 00 ea verw dx +[ ]*[a-f0-9]+: 0f 00 ea verw edx +[ ]*[a-f0-9]+: 0f 00 ea verw edx +[ ]*[a-f0-9]+: 0f 00 ea verw edx [ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\] [ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx [ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx @@ -298,9 +298,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\] -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt edx [ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\] [ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\] [ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx @@ -311,19 +311,19 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\] [ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\] -[ ]*[a-f0-9]+: 0f 00 da ltr dx -[ ]*[a-f0-9]+: 0f 00 da ltr dx -[ ]*[a-f0-9]+: 0f 00 da ltr dx +[ ]*[a-f0-9]+: 0f 00 da ltr edx +[ ]*[a-f0-9]+: 0f 00 da ltr edx +[ ]*[a-f0-9]+: 0f 00 da ltr edx [ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\] [ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\] -[ ]*[a-f0-9]+: 0f 00 e2 verr dx -[ ]*[a-f0-9]+: 0f 00 e2 verr dx -[ ]*[a-f0-9]+: 0f 00 e2 verr dx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx +[ ]*[a-f0-9]+: 0f 00 e2 verr edx [ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\] [ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\] -[ ]*[a-f0-9]+: 0f 00 ea verw dx -[ ]*[a-f0-9]+: 0f 00 ea verw dx -[ ]*[a-f0-9]+: 0f 00 ea verw dx +[ ]*[a-f0-9]+: 0f 00 ea verw edx +[ ]*[a-f0-9]+: 0f 00 ea verw edx +[ ]*[a-f0-9]+: 0f 00 ea verw edx [ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\] [ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\] #pass diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d index cdfe12e..aa38661 100644 --- a/gas/testsuite/gas/i386/x86_64.d +++ b/gas/testsuite/gas/i386/x86_64.d @@ -266,9 +266,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx [ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx [ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx [ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\) [ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx [ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx @@ -278,17 +278,17 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx [ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx [ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx [ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\) -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx [ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\) -[ ]*[a-f0-9]+: 0f 00 ea verw %dx -[ ]*[a-f0-9]+: 0f 00 ea verw %dx -[ ]*[a-f0-9]+: 0f 00 ea verw %dx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx [ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\) [ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx [ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx @@ -298,9 +298,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx [ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx [ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx -[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx +[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx [ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\) [ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\) [ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx @@ -311,19 +311,19 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx [ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx [ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx -[ ]*[a-f0-9]+: 0f 00 da ltr %dx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx +[ ]*[a-f0-9]+: 0f 00 da ltr %edx [ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\) [ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\) -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx -[ ]*[a-f0-9]+: 0f 00 e2 verr %dx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx +[ ]*[a-f0-9]+: 0f 00 e2 verr %edx [ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\) [ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\) -[ ]*[a-f0-9]+: 0f 00 ea verw %dx -[ ]*[a-f0-9]+: 0f 00 ea verw %dx -[ ]*[a-f0-9]+: 0f 00 ea verw %dx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx +[ ]*[a-f0-9]+: 0f 00 ea verw %edx [ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\) [ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\) #pass diff --git a/gas/testsuite/gas/ppc/aix.exp b/gas/testsuite/gas/ppc/aix.exp index 55aedc4..76ffb22 100644 --- a/gas/testsuite/gas/ppc/aix.exp +++ b/gas/testsuite/gas/ppc/aix.exp @@ -88,8 +88,15 @@ if { [istarget "powerpc*-*-aix*"] || [istarget "rs6000-*-aix*"] } then { run_dump_test "xcoff-file-32" run_dump_test "xcoff-file-64" - run_dump_test "xcoff-visibility-1-32" - run_dump_test "xcoff-visibility-1-64" + if { [istarget {*-*-aix[6-9]*}] + || [istarget {*-*-aix5.[2-9]*}] } { + # The expected output of these tests depends on AIX_WEAK_SUPPORT. + # Without that weak syms do not have an aux entry and thus + # BFD_NOT_AT_END is not set. I don't know if any of this is + # correct.. + run_dump_test "xcoff-visibility-1-32" + run_dump_test "xcoff-visibility-1-64" + } run_dump_test "xcoff-visibility-2-32" run_dump_test "xcoff-visibility-2-64" } diff --git a/gas/testsuite/gas/s390/esa-reloc.d b/gas/testsuite/gas/s390/esa-reloc.d index c9da928..0b13cb6 100644 --- a/gas/testsuite/gas/s390/esa-reloc.d +++ b/gas/testsuite/gas/s390/esa-reloc.d @@ -23,7 +23,7 @@ Disassembly of section .text: 22: a7 08 00 00 [ ]*lhi %r0,0 [ ]*24: R_390_GOT16 test_R_390_GOT16 26: a7 08 00 00 [ ]*lhi %r0,0 -[ ]*28: R_390_16 test_R_390_PC16\+0x26 +[ ]*28: R_390_PC16 test_R_390_PC16\+0x28 2a: a7 e5 00 00 [ ]*bras %r14,2a <foo\+0x2a> [ ]*2c: R_390_PC16DBL test_R_390_PC16DBL\+0x2 2e: a7 e5 00 00 [ ]*bras %r14,2e <foo\+0x2e> diff --git a/gas/testsuite/gas/sh/err-at.s b/gas/testsuite/gas/sh/err-at.s index 648ee94..af5d081 100644 --- a/gas/testsuite/gas/sh/err-at.s +++ b/gas/testsuite/gas/sh/err-at.s @@ -4,7 +4,9 @@ start: mov.l r1,@r0 ! ok mov.l r1,@(r0) ! { dg-error "syntax error" } +! { dg-bogus "invalid operands for opcode" "" { xfail *-*-* } 6 } mov.l r1,@(r0,) ! { dg-error "syntax error" } +! { dg-bogus "invalid operands for opcode" "" { xfail *-*-* } 8 } mov.l r1,@(r0,r0) ! ok mov.l r1,@(r0,r1) ! ok mov.l r1,@(r1,r0) ! { dg-error "must be" } |