diff options
author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2021-01-05 17:39:04 +0000 |
---|---|---|
committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2021-01-11 15:01:09 +0000 |
commit | 82c70b08dfb47bf56ce78fbd9147d38f51ecdeb8 (patch) | |
tree | 8027bec80ca4a29fa74c6adaa3e58dfc57f16eda /gas | |
parent | c0f6e439cc59fa60fec3a4c4ff56e6fac52a8c65 (diff) | |
download | gdb-82c70b08dfb47bf56ce78fbd9147d38f51ecdeb8.zip gdb-82c70b08dfb47bf56ce78fbd9147d38f51ecdeb8.tar.gz gdb-82c70b08dfb47bf56ce78fbd9147d38f51ecdeb8.tar.bz2 |
aarch64: Remove support for CSRE
This patch removes support for the CSRE extension from aarch64
gas/objdump.
CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program
and at this time Arm is withdrawing this particular feature.
The patch removes the system registers and the CSR PDEC instruction.
gas/ChangeLog
* NEWS: Remove CSRE.
* config/tc-aarch64.c (parse_csr_operand): Delete.
(parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR.
(aarch64_features): Remove csre.
* doc/c-aarch64.texi: Remove CSRE.
* testsuite/gas/aarch64/csre.d: Delete.
* testsuite/gas/aarch64/csre-invalid.s: Likewise.
* testsuite/gas/aarch64/csre-invalid.d: Likewise.
* testsuite/gas/aarch64/csre_csr.s: Likewise.
* testsuite/gas/aarch64/csre_csr.d: Likewise.
* testsuite/gas/aarch64/csre_csr-invalid.s: Likewise.
* testsuite/gas/aarch64/csre_csr-invalid.l: Likewise.
* testsuite/gas/aarch64/csre_csr-invalid.d: Likewise.
include/ChangeLog
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete.
(aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR.
opcodes/ChangeLog
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-opc.c (aarch64_print_operand): Delete handling of
AARCH64_OPND_CSRE_CSR.
* aarch64-tbl.h (aarch64_feature_csre): Delete.
(CSRE): Likewise.
(_CSRE_INSN): Likewise.
(aarch64_opcode_table): Delete csr.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 17 | ||||
-rw-r--r-- | gas/NEWS | 8 | ||||
-rw-r--r-- | gas/config/tc-aarch64.c | 31 | ||||
-rw-r--r-- | gas/doc/c-aarch64.texi | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre-invalid.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre-invalid.s | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre.d | 29 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr.d | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr.s | 4 |
12 files changed, 19 insertions, 100 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index da9b400..d65b621 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,20 @@ +2021-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * NEWS: Remove CSRE. + * config/tc-aarch64.c (parse_csr_operand): Delete. + (parse_operands): Delete handling of + AARCH64_OPND_CSRE_CSR. + (aarch64_features): Remove csre. + * doc/c-aarch64.texi: Remove CSRE. + * testsuite/gas/aarch64/csre.d: Delete. + * testsuite/gas/aarch64/csre-invalid.s: Likewise. + * testsuite/gas/aarch64/csre-invalid.d: Likewise. + * testsuite/gas/aarch64/csre_csr.s: Likewise. + * testsuite/gas/aarch64/csre_csr.d: Likewise. + * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. + * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. + * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. + 2021-01-11 Nick Clifton <nickc@redhat.com> * po/uk.po: Updated Ukranian translation. @@ -18,18 +18,14 @@ Changes in 2.36: Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM. * Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace - Extension), TRBE (Trace Buffer Extension), CSRE (Call Stack Recorder - Extension) and BRBE (Branch Record Buffer Extension) system registers for - AArch64. + Extension), TRBE (Trace Buffer Extension)and BRBE (Branch Record Buffer + Extension) system registers for AArch64. * Add support for Armv8-R and Armv8.7-A AArch64. * Add support for DSB memory nXS barrier, WFET and WFIT instruction for Armv8.7 AArch64. -* Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE - feature in AArch64. - * Add support for +flagm feature for -march in Armv8.4 AArch64. * Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index b04605c..6f782d0 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4036,29 +4036,6 @@ parse_barrier_psb (char **str, return 0; } -/* Parse an operand for CSR (CSRE instruction). */ - -static int -parse_csr_operand (char **str) -{ - char *p, *q; - - p = q = *str; - while (ISALPHA (*q)) - q++; - - /* Instruction has only one operand PDEC which encodes Rt field of the - operation to 0b11111. */ - if (strcasecmp(p, "pdec")) - { - set_syntax_error (_("CSR instruction accepts only PDEC")); - return PARSE_FAIL; - } - - *str = q; - return 0; -} - /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record return 0 if successful. Otherwise return PARSE_FAIL. */ @@ -6793,12 +6770,6 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; break; - case AARCH64_OPND_CSRE_CSR: - val = parse_csr_operand (&str); - if (val == PARSE_FAIL) - goto failure; - break; - default: as_fatal (_("unhandled operand code %d"), operands[i]); } @@ -9230,8 +9201,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)}, {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0), AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)}, - {"csre", AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0), - AARCH64_ARCH_NONE}, {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0), AARCH64_ARCH_NONE}, {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0), diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 5bd60c6..79dce2f 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -229,8 +229,6 @@ automatically cause those extensions to be disabled. @tab Enable SVE2 SHA3 Extension. @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later @tab Enable Flag Manipulation instructions. -@item @code{csre} @tab ARMv8-A @tab No - @tab Enable Call Stack Recorder Extension. @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later @tab Enable 64 Byte Loads/Stores. @item @code{pauth} @tab ARMv8-A @tab No diff --git a/gas/testsuite/gas/aarch64/csre-invalid.d b/gas/testsuite/gas/aarch64/csre-invalid.d deleted file mode 100644 index f273b65..0000000 --- a/gas/testsuite/gas/aarch64/csre-invalid.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: Invalid CSRE System registers usage -#source: csre-invalid.s -#warning_output: csre-invalid.l diff --git a/gas/testsuite/gas/aarch64/csre-invalid.s b/gas/testsuite/gas/aarch64/csre-invalid.s deleted file mode 100644 index 424f50a..0000000 --- a/gas/testsuite/gas/aarch64/csre-invalid.s +++ /dev/null @@ -1,6 +0,0 @@ -/* Write to read-only CSRE system registers. */ - -msr csridr_el0 ,x0 -msr csrptridx_el0 ,x0 -msr csrptridx_el1 ,x0 -msr csrptridx_el2 ,x0 diff --git a/gas/testsuite/gas/aarch64/csre.d b/gas/testsuite/gas/aarch64/csre.d deleted file mode 100644 index ac77d4a..0000000 --- a/gas/testsuite/gas/aarch64/csre.d +++ /dev/null @@ -1,29 +0,0 @@ -#name: CSRE System registers -#objdump: -dr - -.*: file format .* - - -Disassembly of section \.text: - -0+ <.*>: -[^:]+: d5338000 mrs x0, csrcr_el0 -[^:]+: d5338020 mrs x0, csrptr_el0 -[^:]+: d5338040 mrs x0, csridr_el0 -[^:]+: d5338060 mrs x0, csrptridx_el0 -[^:]+: d5308000 mrs x0, csrcr_el1 -[^:]+: d5358000 mrs x0, csrcr_el12 -[^:]+: d5308020 mrs x0, csrptr_el1 -[^:]+: d5358020 mrs x0, csrptr_el12 -[^:]+: d5308060 mrs x0, csrptridx_el1 -[^:]+: d5348000 mrs x0, csrcr_el2 -[^:]+: d5348020 mrs x0, csrptr_el2 -[^:]+: d5348060 mrs x0, csrptridx_el2 -[^:]+: d5138000 msr csrcr_el0, x0 -[^:]+: d5138020 msr csrptr_el0, x0 -[^:]+: d5108000 msr csrcr_el1, x0 -[^:]+: d5158000 msr csrcr_el12, x0 -[^:]+: d5108020 msr csrptr_el1, x0 -[^:]+: d5158020 msr csrptr_el12, x0 -[^:]+: d5148000 msr csrcr_el2, x0 -[^:]+: d5148020 msr csrptr_el2, x0 diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.d b/gas/testsuite/gas/aarch64/csre_csr-invalid.d deleted file mode 100644 index bec71c8..0000000 --- a/gas/testsuite/gas/aarch64/csre_csr-invalid.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: CSR PDEC instruction -#source: csre_csr-invalid.s -#error_output: csre_csr-invalid.l diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.l b/gas/testsuite/gas/aarch64/csre_csr-invalid.l deleted file mode 100644 index dec38ab..0000000 --- a/gas/testsuite/gas/aarch64/csre_csr-invalid.l +++ /dev/null @@ -1,2 +0,0 @@ -.*: Assembler messages: -.*: Error: selected processor does not support `csr pdec' diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.s b/gas/testsuite/gas/aarch64/csre_csr-invalid.s deleted file mode 100644 index e8520ba..0000000 --- a/gas/testsuite/gas/aarch64/csre_csr-invalid.s +++ /dev/null @@ -1,4 +0,0 @@ -/* CSR PDEC requires +csre for -march= command line option. */ -.arch armv8-a - - csr pdec diff --git a/gas/testsuite/gas/aarch64/csre_csr.d b/gas/testsuite/gas/aarch64/csre_csr.d deleted file mode 100644 index c242f0a..0000000 --- a/gas/testsuite/gas/aarch64/csre_csr.d +++ /dev/null @@ -1,10 +0,0 @@ -#name: CSRE extension CSR PDEC instruction -#objdump: -dr - -.*: file format .* - -Disassembly of section \.text: - -0+ <.*>: -.*: d50b721f csr pdec -.*: d50b721f csr pdec diff --git a/gas/testsuite/gas/aarch64/csre_csr.s b/gas/testsuite/gas/aarch64/csre_csr.s deleted file mode 100644 index d0ac90f..0000000 --- a/gas/testsuite/gas/aarch64/csre_csr.s +++ /dev/null @@ -1,4 +0,0 @@ -.arch armv8-a+csre - - csr pdec - CSR PDEC |