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| author | Jens Remus <jremus@linux.ibm.com> | 2024-03-01 12:45:14 +0100 |
|---|---|---|
| committer | Jens Remus <jremus@linux.ibm.com> | 2024-03-01 12:45:14 +0100 |
| commit | 75a28d1a97ace81c8481fd1c85d21e6f22e68924 (patch) | |
| tree | ad764109e3f3fa1a0228078d50c6e35210589286 /gas | |
| parent | dfa4ac9728ce8999a9b53d1ef37b175380940ee5 (diff) | |
| download | gdb-75a28d1a97ace81c8481fd1c85d21e6f22e68924.zip gdb-75a28d1a97ace81c8481fd1c85d21e6f22e68924.tar.gz gdb-75a28d1a97ace81c8481fd1c85d21e6f22e68924.tar.bz2 | |
s390: Print base register 0 as "0" in disassembly
Base and index register 0 have no effect in address computation:
"A value of zero in the B [base] or X [index] field specifies that no
base or index is to be applied, and, thus, general register 0 cannot be
designated as containing a base address or index."
IBM z/Architecture Principles of Operation [1], chapter "Organization",
section "General Registers".
Index register 0 is omitted in the s390 disassembly. Base register 0 is
omitted in D(B), D(L,B) and D(X,B) - the latter only if the index
register is zero.
To make it more apparent print base register 0 as "0" instead of "%r0",
whenever it would still be printed in the disassembly.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-dis.c: Print base register 0 as "0" in disassembly.
binutils/
* NEWS: Mention base register 0 now being printed as "0" in s390
disassembly.
gas/
* testsuite/gas/s390/zarch-base-index-0.d: Update test case
output verification patterns to accept "0" as base base
register due to disassembler output format change.
* gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/s390/zarch-base-index-0.d | 66 | ||||
| -rw-r--r-- | gas/testsuite/gas/s390/zarch-omitted-base-index.d | 4 |
2 files changed, 35 insertions, 35 deletions
diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.d b/gas/testsuite/gas/s390/zarch-base-index-0.d index e626604..4dd913b 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0.d +++ b/gas/testsuite/gas/s390/zarch-base-index-0.d @@ -17,8 +17,8 @@ Disassembly of section .text: .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 @@ -31,46 +31,46 @@ Disassembly of section .text: .*: 5a 00 00 00 [ ]*a %r0,0 .*: 5a 00 00 00 [ ]*a %r0,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,%r0\),0 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,0\),0 .*: f3 01 10 10 20 20 [ ]*unpk 16\(1,%r1\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,%r0\),0\(2,%r0\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,0\),0\(2,0\) .*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.d b/gas/testsuite/gas/s390/zarch-omitted-base-index.d index b2ff292..cb168a2 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index.d +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.d @@ -18,5 +18,5 @@ Disassembly of section .text: .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 |