RISC-V: Control fence.i and csr instructions by zifencei and zicsr.

bfd/
    * elfxx-riscv.c (riscv_ext_dont_care_version): New function.  Return
    TRUE if we don't care the versions of the extensions.  These extensions
    are added to the subset list for special purposes, with the explicit
    versions or the RISCV_UNKNOWN_VERSION versions.
    (riscv_parse_add_subset): If we do care the versions of the extension,
    and the versions are unknown, then report errors for the non-implicit
    extensions, and return directly for the implicit one.
    (riscv_arch_str1): Do not output i extension after e, and the extensions
    which versions are unknown.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
    and INSN_CLASS_ZIFENCEI.
    * testsuite/gas/riscv/march-imply-i.s: New testcase.
    * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase.  The version
    of i is less than 2.1, and zi* are supported in the chosen spec, so
    enable the fence.i and csr instructions, also output the implicit zi* to
    the arch string.
    * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
    not supported in the spec 2.2.  Enable the related instructions since
    i's version is less than 2.1, but do not output them.
    * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase.  The version
    of i is 2.1, so don't add it's implicit zi*, and disable the related
    instructions.
    * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
    * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
    explicitly, so enable the related instructions.
    * testsuite/gas/riscv/march-imply-i2p0.d: Removed.
    * testsuite/gas/riscv/march-imply-i2p1.d: Removed.
include/
    * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI.
opcodes/
    * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by
    zifencei and zicsr.

9 files changed, 95 insertions, 11 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 987a47c..d657f87 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,24 @@
+2020-12-10  Nelson Chu  <nelson.chu@sifive.com>
+
+	* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
+	and INSN_CLASS_ZIFENCEI.
+	* testsuite/gas/riscv/march-imply-i.s: New testcase.
+	* testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase.  The version
+	of i is less than 2.1, and zi* are supported in the chosen spec, so
+	enable the fence.i and csr instructions, also output the implicit zi* to
+	the arch string.
+	* testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
+	not supported in the spec 2.2.  Enable the related instructions since
+	i's version is less than 2.1, but do not output them.
+	* testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase.  The version
+	of i is 2.1, so don't add it's implicit zi*, and disable the related
+	instructions.
+	* testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
+	* testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
+	explicitly, so enable the related instructions.
+	* testsuite/gas/riscv/march-imply-i2p0.d: Removed.
+	* testsuite/gas/riscv/march-imply-i2p1.d: Removed.
+
 2020-12-08  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/obj-elf.c (SEC_ASSEMBLER_SHF_MASK): New.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5e140fe..dfdbadf 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -237,13 +237,19 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
     case INSN_CLASS_M: return riscv_subset_supports ("m");
     case INSN_CLASS_F: return riscv_subset_supports ("f");
     case INSN_CLASS_D: return riscv_subset_supports ("d");
-    case INSN_CLASS_D_AND_C:
-      return riscv_subset_supports ("d") && riscv_subset_supports ("c");
+    case INSN_CLASS_Q: return riscv_subset_supports ("q");
 
     case INSN_CLASS_F_AND_C:
-      return riscv_subset_supports ("f") && riscv_subset_supports ("c");
+      return (riscv_subset_supports ("f")
+	      && riscv_subset_supports ("c"));
+    case INSN_CLASS_D_AND_C:
+      return (riscv_subset_supports ("d")
+	      && riscv_subset_supports ("c"));
 
-    case INSN_CLASS_Q: return riscv_subset_supports ("q");
+    case INSN_CLASS_ZICSR:
+      return riscv_subset_supports ("zicsr");
+    case INSN_CLASS_ZIFENCEI:
+      return riscv_subset_supports ("zifencei");
 
     default:
       as_fatal ("Unreachable");
diff --git a/gas/testsuite/gas/riscv/march-imply-i.s b/gas/testsuite/gas/riscv/march-imply-i.s
new file mode 100644
index 0000000..b65c3c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-i.s
@@ -0,0 +1,24 @@
+target:
+	# zicsr
+	csrr	t0, ustatus
+	csrwi	ustatus, 0x0
+	csrsi	ustatus, 0x0
+	csrci	ustatus, 0x0
+	csrw	ustatus, t0
+	csrw	ustatus, 0x0
+	csrs	ustatus, t0
+	csrs	ustatus, 0x0
+	csrc	ustatus, t0
+	csrc	ustatus, 0x0
+	csrrwi	t0, ustatus, 0x0
+	csrrsi	t0, ustatus, 0x0
+	csrrci	t0, ustatus, 0x0
+	csrrw	t0, ustatus, t0
+	csrrw	t0, ustatus, 0x0
+	csrrs	t0, ustatus, t0
+	csrrs	t0, ustatus, 0x0
+	csrrc	t0, ustatus, t0
+	csrrc	t0, ustatus, 0x0
+
+	# zifencei
+	fence.i
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0.d b/gas/testsuite/gas/riscv/march-imply-i2p0-01.d
index 17fcc7a..6d86034 100644
--- a/gas/testsuite/gas/riscv/march-imply-i2p0.d
+++ b/gas/testsuite/gas/riscv/march-imply-i2p0-01.d
@@ -1,6 +1,7 @@
 #as: -march=rv32i2p0 -march-attr -misa-spec=20191213
 #readelf: -A
-#source: empty.s
+#source: march-imply-i.s
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_zicsr2p0_zifencei2p0"
+#...
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0-02.d b/gas/testsuite/gas/riscv/march-imply-i2p0-02.d
new file mode 100644
index 0000000..7686296
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-i2p0-02.d
@@ -0,0 +1,7 @@
+#as: -march=rv32i -march-attr -misa-spec=2.2
+#readelf: -A
+#source: march-imply-i.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p0"
+#...
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-01.d b/gas/testsuite/gas/riscv/march-imply-i2p1-01.d
new file mode 100644
index 0000000..fcf22ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-i2p1-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i -march-attr -misa-spec=20191213
+#source: march-imply-i.s
+#error_output: march-imply-i2p1-01.l
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-01.l b/gas/testsuite/gas/riscv/march-imply-i2p1-01.l
new file mode 100644
index 0000000..b54d4ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-i2p1-01.l
@@ -0,0 +1,21 @@
+.*Assembler messages:
+.*Error: unrecognized opcode `csrr t0,ustatus'
+.*Error: unrecognized opcode `csrwi ustatus,0x0'
+.*Error: unrecognized opcode `csrsi ustatus,0x0'
+.*Error: unrecognized opcode `csrci ustatus,0x0'
+.*Error: unrecognized opcode `csrw ustatus,t0'
+.*Error: unrecognized opcode `csrw ustatus,0x0'
+.*Error: unrecognized opcode `csrs ustatus,t0'
+.*Error: unrecognized opcode `csrs ustatus,0x0'
+.*Error: unrecognized opcode `csrc ustatus,t0'
+.*Error: unrecognized opcode `csrc ustatus,0x0'
+.*Error: unrecognized opcode `csrrwi t0,ustatus,0x0'
+.*Error: unrecognized opcode `csrrsi t0,ustatus,0x0'
+.*Error: unrecognized opcode `csrrci t0,ustatus,0x0'
+.*Error: unrecognized opcode `csrrw t0,ustatus,t0'
+.*Error: unrecognized opcode `csrrw t0,ustatus,0x0'
+.*Error: unrecognized opcode `csrrs t0,ustatus,t0'
+.*Error: unrecognized opcode `csrrs t0,ustatus,0x0'
+.*Error: unrecognized opcode `csrrc t0,ustatus,t0'
+.*Error: unrecognized opcode `csrrc t0,ustatus,0x0'
+.*Error: unrecognized opcode `fence.i'
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-02.d b/gas/testsuite/gas/riscv/march-imply-i2p1-02.d
new file mode 100644
index 0000000..b8065b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-i2p1-02.d
@@ -0,0 +1,7 @@
+#as: -march=rv32i_zicsr_zifencei -march-attr -misa-spec=20191213
+#readelf: -A
+#source: march-imply-i.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zifencei2p0"
+#...
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1.d b/gas/testsuite/gas/riscv/march-imply-i2p1.d
deleted file mode 100644
index 0e9a464..0000000
--- a/gas/testsuite/gas/riscv/march-imply-i2p1.d
+++ /dev/null
@@ -1,6 +0,0 @@
-#as: -march=rv32i -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
-  Tag_RISCV_arch: "rv32i2p1"