Add system register and embedded debug register support.

Add two more as test files for user special and system register.
Fix typo.

2013-12-17  Kuan-Lin Chen  <kuanlinchentw@gmail.com>

	* gas/nds32/nds32.exp: Add system and user special register tests.
	* gas/nds32/sys-reg.s: New test.
	* gas/nds32/sys-reg.d: Likewise.
	* gas/nds32/usr-spe-reg.s: Likewise.
	* gas/nds32/usr-spe-reg.d: Likewise.
	* gas/nds32/alu-2.d: Delete the new blank line at EOF.
	* gas/nds32/br-1.d: Likewise.
	* gas/nds32/br-2.d: Likewise.
	* gas/nds32/ji-jr.d: Likewise.
	* gas/nds32/lsi.d: Likewise.
	* nds32-dis.c (sr_map): Add system register table for disassembling.
	(usr_map): Fix typo.
	* nds32-asm.c (keyword_sr): Add embedded debug registers.

11 files changed, 297 insertions, 5 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 194a47a..20f13f4 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2013-12-17  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+	* gas/nds32/nds32.exp: Add system and user special register tests.
+	* gas/nds32/sys-reg.s: New test.
+	* gas/nds32/sys-reg.d: Likewise.
+	* gas/nds32/usr-spe-reg.s: Likewise.
+	* gas/nds32/usr-spe-reg.d: Likewise.
+	* gas/nds32/alu-2.d: Delete the new blank line at EOF.
+	* gas/nds32/br-1.d: Likewise.
+	* gas/nds32/br-2.d: Likewise.
+	* gas/nds32/ji-jr.d: Likewise.
+	* gas/nds32/lsi.d: Likewise.
+
 2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 
 	* gas/i386/disassem.s: New.
diff --git a/gas/testsuite/gas/nds32/alu-2.d b/gas/testsuite/gas/nds32/alu-2.d
index 1b32f0b..11c2eb1 100644
--- a/gas/testsuite/gas/nds32/alu-2.d
+++ b/gas/testsuite/gas/nds32/alu-2.d
@@ -39,4 +39,3 @@ Disassembly of section .text:
 0+0074 <[^>]*> msubr32	\$r0, \$r1, \$r2
 0+0078 <[^>]*> mulr64	\$r0, \$r1, \$r2
 0+007c <[^>]*> mulsr64	\$r0, \$r1, \$r2
-
diff --git a/gas/testsuite/gas/nds32/br-1.d b/gas/testsuite/gas/nds32/br-1.d
index e27f96c..b4842d8 100644
--- a/gas/testsuite/gas/nds32/br-1.d
+++ b/gas/testsuite/gas/nds32/br-1.d
@@ -12,4 +12,3 @@ Disassembly of section .text:
 			0: R_NDS32_RELAX_ENTRY	.text
 0+0004 <[^>]*> bne	\$r0, \$r1, 00000004 <foo\+0x4>
 			4: R_NDS32_15_PCREL_RELA	.text
-
diff --git a/gas/testsuite/gas/nds32/br-2.d b/gas/testsuite/gas/nds32/br-2.d
index 0edc375..24ce157 100644
--- a/gas/testsuite/gas/nds32/br-2.d
+++ b/gas/testsuite/gas/nds32/br-2.d
@@ -22,4 +22,3 @@ Disassembly of section .text:
 			14: R_NDS32_17_PCREL_RELA	.text
 0+0018 <[^>]*> bltzal	\$r0, 00000018 <foo\+0x18>
 			18: R_NDS32_17_PCREL_RELA	.text
-
diff --git a/gas/testsuite/gas/nds32/ji-jr.d b/gas/testsuite/gas/nds32/ji-jr.d
index 31969e1..ac79218 100644
--- a/gas/testsuite/gas/nds32/ji-jr.d
+++ b/gas/testsuite/gas/nds32/ji-jr.d
@@ -15,4 +15,3 @@ Disassembly of section .text:
 0+0006 <[^>]*> jr	\$r0
 0+000a <[^>]*> jral	\$lp, \$r0
 0+000e <[^>]*> ret	\$lp
-
diff --git a/gas/testsuite/gas/nds32/lsi.d b/gas/testsuite/gas/nds32/lsi.d
index 9fe5371..9f9839e 100644
--- a/gas/testsuite/gas/nds32/lsi.d
+++ b/gas/testsuite/gas/nds32/lsi.d
@@ -23,4 +23,3 @@ Disassembly of section .text:
 0+0034 <[^>]*> swi.bi	\$r0, \[\$r1\], #4
 0+0038 <[^>]*> shi.bi	\$r0, \[\$r1\], #2
 0+003c <[^>]*> sbi.bi	\$r0, \[\$r1\], #1
-
diff --git a/gas/testsuite/gas/nds32/nds32.exp b/gas/testsuite/gas/nds32/nds32.exp
index f547697..9686e6a 100644
--- a/gas/testsuite/gas/nds32/nds32.exp
+++ b/gas/testsuite/gas/nds32/nds32.exp
@@ -27,4 +27,6 @@ if { [istarget nds32*] } {
     run_dump_test "to-16bit-v1"
     run_dump_test "to-16bit-v2"
     run_dump_test "to-16bit-v3"
+    run_dump_test "usr-spe-reg"
+    run_dump_test "sys-reg"
 }
diff --git a/gas/testsuite/gas/nds32/sys-reg.d b/gas/testsuite/gas/nds32/sys-reg.d
new file mode 100644
index 0000000..0a3b634
--- /dev/null
+++ b/gas/testsuite/gas/nds32/sys-reg.d
@@ -0,0 +1,118 @@
+#objdump: -d --prefix-addresses
+#name: nds32 sys-reg instructions
+#as:
+
+# Test system register instructions
+
+.*:     file format .*
+
+
+Disassembly of section .text:
+0+0000 <[^>]*> mfsr	\$r0, \$CPU_VER
+0+0004 <[^>]*> mfsr	\$r0, \$CORE_ID
+0+0008 <[^>]*> mfsr	\$r0, \$ICM_CFG
+0+000c <[^>]*> mfsr	\$r0, \$DCM_CFG
+0+0010 <[^>]*> mfsr	\$r0, \$MMU_CFG
+0+0014 <[^>]*> mfsr	\$r0, \$MSC_CFG
+0+0018 <[^>]*> mfsr	\$r0, \$PSW
+0+001c <[^>]*> mfsr	\$r0, \$IPSW
+0+0020 <[^>]*> mfsr	\$r0, \$P_IPSW
+0+0024 <[^>]*> mfsr	\$r0, \$IVB
+0+0028 <[^>]*> mfsr	\$r0, \$INT_CTRL
+0+002c <[^>]*> mfsr	\$r0, \$EVA
+0+0030 <[^>]*> mfsr	\$r0, \$P_EVA
+0+0034 <[^>]*> mfsr	\$r0, \$ITYPE
+0+0038 <[^>]*> mfsr	\$r0, \$P_ITYPE
+0+003c <[^>]*> mfsr	\$r0, \$MERR
+0+0040 <[^>]*> mfsr	\$r0, \$IPC
+0+0044 <[^>]*> mfsr	\$r0, \$P_IPC
+0+0048 <[^>]*> mfsr	\$r0, \$OIPC
+0+004c <[^>]*> mfsr	\$r0, \$P_P0
+0+0050 <[^>]*> mfsr	\$r0, \$P_P1
+0+0054 <[^>]*> mfsr	\$r0, \$INT_MASK
+0+0058 <[^>]*> mfsr	\$r0, \$INT_MASK2
+0+005c <[^>]*> mfsr	\$r0, \$INT_PEND
+0+0060 <[^>]*> mfsr	\$r0, \$INT_PEND2
+0+0064 <[^>]*> mfsr	\$r0, \$INT_TRIGGER
+0+0068 <[^>]*> mfsr	\$r0, \$SP_USR
+0+006c <[^>]*> mfsr	\$r0, \$SP_PRIV
+0+0070 <[^>]*> mfsr	\$r0, \$INT_PRI
+0+0074 <[^>]*> mfsr	\$r0, \$INT_PRI2
+0+0078 <[^>]*> mfsr	\$r0, \$MMU_CTL
+0+007c <[^>]*> mfsr	\$r0, \$L1_PPTB
+0+0080 <[^>]*> mfsr	\$r0, \$TLB_VPN
+0+0084 <[^>]*> mfsr	\$r0, \$TLB_DATA
+0+0088 <[^>]*> mfsr	\$r0, \$TLB_MISC
+0+008c <[^>]*> mfsr	\$r0, \$VLPT_IDX
+0+0090 <[^>]*> mfsr	\$r0, \$ILMB
+0+0094 <[^>]*> mfsr	\$r0, \$DLMB
+0+0098 <[^>]*> mfsr	\$r0, \$CACHE_CTL
+0+009c <[^>]*> mfsr	\$r0, \$HSMP_SADDR
+0+00a0 <[^>]*> mfsr	\$r0, \$HSMP_EADDR
+0+00a4 <[^>]*> mfsr	\$r0, \$SDZ_CTL
+0+00a8 <[^>]*> mfsr	\$r0, \$MISC_CTL
+0+00ac <[^>]*> mfsr	\$r0, \$BPC0
+0+00b0 <[^>]*> mfsr	\$r0, \$BPC1
+0+00b4 <[^>]*> mfsr	\$r0, \$BPC2
+0+00b8 <[^>]*> mfsr	\$r0, \$BPC3
+0+00bc <[^>]*> mfsr	\$r0, \$BPC4
+0+00c0 <[^>]*> mfsr	\$r0, \$BPC5
+0+00c4 <[^>]*> mfsr	\$r0, \$BPC6
+0+00c8 <[^>]*> mfsr	\$r0, \$BPC7
+0+00cc <[^>]*> mfsr	\$r0, \$BPA0
+0+00d0 <[^>]*> mfsr	\$r0, \$BPA1
+0+00d4 <[^>]*> mfsr	\$r0, \$BPA2
+0+00d8 <[^>]*> mfsr	\$r0, \$BPA3
+0+00dc <[^>]*> mfsr	\$r0, \$BPA4
+0+00e0 <[^>]*> mfsr	\$r0, \$BPA5
+0+00e4 <[^>]*> mfsr	\$r0, \$BPA6
+0+00e8 <[^>]*> mfsr	\$r0, \$BPA7
+0+00ec <[^>]*> mfsr	\$r0, \$BPAM0
+0+00f0 <[^>]*> mfsr	\$r0, \$BPAM1
+0+00f4 <[^>]*> mfsr	\$r0, \$BPAM2
+0+00f8 <[^>]*> mfsr	\$r0, \$BPAM3
+0+00fc <[^>]*> mfsr	\$r0, \$BPAM4
+0+0100 <[^>]*> mfsr	\$r0, \$BPAM5
+0+0104 <[^>]*> mfsr	\$r0, \$BPAM6
+0+0108 <[^>]*> mfsr	\$r0, \$BPAM7
+0+010c <[^>]*> mfsr	\$r0, \$BPV0
+0+0110 <[^>]*> mfsr	\$r0, \$BPV1
+0+0114 <[^>]*> mfsr	\$r0, \$BPV2
+0+0118 <[^>]*> mfsr	\$r0, \$BPV3
+0+011c <[^>]*> mfsr	\$r0, \$BPV4
+0+0120 <[^>]*> mfsr	\$r0, \$BPV5
+0+0124 <[^>]*> mfsr	\$r0, \$BPV6
+0+0128 <[^>]*> mfsr	\$r0, \$BPV7
+0+012c <[^>]*> mfsr	\$r0, \$BPCID0
+0+0130 <[^>]*> mfsr	\$r0, \$BPCID1
+0+0134 <[^>]*> mfsr	\$r0, \$BPCID2
+0+0138 <[^>]*> mfsr	\$r0, \$BPCID3
+0+013c <[^>]*> mfsr	\$r0, \$BPCID4
+0+0140 <[^>]*> mfsr	\$r0, \$BPCID5
+0+0144 <[^>]*> mfsr	\$r0, \$BPCID6
+0+0148 <[^>]*> mfsr	\$r0, \$BPCID7
+0+014c <[^>]*> mfsr	\$r0, \$EDM_CFG
+0+0150 <[^>]*> mfsr	\$r0, \$EDMSW
+0+0154 <[^>]*> mfsr	\$r0, \$EDM_CTL
+0+0158 <[^>]*> mfsr	\$r0, \$EDM_DTR
+0+015c <[^>]*> mfsr	\$r0, \$BPMTC
+0+0160 <[^>]*> mfsr	\$r0, \$DIMBR
+0+0164 <[^>]*> mfsr	\$r0, \$TECR0
+0+0168 <[^>]*> mfsr	\$r0, \$TECR1
+0+016c <[^>]*> mfsr	\$r0, \$PFMC0
+0+0170 <[^>]*> mfsr	\$r0, \$PFMC1
+0+0174 <[^>]*> mfsr	\$r0, \$PFMC2
+0+0178 <[^>]*> mfsr	\$r0, \$PFM_CTL
+0+017c <[^>]*> mfsr	\$r0, \$PRUSR_ACC_CTL
+0+0180 <[^>]*> mfsr	\$r0, \$FUCOP_CTL
+0+0184 <[^>]*> mfsr	\$r0, \$DMA_CFG
+0+0188 <[^>]*> mfsr	\$r0, \$DMA_GCSW
+0+018c <[^>]*> mfsr	\$r0, \$DMA_CHNSEL
+0+0190 <[^>]*> mfsr	\$r0, \$DMA_ACT
+0+0194 <[^>]*> mfsr	\$r0, \$DMA_SETUP
+0+0198 <[^>]*> mfsr	\$r0, \$DMA_ISADDR
+0+019c <[^>]*> mfsr	\$r0, \$DMA_ESADDR
+0+01a0 <[^>]*> mfsr	\$r0, \$DMA_TCNT
+0+01a4 <[^>]*> mfsr	\$r0, \$DMA_STATUS
+0+01a8 <[^>]*> mfsr	\$r0, \$DMA_2DSET
+0+01ac <[^>]*> mfsr	\$r0, \$DMA_2DSCTL
diff --git a/gas/testsuite/gas/nds32/sys-reg.s b/gas/testsuite/gas/nds32/sys-reg.s
new file mode 100644
index 0000000..77fa15e
--- /dev/null
+++ b/gas/testsuite/gas/nds32/sys-reg.s
@@ -0,0 +1,114 @@
+foo:
+	mfsr $r0 ,$CPU_VER
+	mfsr $r0 ,$CORE_ID
+	mfsr $r0 ,$ICM_CFG
+	mfsr $r0 ,$DCM_CFG
+	mfsr $r0 ,$MMU_CFG
+	mfsr $r0 ,$MSC_CFG
+
+	mfsr $r0 ,$PSW
+	mfsr $r0 ,$IPSW
+	mfsr $r0 ,$P_IPSW
+	mfsr $r0 ,$IVB
+	mfsr $r0 ,$INT_CTRL
+	mfsr $r0 ,$EVA
+	mfsr $r0 ,$P_EVA
+	mfsr $r0 ,$ITYPE
+	mfsr $r0 ,$P_ITYPE
+	mfsr $r0 ,$MERR
+	mfsr $r0 ,$IPC
+	mfsr $r0 ,$P_IPC
+	mfsr $r0 ,$OIPC
+	mfsr $r0 ,$P_P0
+	mfsr $r0 ,$P_P1
+	mfsr $r0 ,$INT_MASK
+	mfsr $r0 ,$INT_MASK2
+	mfsr $r0 ,$INT_PEND
+	mfsr $r0 ,$INT_PEND2
+	mfsr $r0 ,$INT_TRIGGER
+	mfsr $r0 ,$SP_USR
+	mfsr $r0 ,$SP_PRIV
+	mfsr $r0 ,$INT_PRI
+	mfsr $r0 ,$INT_PRI2
+
+	mfsr $r0 ,$MMU_CTL
+	mfsr $r0 ,$L1_PPTB
+	mfsr $r0 ,$TLB_VPN
+	mfsr $r0 ,$TLB_DATA
+	mfsr $r0 ,$TLB_MISC
+	mfsr $r0 ,$VLPT_IDX
+	mfsr $r0 ,$ILMB
+	mfsr $r0 ,$DLMB
+	mfsr $r0 ,$CACHE_CTL
+	mfsr $r0 ,$HSMP_SADDR
+	mfsr $r0 ,$HSMP_EADDR
+	mfsr $r0 ,$SDZ_CTL
+	mfsr $r0 ,$MISC_CTL
+
+	mfsr $r0 ,$BPC0
+	mfsr $r0 ,$BPC1
+	mfsr $r0 ,$BPC2
+	mfsr $r0 ,$BPC3
+	mfsr $r0 ,$BPC4
+	mfsr $r0 ,$BPC5
+	mfsr $r0 ,$BPC6
+	mfsr $r0 ,$BPC7
+	mfsr $r0 ,$BPA0
+	mfsr $r0 ,$BPA1
+	mfsr $r0 ,$BPA2
+	mfsr $r0 ,$BPA3
+	mfsr $r0 ,$BPA4
+	mfsr $r0 ,$BPA5
+	mfsr $r0 ,$BPA6
+	mfsr $r0 ,$BPA7
+	mfsr $r0 ,$BPAM0
+	mfsr $r0 ,$BPAM1
+	mfsr $r0 ,$BPAM2
+	mfsr $r0 ,$BPAM3
+	mfsr $r0 ,$BPAM4
+	mfsr $r0 ,$BPAM5
+	mfsr $r0 ,$BPAM6
+	mfsr $r0 ,$BPAM7
+	mfsr $r0 ,$BPV0
+	mfsr $r0 ,$BPV1
+	mfsr $r0 ,$BPV2
+	mfsr $r0 ,$BPV3
+	mfsr $r0 ,$BPV4
+	mfsr $r0 ,$BPV5
+	mfsr $r0 ,$BPV6
+	mfsr $r0 ,$BPV7
+	mfsr $r0 ,$BPCID0
+	mfsr $r0 ,$BPCID1
+	mfsr $r0 ,$BPCID2
+	mfsr $r0 ,$BPCID3
+	mfsr $r0 ,$BPCID4
+	mfsr $r0 ,$BPCID5
+	mfsr $r0 ,$BPCID6
+	mfsr $r0 ,$BPCID7
+	mfsr $r0 ,$EDM_CFG
+	mfsr $r0 ,$EDMSW
+	mfsr $r0 ,$EDM_CTL
+	mfsr $r0 ,$EDM_DTR
+	mfsr $r0 ,$BPMTC
+	mfsr $r0 ,$DIMBR
+	mfsr $r0 ,$TECR0
+	mfsr $r0 ,$TECR1
+
+	mfsr $r0 ,$PFMC0
+	mfsr $r0 ,$PFMC1
+	mfsr $r0 ,$PFMC2
+	mfsr $r0 ,$PFM_CTL
+	mfsr $r0 ,$PRUSR_ACC_CTL
+	mfsr $r0 ,$FUCOP_CTL
+
+	mfsr $r0 ,$DMA_CFG
+	mfsr $r0 ,$DMA_GCSW
+	mfsr $r0 ,$DMA_CHNSEL
+	mfsr $r0 ,$DMA_ACT
+	mfsr $r0 ,$DMA_SETUP
+	mfsr $r0 ,$DMA_ISADDR
+	mfsr $r0 ,$DMA_ESADDR
+	mfsr $r0 ,$DMA_TCNT
+	mfsr $r0 ,$DMA_STATUS
+	mfsr $r0 ,$DMA_2DSET
+	mfsr $r0 ,$DMA_2DSCTL
diff --git a/gas/testsuite/gas/nds32/usr-spe-reg.d b/gas/testsuite/gas/nds32/usr-spe-reg.d
new file mode 100644
index 0000000..6ff6d96
--- /dev/null
+++ b/gas/testsuite/gas/nds32/usr-spe-reg.d
@@ -0,0 +1,29 @@
+#objdump: -d --prefix-addresses
+#name: nds32 usr-spe-reg instructions
+#as:
+
+# Test user specail register instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> mfusr	\$r0, \$d0.lo
+0+0004 <[^>]*> mfusr	\$r0, \$d0.hi
+0+0008 <[^>]*> mfusr	\$r0, \$d1.lo
+0+000c <[^>]*> mfusr	\$r0, \$d1.hi
+0+0010 <[^>]*> mfusr	\$r0, \$pc
+0+0014 <[^>]*> mfusr	\$r0, \$DMA_CFG
+0+0018 <[^>]*> mfusr	\$r0, \$DMA_GCSW
+0+001c <[^>]*> mfusr	\$r0, \$DMA_CHNSEL
+0+0020 <[^>]*> mfusr	\$r0, \$DMA_ACT
+0+0024 <[^>]*> mfusr	\$r0, \$DMA_SETUP
+0+0028 <[^>]*> mfusr	\$r0, \$DMA_ISADDR
+0+002c <[^>]*> mfusr	\$r0, \$DMA_ESADDR
+0+0030 <[^>]*> mfusr	\$r0, \$DMA_TCNT
+0+0034 <[^>]*> mfusr	\$r0, \$DMA_STATUS
+0+0038 <[^>]*> mfusr	\$r0, \$DMA_2DSET
+0+003c <[^>]*> mfusr	\$r0, \$DMA_2DSCTL
+0+0040 <[^>]*> mfusr	\$r0, \$PFMC0
+0+0044 <[^>]*> mfusr	\$r0, \$PFMC1
+0+0048 <[^>]*> mfusr	\$r0, \$PFMC2
+0+004c <[^>]*> mfusr	\$r0, \$PFM_CTL
diff --git a/gas/testsuite/gas/nds32/usr-spe-reg.s b/gas/testsuite/gas/nds32/usr-spe-reg.s
new file mode 100644
index 0000000..d43cf1e
--- /dev/null
+++ b/gas/testsuite/gas/nds32/usr-spe-reg.s
@@ -0,0 +1,21 @@
+foo:
+	mfusr $r0, d0.lo
+	mfusr $r0, d0.hi
+	mfusr $r0, d1.lo
+	mfusr $r0, d1.hi
+	mfusr $r0, $pc
+	mfusr $r0, $DMA_CFG
+	mfusr $r0, $DMA_GCSW
+	mfusr $r0, $DMA_CHNSEL
+	mfusr $r0, $DMA_ACT
+	mfusr $r0, $DMA_SETUP
+	mfusr $r0, $DMA_ISADDR
+	mfusr $r0, $DMA_ESADDR
+	mfusr $r0, $DMA_TCNT
+	mfusr $r0, $DMA_STATUS
+	mfusr $r0, $DMA_2DSET
+	mfusr $r0, $DMA_2DSCTL
+	mfusr $r0, $PFMC0
+	mfusr $r0, $PFMC1
+	mfusr $r0, $PFMC2
+	mfusr $r0, $PFM_CTL