opcodes: blackfin: fix decoding of LSHIFT insns

The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT.  So be specific when disassembling.

As fall out of this change, we need to update some assembler tests.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

6 files changed, 17 insertions, 12 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0ebbc5a..031daa1 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2010-09-22  Mike Frysinger  <vapier@gentoo.org>
+
+	* gas/bfin/parallel2.d, gas/bfin/parallel3.d, gas/bfin/shift.d,
+	gas/bfin/vector.2, gas/bfin/vector2.d: Change SHIFT to LSHIFT.
+
 2010-09-20  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 	* gas/arm/attr-cpu-directive.d: Update test for change in canonical
diff --git a/gas/testsuite/gas/bfin/parallel2.d b/gas/testsuite/gas/bfin/parallel2.d
index ce21097..3a07b86 100644
--- a/gas/testsuite/gas/bfin/parallel2.d
+++ b/gas/testsuite/gas/bfin/parallel2.d
@@ -113,7 +113,7 @@ Disassembly of section .text:
  1a4:	d5 a6 00 00 
  1a8:	00 ce 16 8e 	R7.L = LSHIFT R6.L BY R2.L \|\| R5 = W\[P2 \+ 0x14\] \(Z\) \|\| NOP;
  1ac:	95 a6 00 00 
- 1b0:	02 ce 1c 8a 	R5 = SHIFT R4 BY R3.L \|\| R4 = W\[P2 \+ 0x12\] \(Z\) \|\| NOP;
+ 1b0:	02 ce 1c 8a 	R5 = LSHIFT R4 BY R3.L \|\| R4 = W\[P2 \+ 0x12\] \(Z\) \|\| NOP;
  1b4:	54 a6 00 00 
  1b8:	03 ce 30 40 	A0 = LSHIFT A0 BY R6.L \|\| R5 = W\[P2 \+ 0x10\] \(Z\) \|\| NOP;
  1bc:	15 a6 00 00 
diff --git a/gas/testsuite/gas/bfin/parallel3.d b/gas/testsuite/gas/bfin/parallel3.d
index 4fd9ed7..0568f9b 100644
--- a/gas/testsuite/gas/bfin/parallel3.d
+++ b/gas/testsuite/gas/bfin/parallel3.d
@@ -67,7 +67,7 @@ Disassembly of section .text:
   ec:	20 bd 00 00 
   f0:	81 ce 11 80 	R0 = R1 << 0x2 \(V\) \|\| \[P4 \+ 0xc\] = P0 \|\| NOP;
   f4:	e0 bc 00 00 
-  f8:	01 ce 11 88 	R4 = SHIFT R1 BY R2.L \(V\) \|\| \[P5\] = P0 \|\| NOP;
+  f8:	01 ce 11 88 	R4 = LSHIFT R1 BY R2.L \(V\) \|\| \[P5\] = P0 \|\| NOP;
   fc:	68 93 00 00 
  100:	06 cc 01 0c 	R6 = MAX \(R0, R1\) \(V\) \|\| \[P5\+\+\] = P0 \|\| NOP;
  104:	68 92 00 00 
diff --git a/gas/testsuite/gas/bfin/shift.d b/gas/testsuite/gas/bfin/shift.d
index 2b85101..eb0bfa8 100644
--- a/gas/testsuite/gas/bfin/shift.d
+++ b/gas/testsuite/gas/bfin/shift.d
@@ -56,7 +56,7 @@ Disassembly of section .text:
   84:	00 c6 02 b2 	R1.H = LSHIFT R2.H BY R0.L;
   88:	00 c6 08 90 	R0.L = LSHIFT R0.H BY R1.L;
   8c:	00 c6 16 8e 	R7.L = LSHIFT R6.L BY R2.L;
-  90:	02 c6 1c 8a 	R5 = SHIFT R4 BY R3.L;
+  90:	02 c6 1c 8a 	R5 = LSHIFT R4 BY R3.L;
   94:	03 c6 30 40 	A0 = LSHIFT A0 BY R6.L;
   98:	03 c6 28 50 	A1 = LSHIFT A1 BY R5.L;
 
diff --git a/gas/testsuite/gas/bfin/vector.d b/gas/testsuite/gas/bfin/vector.d
index 169c9da..26cdc17 100644
--- a/gas/testsuite/gas/bfin/vector.d
+++ b/gas/testsuite/gas/bfin/vector.d
@@ -46,7 +46,7 @@ Disassembly of section .text:
 00000074 <vector_lshift>:
   74:	81 c6 8a 8b 	R5 = R2 >> 0xf \(V\);
   78:	81 c6 11 80 	R0 = R1 << 0x2 \(V\);
-  7c:	01 c6 11 88 	R4 = SHIFT R1 BY R2.L \(V\);
+  7c:	01 c6 11 88 	R4 = LSHIFT R1 BY R2.L \(V\);
 
 00000080 <vector_max>:
   80:	06 c4 01 0c 	R6 = MAX \(R0, R1\) \(V\);
diff --git a/gas/testsuite/gas/bfin/vector2.d b/gas/testsuite/gas/bfin/vector2.d
index d4746ca..a6b1935 100644
--- a/gas/testsuite/gas/bfin/vector2.d
+++ b/gas/testsuite/gas/bfin/vector2.d
@@ -386,14 +386,14 @@ Disassembly of section .text:
  5e8:	81 c6 2a 86 	R3 = R2 << 0x5 \(V\);
  5ec:	81 c6 2c 8a 	R5 = R4 << 0x5 \(V\);
  5f0:	81 c6 2e 8e 	R7 = R6 << 0x5 \(V\);
- 5f4:	01 c6 11 80 	R0 = SHIFT R1 BY R2.L \(V\);
- 5f8:	01 c6 2c 86 	R3 = SHIFT R4 BY R5.L \(V\);
- 5fc:	01 c6 07 8c 	R6 = SHIFT R7 BY R0.L \(V\);
- 600:	01 c6 1a 82 	R1 = SHIFT R2 BY R3.L \(V\);
- 604:	01 c6 35 88 	R4 = SHIFT R5 BY R6.L \(V\);
- 608:	01 c6 08 8e 	R7 = SHIFT R0 BY R1.L \(V\);
- 60c:	01 c6 23 84 	R2 = SHIFT R3 BY R4.L \(V\);
- 610:	01 c6 3e 8a 	R5 = SHIFT R6 BY R7.L \(V\);
+ 5f4:	01 c6 11 80 	R0 = LSHIFT R1 BY R2.L \(V\);
+ 5f8:	01 c6 2c 86 	R3 = LSHIFT R4 BY R5.L \(V\);
+ 5fc:	01 c6 07 8c 	R6 = LSHIFT R7 BY R0.L \(V\);
+ 600:	01 c6 1a 82 	R1 = LSHIFT R2 BY R3.L \(V\);
+ 604:	01 c6 35 88 	R4 = LSHIFT R5 BY R6.L \(V\);
+ 608:	01 c6 08 8e 	R7 = LSHIFT R0 BY R1.L \(V\);
+ 60c:	01 c6 23 84 	R2 = LSHIFT R3 BY R4.L \(V\);
+ 610:	01 c6 3e 8a 	R5 = LSHIFT R6 BY R7.L \(V\);
  614:	06 c4 08 0e 	R7 = MAX \(R1, R0\) \(V\);
  618:	06 c4 0a 00 	R0 = MAX \(R1, R2\) \(V\);
  61c:	06 c4 25 06 	R3 = MAX \(R4, R5\) \(V\);