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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:16:44 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:16:44 +0100 |
| commit | 5437a02abc9fe106054965828787e8f232692935 (patch) | |
| tree | 4723e3eddeef436e20d15d44c109b0f1529db3ba /gas | |
| parent | 567dfba2bed4bce68a13b0c8963dec9605dea6c8 (diff) | |
| download | gdb-5437a02abc9fe106054965828787e8f232692935.zip gdb-5437a02abc9fe106054965828787e8f232692935.tar.gz gdb-5437a02abc9fe106054965828787e8f232692935.tar.bz2 | |
Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/f64mm.d | 24 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/f64mm.s | 24 |
3 files changed, 29 insertions, 24 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 4a8bb54..41959ae 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2020-01-03 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}. + * testsuite/gas/aarch64/f64mm.d: Adjust expectations. + +2020-01-03 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for by-element usdot. Add 64-bit form tests for by-element sudot. * testsuite/gas/aarch64/i8mm.d: Adjust expectations. diff --git a/gas/testsuite/gas/aarch64/f64mm.d b/gas/testsuite/gas/aarch64/f64mm.d index e9ec694..35c0853 100644 --- a/gas/testsuite/gas/aarch64/f64mm.d +++ b/gas/testsuite/gas/aarch64/f64mm.d @@ -10,20 +10,20 @@ Disassembly of section \.text: *[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d *[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\] *[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\] - *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\] - *[0-9a-f]+: a4a003e0 ld1roh {z0\.h}, p0/z, \[sp, x0\] - *[0-9a-f]+: a53b17f1 ld1row {z17\.s}, p5/z, \[sp, x27\] - *[0-9a-f]+: a52003e0 ld1row {z0\.s}, p0/z, \[sp, x0\] - *[0-9a-f]+: a5bb17f1 ld1rod {z17\.d}, p5/z, \[sp, x27\] - *[0-9a-f]+: a5a003e0 ld1rod {z0\.d}, p0/z, \[sp, x0\] + *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27, lsl #1\] + *[0-9a-f]+: a4a003e0 ld1roh {z0\.h}, p0/z, \[sp, x0, lsl #1\] + *[0-9a-f]+: a53b17f1 ld1row {z17\.s}, p5/z, \[sp, x27, lsl #2\] + *[0-9a-f]+: a52003e0 ld1row {z0\.s}, p0/z, \[sp, x0, lsl #2\] + *[0-9a-f]+: a5bb17f1 ld1rod {z17\.d}, p5/z, \[sp, x27, lsl #3\] + *[0-9a-f]+: a5a003e0 ld1rod {z0\.d}, p0/z, \[sp, x0, lsl #3\] *[0-9a-f]+: a43b1411 ld1rob {z17\.b}, p5/z, \[x0, x27\] *[0-9a-f]+: a4200000 ld1rob {z0\.b}, p0/z, \[x0, x0\] - *[0-9a-f]+: a4bb1411 ld1roh {z17\.h}, p5/z, \[x0, x27\] - *[0-9a-f]+: a4a00000 ld1roh {z0\.h}, p0/z, \[x0, x0\] - *[0-9a-f]+: a53b1411 ld1row {z17\.s}, p5/z, \[x0, x27\] - *[0-9a-f]+: a5200000 ld1row {z0\.s}, p0/z, \[x0, x0\] - *[0-9a-f]+: a5bb1411 ld1rod {z17\.d}, p5/z, \[x0, x27\] - *[0-9a-f]+: a5a00000 ld1rod {z0\.d}, p0/z, \[x0, x0\] + *[0-9a-f]+: a4bb1411 ld1roh {z17\.h}, p5/z, \[x0, x27, lsl #1\] + *[0-9a-f]+: a4a00000 ld1roh {z0\.h}, p0/z, \[x0, x0, lsl #1\] + *[0-9a-f]+: a53b1411 ld1row {z17\.s}, p5/z, \[x0, x27, lsl #2\] + *[0-9a-f]+: a5200000 ld1row {z0\.s}, p0/z, \[x0, x0, lsl #2\] + *[0-9a-f]+: a5bb1411 ld1rod {z17\.d}, p5/z, \[x0, x27, lsl #3\] + *[0-9a-f]+: a5a00000 ld1rod {z0\.d}, p0/z, \[x0, x0, lsl #3\] *[0-9a-f]+: a42037f1 ld1rob {z17\.b}, p5/z, \[sp\] *[0-9a-f]+: a42723e0 ld1rob {z0\.b}, p0/z, \[sp, #224\] *[0-9a-f]+: a42823e0 ld1rob {z0\.b}, p0/z, \[sp, #-256\] diff --git a/gas/testsuite/gas/aarch64/f64mm.s b/gas/testsuite/gas/aarch64/f64mm.s index cfe6b17..a58b3e9 100644 --- a/gas/testsuite/gas/aarch64/f64mm.s +++ b/gas/testsuite/gas/aarch64/f64mm.s @@ -13,21 +13,21 @@ fmmla z0.d, z0.d, z0.d ld1rob { z17.b }, p5/z, [sp, x27] ld1rob { z0.b }, p0/z, [sp, x0] -ld1roh { z17.h }, p5/z, [sp, x27] -ld1roh { z0.h }, p0/z, [sp, x0] -ld1row { z17.s }, p5/z, [sp, x27] -ld1row { z0.s }, p0/z, [sp, x0] -ld1rod { z17.d }, p5/z, [sp, x27] -ld1rod { z0.d }, p0/z, [sp, x0] +ld1roh { z17.h }, p5/z, [sp, x27, lsl #1] +ld1roh { z0.h }, p0/z, [sp, x0, lsl #1] +ld1row { z17.s }, p5/z, [sp, x27, lsl #2] +ld1row { z0.s }, p0/z, [sp, x0, lsl #2] +ld1rod { z17.d }, p5/z, [sp, x27, lsl #3] +ld1rod { z0.d }, p0/z, [sp, x0, lsl #3] ld1rob { z17.b }, p5/z, [x0, x27] ld1rob { z0.b }, p0/z, [x0, x0] -ld1roh { z17.h }, p5/z, [x0, x27] -ld1roh { z0.h }, p0/z, [x0, x0] -ld1row { z17.s }, p5/z, [x0, x27] -ld1row { z0.s }, p0/z, [x0, x0] -ld1rod { z17.d }, p5/z, [x0, x27] -ld1rod { z0.d }, p0/z, [x0, x0] +ld1roh { z17.h }, p5/z, [x0, x27, lsl #1] +ld1roh { z0.h }, p0/z, [x0, x0, lsl #1] +ld1row { z17.s }, p5/z, [x0, x27, lsl #2] +ld1row { z0.s }, p0/z, [x0, x0, lsl #2] +ld1rod { z17.d }, p5/z, [x0, x27, lsl #3] +ld1rod { z0.d }, p0/z, [x0, x0, lsl #3] ld1rob { z17.b }, p5/z, [sp, #0] ld1rob { z0.b }, p0/z, [sp, #224] |