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authorYufeng Zhang <yufeng.zhang@arm.com>2013-11-18 11:34:43 +0000
committerYufeng Zhang <yufeng.zhang@arm.com>2013-11-18 11:42:42 +0000
commit18cf6de4004b9eaa1a2c0be8dd03523fd60991d1 (patch)
tree84c91be5d2df9bd00825d60f98154af11a679ac1 /gas
parenta203d9b72fc2bc37992e0f0e3f2b7f0d9abdd0bd (diff)
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gas/
* config/tc-aarch64.c (parse_sys_reg): Support S2_<op1>_<Cn>_<Cm>_<op2>. gas/testsuite/ * gas/testsuite/sysreg.s: Add test. * gas/testsuite/sysreg.d: Update.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-aarch64.c10
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/aarch64/sysreg.d2
-rw-r--r--gas/testsuite/gas/aarch64/sysreg.s3
5 files changed, 20 insertions, 5 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d32a4d0..da64a28 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-18 Zhenqiang Chen <zhenqiang.chen@linaro.org>
+
+ * config/tc-aarch64.c (parse_sys_reg): Support
+ S2_<op1>_<Cn>_<Cm>_<op2>.
+
2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
Revert
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c230b1e..fb0ae33 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3270,7 +3270,7 @@ parse_barrier (char **str)
Returns the encoding for the option, or PARSE_FAIL.
If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
- implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
+ implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
static int
parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
@@ -3295,7 +3295,7 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
return PARSE_FAIL;
else
{
- /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
+ /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
registers. */
unsigned int op0, op1, cn, cm, op2;
if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
@@ -3303,11 +3303,11 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
/* The architecture specifies the encoding space for implementation
defined registers as:
op0 op1 CRn CRm op2
- 11 xxx 1x11 xxxx xxx
+ 1x xxx 1x11 xxxx xxx
For convenience GAS accepts a wider encoding space, as follows:
op0 op1 CRn CRm op2
- 11 xxx xxxx xxxx xxx */
- if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
+ 1x xxx xxxx xxxx xxx */
+ if ((op0 != 2 && op0 != 3) || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
return PARSE_FAIL;
value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
}
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5f860bc..f2912bb 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-18 Zhenqiang Chen <zhenqiang.chen@linaro.org>
+
+ * gas/testsuite/sysreg.s: Add test.
+ * gas/testsuite/sysreg.d: Update.
+
2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
Revert
diff --git a/gas/testsuite/gas/aarch64/sysreg.d b/gas/testsuite/gas/aarch64/sysreg.d
index c7cf00e..7795b4d 100644
--- a/gas/testsuite/gas/aarch64/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg.d
@@ -26,3 +26,5 @@ Disassembly of section \.text:
48: d538cc00 mrs x0, s3_0_c12_c12_0
4c: d5384600 mrs x0, s3_0_c4_c6_0
50: d5184600 msr s3_0_c4_c6_0, x0
+ 54: d5310300 mrs x0, s2_1_c0_c3_0
+ 58: d5110300 msr s2_1_c0_c3_0, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg.s b/gas/testsuite/gas/aarch64/sysreg.s
index 3287594..b7e5ff6 100644
--- a/gas/testsuite/gas/aarch64/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg.s
@@ -26,3 +26,6 @@
mrs x0, s3_0_c12_c12_0
mrs x0, s3_0_c4_c6_0
msr s3_0_c4_c6_0, x0
+
+ mrs x0, s2_1_c0_c3_0
+ msr s2_1_c0_c3_0, x0