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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-08-12 06:16:51 +0900 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-03 04:04:35 +0000 |
| commit | 7b4f240762ffa03e65e17cb7dee807bc1628c24a (patch) | |
| tree | f428de64dfdf15773b3c37b78d99796ebf2a1b8c /gas/testsuite | |
| parent | 61233edc75c8aaa003e7cbe5e129faf6bb7b9126 (diff) | |
| download | gdb-7b4f240762ffa03e65e17cb7dee807bc1628c24a.zip gdb-7b4f240762ffa03e65e17cb7dee807bc1628c24a.tar.gz gdb-7b4f240762ffa03e65e17cb7dee807bc1628c24a.tar.bz2 | |
RISC-V: Assign DWARF numbers to vector registers
This commit assigns DWARF register numbers to vector registers (v0-v31:
96..127) to implement RISC-V DWARF Specification version 1.0-rc4
(now in the frozen state):
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4
binutils/ChangeLog:
* dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers
96..127 to vector registers v0-v31.
gas/ChangeLog:
* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support
vector registers.
* testsuite/gas/riscv/dw-regnums.s: Add vector registers to the
DWARF register number test.
* testsuite/gas/riscv/dw-regnums.d: Likewise.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/riscv/dw-regnums.d | 34 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/dw-regnums.s | 38 |
2 files changed, 70 insertions, 2 deletions
diff --git a/gas/testsuite/gas/riscv/dw-regnums.d b/gas/testsuite/gas/riscv/dw-regnums.d index 5f1c879..5ec61b9 100644 --- a/gas/testsuite/gas/riscv/dw-regnums.d +++ b/gas/testsuite/gas/riscv/dw-regnums.d @@ -1,4 +1,4 @@ -#as: -march=rv32if +#as: -march=rv32iv #objdump: --dwarf=frames @@ -145,4 +145,36 @@ Contents of the .* section: DW_CFA_offset_extended_sf: r61 \(ft9\) at cfa\+248 DW_CFA_offset_extended_sf: r62 \(ft10\) at cfa\+252 DW_CFA_offset_extended_sf: r63 \(ft11\) at cfa\+256 + DW_CFA_offset_extended_sf: r96 \(v0\) at cfa\+388 + DW_CFA_offset_extended_sf: r97 \(v1\) at cfa\+392 + DW_CFA_offset_extended_sf: r98 \(v2\) at cfa\+396 + DW_CFA_offset_extended_sf: r99 \(v3\) at cfa\+400 + DW_CFA_offset_extended_sf: r100 \(v4\) at cfa\+404 + DW_CFA_offset_extended_sf: r101 \(v5\) at cfa\+408 + DW_CFA_offset_extended_sf: r102 \(v6\) at cfa\+412 + DW_CFA_offset_extended_sf: r103 \(v7\) at cfa\+416 + DW_CFA_offset_extended_sf: r104 \(v8\) at cfa\+420 + DW_CFA_offset_extended_sf: r105 \(v9\) at cfa\+424 + DW_CFA_offset_extended_sf: r106 \(v10\) at cfa\+428 + DW_CFA_offset_extended_sf: r107 \(v11\) at cfa\+432 + DW_CFA_offset_extended_sf: r108 \(v12\) at cfa\+436 + DW_CFA_offset_extended_sf: r109 \(v13\) at cfa\+440 + DW_CFA_offset_extended_sf: r110 \(v14\) at cfa\+444 + DW_CFA_offset_extended_sf: r111 \(v15\) at cfa\+448 + DW_CFA_offset_extended_sf: r112 \(v16\) at cfa\+452 + DW_CFA_offset_extended_sf: r113 \(v17\) at cfa\+456 + DW_CFA_offset_extended_sf: r114 \(v18\) at cfa\+460 + DW_CFA_offset_extended_sf: r115 \(v19\) at cfa\+464 + DW_CFA_offset_extended_sf: r116 \(v20\) at cfa\+468 + DW_CFA_offset_extended_sf: r117 \(v21\) at cfa\+472 + DW_CFA_offset_extended_sf: r118 \(v22\) at cfa\+476 + DW_CFA_offset_extended_sf: r119 \(v23\) at cfa\+480 + DW_CFA_offset_extended_sf: r120 \(v24\) at cfa\+484 + DW_CFA_offset_extended_sf: r121 \(v25\) at cfa\+488 + DW_CFA_offset_extended_sf: r122 \(v26\) at cfa\+492 + DW_CFA_offset_extended_sf: r123 \(v27\) at cfa\+496 + DW_CFA_offset_extended_sf: r124 \(v28\) at cfa\+500 + DW_CFA_offset_extended_sf: r125 \(v29\) at cfa\+504 + DW_CFA_offset_extended_sf: r126 \(v30\) at cfa\+508 + DW_CFA_offset_extended_sf: r127 \(v31\) at cfa\+512 #... diff --git a/gas/testsuite/gas/riscv/dw-regnums.s b/gas/testsuite/gas/riscv/dw-regnums.s index 6686e8b..bbe1b13 100644 --- a/gas/testsuite/gas/riscv/dw-regnums.s +++ b/gas/testsuite/gas/riscv/dw-regnums.s @@ -1,6 +1,8 @@ # Check that CFI directives can accept all of the register names (including # aliases). The results for this test also ensures that the DWARF -# register numbers for the GPRs/FPRs registers shouldn't change. +# register numbers for the GPRs/FPRs/vector registers shouldn't change. +# Note that, because vector register size is "variable" in principle, +# vector registers are very unlikely to be used within .cfi_offset directive. .text .global _start @@ -144,5 +146,39 @@ _start: .cfi_offset f30, 252 .cfi_offset f31, 256 + # Vector registers (numeric only) + .cfi_offset v0, 388 + .cfi_offset v1, 392 + .cfi_offset v2, 396 + .cfi_offset v3, 400 + .cfi_offset v4, 404 + .cfi_offset v5, 408 + .cfi_offset v6, 412 + .cfi_offset v7, 416 + .cfi_offset v8, 420 + .cfi_offset v9, 424 + .cfi_offset v10, 428 + .cfi_offset v11, 432 + .cfi_offset v12, 436 + .cfi_offset v13, 440 + .cfi_offset v14, 444 + .cfi_offset v15, 448 + .cfi_offset v16, 452 + .cfi_offset v17, 456 + .cfi_offset v18, 460 + .cfi_offset v19, 464 + .cfi_offset v20, 468 + .cfi_offset v21, 472 + .cfi_offset v22, 476 + .cfi_offset v23, 480 + .cfi_offset v24, 484 + .cfi_offset v25, 488 + .cfi_offset v26, 492 + .cfi_offset v27, 496 + .cfi_offset v28, 500 + .cfi_offset v29, 504 + .cfi_offset v30, 508 + .cfi_offset v31, 512 + nop .cfi_endproc |