x86/Intel: restrict suffix derivation

While in some cases deriving an AT&T-style suffix from an Intel syntax
memory operand size specifier is necessary, in many cases this is not
only pointless, but has led to the introduction of various workarounds:
Excessive use of IgnoreSize and NoRex64 as well as the ToDword and
ToQword attributes. Suppress suffix derivation when we can clearly tell
that the memory operand's size isn't going to be needed to infer the
possible need for the low byte/word opcode bit or an operand size prefix
(0x66 or REX.W).

As a result ToDword and ToQword can be dropped entirely, plus a fair
number of IgnoreSize and NoRex64 can also be got rid of. Note that
IgnoreSize needs to remain on legacy encoded SIMD insns with GPR
operand, to avoid emitting an operand size prefix in 16-bit mode. (Since
16-bit code using SIMD insns isn't well tested, clone an existing
testcase just enough to cover a few insns which are potentially
problematic but are being touched here.)

Note that while folding the VCVT{,T}S{S,D}2SI templates, VCVT{,T}SH2SI
isn't included there. This is to fulfill the request of not allowing L
and Q suffixes there, despite the inconsistency with VCVT{,T}S{S,D}2SI.

4 files changed, 145 insertions, 0 deletions

diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 68576be..0ad2b6a 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -169,6 +169,7 @@ if [gas_32_check] then {
     run_dump_test "simd"
     run_dump_test "simd-intel"
     run_dump_test "simd-suffix"
+    run_dump_test "simd16"
     run_dump_test "mem"
     run_dump_test "mem-intel"
     run_dump_test "reg"
diff --git a/gas/testsuite/gas/i386/simd.s b/gas/testsuite/gas/i386/simd.s
index faa37cf..75cd440 100644
--- a/gas/testsuite/gas/i386/simd.s
+++ b/gas/testsuite/gas/i386/simd.s
@@ -1,5 +1,6 @@
 	.text
 _start:
+	.ifndef use16
 	addsubps 0x12345678,%xmm1
 	comisd 0x12345678,%xmm1
 	comiss 0x12345678,%xmm1
@@ -31,6 +32,7 @@ _start:
 	punpcklqdq 0x12345678,%xmm1
 	ucomisd 0x12345678,%xmm1
 	ucomiss 0x12345678,%xmm1
+	.endif
 
 	cmpeqsd (%eax),%xmm0
 	cmpeqss (%eax),%xmm0
@@ -101,6 +103,7 @@ cmpsd	$0x10,(%eax),%xmm7
 
 	.intel_syntax noprefix
 
+	.ifndef use16
 addsubps xmm1,XMMWORD PTR ds:0x12345678
 comisd xmm1,QWORD PTR ds:0x12345678
 comiss xmm1,DWORD PTR ds:0x12345678
@@ -132,6 +135,8 @@ punpcklwd xmm1,XMMWORD PTR ds:0x12345678
 punpcklqdq xmm1,XMMWORD PTR ds:0x12345678
 ucomisd xmm1,QWORD PTR ds:0x12345678
 ucomiss xmm1,DWORD PTR ds:0x12345678
+	.endif
+
 cmpeqsd xmm0,QWORD PTR [eax]
 cmpeqss xmm0,DWORD PTR [eax]
 cvtpi2pd xmm0,QWORD PTR [eax]
diff --git a/gas/testsuite/gas/i386/simd16.d b/gas/testsuite/gas/i386/simd16.d
new file mode 100644
index 0000000..5900c77
--- /dev/null
+++ b/gas/testsuite/gas/i386/simd16.d
@@ -0,0 +1,137 @@
+#as: --defsym use16=1 -I${srcdir}/$subdir
+#objdump: -dw -Mi8086
+#name: i386 SIMD (16-bit)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	67 f2 0f c2 00 00    	cmpeqsd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f c2 00 00    	cmpeqss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 2a 00       	cvtpi2pd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 0f 2a 00          	cvtpi2ps \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 0f 2d 00          	cvtps2pi \(%eax\),%mm0
+[ 	]*[a-f0-9]+:	67 f2 0f 2d 00       	cvtsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f2 0f 2c 00       	cvttsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f2 0f 5a 00       	cvtsd2ss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5a 00       	cvtss2sd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 2d 00       	cvtss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f3 0f 2c 00       	cvttss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f2 0f 5e 00       	divsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5e 00       	divss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 5f 00       	maxsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5f 00       	maxss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5d 00       	minss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5d 00       	minss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 2b 00       	movntsd %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f3 0f 2b 00       	movntss %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f2 0f 10 00       	movsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 11 00       	movsd  %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f3 0f 10 00       	movss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 11 00       	movss  %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f2 0f 59 00       	mulsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 59 00       	mulss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 53 00       	rcpss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 3a 0b 00 00 	roundsd \$0x0,\(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 3a 0a 00 00 	roundss \$0x0,\(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 52 00       	rsqrtss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 51 00       	sqrtsd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 51 00       	sqrtss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 5c 00       	subsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5c 00       	subss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 20 00    	pmovsxbw \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 21 00    	pmovsxbd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 22 00    	pmovsxbq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 23 00    	pmovsxwd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 24 00    	pmovsxwq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 25 00    	pmovsxdq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 30 00    	pmovzxbw \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 31 00    	pmovzxbd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 32 00    	pmovzxbq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 33 00    	pmovzxwd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 34 00    	pmovzxwq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 35 00    	pmovzxdq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 3a 21 00 00 	insertps \$0x0,\(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 15 08       	unpckhpd \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 0f 15 08          	unpckhps \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 66 0f 14 08       	unpcklpd \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 0f 14 08          	unpcklps \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	f3 0f c2 f7 10       	cmpss  \$0x10,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	67 f3 0f c2 38 10    	cmpss  \$0x10,\(%eax\),%xmm7
+[ 	]*[a-f0-9]+:	f2 0f c2 f7 10       	cmpsd  \$0x10,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	67 f2 0f c2 38 10    	cmpsd  \$0x10,\(%eax\),%xmm7
+[ 	]*[a-f0-9]+:	f3 0f 2a c8          	cvtsi2ss %eax,%xmm1
+[ 	]*[a-f0-9]+:	f2 0f 2a c8          	cvtsi2sd %eax,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 2a c8          	cvtsi2ss %eax,%xmm1
+[ 	]*[a-f0-9]+:	f2 0f 2a c8          	cvtsi2sd %eax,%xmm1
+[ 	]*[a-f0-9]+:	67 f3 0f 2a 08       	cvtsi2ss \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f2 0f 2a 08       	cvtsi2sd \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f3 0f 2a 08       	cvtsi2ss \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f2 0f 2a 08       	cvtsi2sd \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f2 0f c2 00 00    	cmpeqsd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f c2 00 00    	cmpeqss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 2a 00       	cvtpi2pd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 0f 2a 00          	cvtpi2ps \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 0f 2d 00          	cvtps2pi \(%eax\),%mm0
+[ 	]*[a-f0-9]+:	67 f2 0f 2d 00       	cvtsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f2 0f 2c 00       	cvttsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f2 0f 5a 00       	cvtsd2ss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5a 00       	cvtss2sd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 2d 00       	cvtss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f3 0f 2c 00       	cvttss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	67 f2 0f 5e 00       	divsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5e 00       	divss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 5f 00       	maxsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5f 00       	maxss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5d 00       	minss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5d 00       	minss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 2b 00       	movntsd %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f3 0f 2b 00       	movntss %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f2 0f 10 00       	movsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 11 00       	movsd  %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f3 0f 10 00       	movss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 11 00       	movss  %xmm0,\(%eax\)
+[ 	]*[a-f0-9]+:	67 f2 0f 59 00       	mulsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 59 00       	mulss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 53 00       	rcpss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 3a 0b 00 00 	roundsd \$0x0,\(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 3a 0a 00 00 	roundss \$0x0,\(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 52 00       	rsqrtss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 51 00       	sqrtsd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 51 00       	sqrtss \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f2 0f 5c 00       	subsd  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 f3 0f 5c 00       	subss  \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 20 00    	pmovsxbw \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 21 00    	pmovsxbd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 22 00    	pmovsxbq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 23 00    	pmovsxwd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 24 00    	pmovsxwq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 25 00    	pmovsxdq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 30 00    	pmovzxbw \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 31 00    	pmovzxbd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 32 00    	pmovzxbq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 33 00    	pmovzxwd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 34 00    	pmovzxwq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 38 35 00    	pmovzxdq \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 3a 21 00 00 	insertps \$0x0,\(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 15 00       	unpckhpd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 0f 15 00          	unpckhps \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 66 0f 14 00       	unpcklpd \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	67 0f 14 00          	unpcklps \(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	f3 0f c2 f7 10       	cmpss  \$0x10,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	67 f3 0f c2 38 10    	cmpss  \$0x10,\(%eax\),%xmm7
+[ 	]*[a-f0-9]+:	f2 0f c2 f7 10       	cmpsd  \$0x10,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	67 f2 0f c2 38 10    	cmpsd  \$0x10,\(%eax\),%xmm7
+[ 	]*[a-f0-9]+:	f3 0f 2a c8          	cvtsi2ss %eax,%xmm1
+[ 	]*[a-f0-9]+:	f2 0f 2a c8          	cvtsi2sd %eax,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 2a c8          	cvtsi2ss %eax,%xmm1
+[ 	]*[a-f0-9]+:	f2 0f 2a c8          	cvtsi2sd %eax,%xmm1
+[ 	]*[a-f0-9]+:	67 f3 0f 2a 08       	cvtsi2ss \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f3 0f 2a 08       	cvtsi2ss \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f2 0f 2a 08       	cvtsi2sd \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f2 0f 2a 08       	cvtsi2sd \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f3 0f 2a 08       	cvtsi2ss \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 f2 0f 2a 08       	cvtsi2sd \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	67 0f 2c 00          	cvttps2pi \(%eax\),%mm0
+#pass
diff --git a/gas/testsuite/gas/i386/simd16.s b/gas/testsuite/gas/i386/simd16.s
new file mode 100644
index 0000000..8aebf83
--- /dev/null
+++ b/gas/testsuite/gas/i386/simd16.s
@@ -0,0 +1,2 @@
+	.code16
+	.include "simd.s"