Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add support

for m68hc11 and m68hc12 processors.

5 files changed, 290 insertions, 1 deletions

diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index c6eaf77..65d7d6e 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -26,6 +26,7 @@ CPU_DOCS = \
 	c-i386.texi \
 	c-i960.texi \
 	c-m32r.texi \
+	c-m68hc11.texi \
 	c-m68k.texi \
 	c-mips.texi \
 	c-ns32k.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 48f4e08..6336678 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -129,6 +129,7 @@ CPU_DOCS = \
 	c-i386.texi \
 	c-i960.texi \
 	c-m32r.texi \
+	c-m68hc11.texi \
 	c-m68k.texi \
 	c-mips.texi \
 	c-ns32k.texi \
@@ -164,7 +165,7 @@ DIST_COMMON =  Makefile.am Makefile.in
 
 DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
 
-TAR = tar
+TAR = gtar
 GZIP_ENV = --best
 all: all-redirect
 .SUFFIXES:
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index d1058fb..14f735d 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -37,6 +37,7 @@
 @set I80386
 @set I960
 @set M32R
+@set M68HC11
 @set M680X0
 @set MCORE
 @set MIPS
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 20efcd3..62f8868 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -267,6 +267,11 @@ Here is a brief summary of how to invoke @code{@value{AS}}.  For details,
  [ -jsri2bsr ] [ -sifilter ] [ -relax ]
  [ -mcpu=[210|340] ]
 @end ifset
+@ifset M68HC11
+ [ -m68hc11 | -m68hc12 ]
+ [ --force-long-branchs ] [ --short-branchs ] [ --strict-direct-mode ]
+ [ --print-insn-syntax ] [ --print-opcodes ] [ --generate-example ]
+@end ifset
 @ifset MIPS
  [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
  [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ]
@@ -558,6 +563,42 @@ Generate ``little endian'' format output.
 @end table
 @end ifset
 
+@ifset M68HC11
+The following options are available when @value{AS} is configured for the
+Motorola 68HC11 or 68HC12 series.
+
+@table @code
+
+@item -m68hc11 | -m68hc12
+Specify what processor is the target.  The default is
+defined by the configuration option when building the assembler.
+
+@item --force-long-branchs
+Relative branches are turned into absolute ones. This concerns
+conditional branches, unconditional branches and branches to a
+sub routine.
+
+@item -S | --short-branchs
+Do not turn relative branchs into absolute ones
+when the offset is out of range.
+
+@item --strict-direct-mode
+Do not turn the direct addressing mode into extended addressing mode
+when the instruction does not support direct addressing mode.
+
+@item --print-insn-syntax
+Print the syntax of instruction in case of error.
+
+@item --print-opcodes
+print the list of instructions with syntax and then exit.
+
+@item --generate-example
+print an example of instruction for each possible instruction and then exit.
+This option is only useful for testing @code{@value{AS}}.
+
+@end table
+@end ifset
+
 @ifset SPARC
 The following options are available when @code{@value{AS}} is configured
 for the SPARC architecture:
@@ -1614,6 +1655,9 @@ is considered a comment and is ignored.  The line comment character is
 @ifset M680X0
 @samp{|} on the 680x0;
 @end ifset
+@ifset M68HC11
+@samp{#} on the 68HC11 and 68HC12;
+@end ifset
 @ifset VAX
 @samp{#} on the Vax;
 @end ifset
@@ -4972,6 +5016,9 @@ subject, see the hardware manufacturer's manual.
 @ifset M680X0
 * M68K-Dependent::              M680x0 Dependent Features
 @end ifset
+@ifset M68HC11
+* M68HC11-Dependent::           M68HC11 and 68HC12 Dependent Features
+@end ifset
 @ifset MIPS
 * MIPS-Dependent::              MIPS Dependent Features
 @end ifset
@@ -5150,6 +5197,10 @@ family.
 @include c-m68k.texi
 @end ifset
 
+@ifset M68HC11
+@include c-m68hc11.texi
+@end ifset
+
 @ifset MIPS
 @include c-mips.texi
 @end ifset
diff --git a/gas/doc/c-m68hc11.texi b/gas/doc/c-m68hc11.texi
new file mode 100644
index 0000000..df80f8d
--- /dev/null
+++ b/gas/doc/c-m68hc11.texi
@@ -0,0 +1,235 @@
+@c Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node M68HC11-Dependent
+@chapter M68HC11 and M68HC12 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter M68HC11 and M68HC12 Dependent Features
+@end ifclear
+
+@cindex M68HC11 and M68HC12 support
+@menu
+* M68HC11-Opts::                   M68HC11 and M68HC12 Options
+* M68HC11-Syntax::                 Syntax
+* M68HC11-Float::                  Floating Point
+* M68HC11-opcodes::                Opcodes
+@end menu
+
+@node M68HC11-Opts
+@section M68HC11 and M68HC12 Options
+
+@cindex options, M68HC11
+@cindex M68HC11 options
+The Motorola 68HC11 and 68HC12 version of @code{@value{AS}} has a few machine
+dependent options.
+
+@cindex @samp{-m68hc11}
+This option switches the assembler in the M68HC11 mode. In this mode,
+the assembler only accepts 68HC11 operands and mnemonics. It produces
+code for the 68HC11.
+
+@cindex @samp{-m68hc12}
+This option switches the assembler in the M68HC12 mode. In this mode,
+the assembler also accepts 68HC12 operands and mnemonics. It produces
+code for the 68HC12. A fiew 68HC11 instructions are replaced by
+some 68HC12 instructions as recommended by Motorola specifications.
+
+@cindex @samp{--strict-direct-mode}
+You can use the @samp{--strict-direct-mode} option to disable
+the automatic translation of direct page mode addressing into
+extended mode when the instruction does not support direct mode.
+For example, the @samp{clr} instruction does not support direct page
+mode addressing. When it is used with the direct page mode,
+@code{@value{AS}} will ignore it and generate an absolute addressing.
+This option prevents @code{@value{AS}} from doing this, and the wrong
+usage of the direct page mode will raise an error.
+
+@cindex @samp{--short-branchs}
+The @samp{--short-branchs} option turns off the translation of
+relative branches into absolute branches when the branch offset is
+out of range. By default @code{@value{AS}} transforms the relative
+branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne},
+@samp{ble}, @samp{blt}, @samp{bhi}, @samp{bcc}, @samp{bls},
+@samp{bcs}, @samp{bmi}, @samp{bvs}, @samp{bvs}, @samp{bra}) into
+an absolute branch when the offset is out of the -128 .. 127 range.
+In that case, the @samp{bsr} instruction is translated into a
+@samp{jsr}, the @samp{bra} instruction is translated into a
+@samp{jmp} and the conditional branchs instructions are inverted and
+followed by a @samp{jmp}. This option disables these translations
+and @code{@value{AS}} will generate an error if a relative branch
+is out of range. This option does not affect the optimization
+associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes.
+
+@cindex @samp{--force-long-branchs}
+The @samp{--force-long-branchs} option forces the translation of
+relative branches into absolute branches. This option does not affect
+the optimization associated to the @samp{jbra}, @samp{jbsr} and
+@samp{jbXX} pseudo opcodes. 
+
+@cindex @samp{--print-insn-syntax}
+You can use the @samp{--print-insn-syntax} option to obtain the
+syntax description of the instruction when an error is detected.
+
+@cindex @samp{--print-opcodes}
+The @samp{--print-opcodes} option prints the list of all the
+instructions with their syntax. The first item of each line
+represents the instruction name and the rest of the line indicates
+the possible operands for that instruction. The list is printed
+in alphabetical order. Once the list is printed @code{@value{AS}}
+exits.
+
+@cindex @samp{--generate-example}
+The @samp{--generate-example} option is similar to @samp{--print-opcodes}
+but it generates an example for each instruction instead.
+
+@node M68HC11-Syntax
+@section Syntax
+
+@cindex M68HC11 syntax
+@cindex syntax, M68HC11
+
+In the M68HC11 syntax, the instruction name comes first and it may
+be followed by one or several operands (up to three). Operands are
+separated by comma (@samp{,}). In the normal mode,
+@code{@value{AS}} will complain if too many operands are specified for
+a given instruction. In the MRI mode (turned on with @samp{-M} option),
+it will treat them as comments. Example:
+
+@smallexample
+inx
+lda  #23
+bset 2,x #4
+brclr *bot #8 foo
+@end smallexample
+
+@cindex M68HC11 addressing modes
+@cindex addressing modes, M68HC11
+The following addressing modes are understood:
+@table @dfn
+@item Immediate
+@samp{#@var{number}}
+
+@item Address Register
+@samp{@var{number},X}, @samp{@var{number},Y}
+
+The @var{number} may be omitted in which case 0 is assumed.
+
+@item Direct Addressing mode
+@samp{*@var{symbol}}, or @samp{*@var{digits}}
+
+@item Absolute
+@samp{@var{symbol}}, or @samp{@var{digits}}
+@end table
+
+@node M68HC11-Float
+@section Floating Point
+
+@cindex floating point, M68HC11
+@cindex M68HC11 floating point
+Packed decimal (P) format floating literals are not supported.
+Feel free to add the code!
+
+The floating point formats generated by directives are these.
+
+@table @code
+@cindex @code{float} directive, M68HC11
+@item .float
+@code{Single} precision floating point constants.
+
+@cindex @code{double} directive, M68HC11
+@item .double
+@code{Double} precision floating point constants.
+
+@cindex @code{extend} directive M68HC11
+@cindex @code{ldouble} directive M68HC11
+@item .extend
+@itemx .ldouble
+@code{Extended} precision (@code{long double}) floating point constants.
+@end table
+
+@need 2000
+@node M68HC11-opcodes
+@section Opcodes
+
+@cindex M68HC11 opcodes
+@cindex opcodes, M68HC11
+@cindex instruction set, M68HC11
+
+@menu
+* M68HC11-Branch::                 Branch Improvement
+@end menu
+
+@node M68HC11-Branch
+@subsection Branch Improvement
+
+@cindex pseudo-opcodes, M68HC11
+@cindex M68HC11 pseudo-opcodes
+@cindex branch improvement, M68HC11
+@cindex M68HC11 branch improvement
+
+Certain pseudo opcodes are permitted for branch instructions.
+They expand to the shortest branch instruction that reach the
+target. Generally these mnemonics are made by prepending @samp{j} to
+the start of Motorola mnemonic. These pseudo opcodes are not affected
+by the @samp{--short-branchs} or @samp{--force-long-branchs} options.
+
+The following table summarizes the pseudo-operations.
+
+@smallexample
+                              Displacement Width
+          +-------------------------------------------------------------+
+          |                     Options                                 |
+          |    --short-branchs            --force-long-branchs          |
+          +--------------------------+----------------------------------+
+Pseudo-Op |BYTE             WORD     | BYTE          WORD               |
+          +--------------------------+----------------------------------+
+      bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
+      bra | bra <pc-rel>    <error>  |               jmp <abs>          |
+     jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
+     jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
+      bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  | 
+     jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
+          |                jmp <abs> |                                  |
+          +--------------------------+----------------------------------+
+XX: condition
+NX: negative of condition XX
+
+@end smallexample
+
+@table @code
+@item jbsr
+@itemx jbra
+These are the simplest jump pseudo-operations; they always map to one
+particular machine instruction, depending on the displacement to the
+branch target.
+
+@item jb@var{XX}
+Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations,
+where @var{XX} is a conditional branch or condition-code test.  The full
+list of pseudo-ops in this family is:
+@smallexample
+ jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
+ jbcs   jbne   jblt   jble   jbls   jbvc   jbmi
+@end smallexample
+
+For the cases of non-PC relative displacements and long displacements,
+@code{@value{AS}} issues a longer code fragment in terms of
+@var{NX}, the opposite condition to @var{XX}.  For example, for the
+non-PC relative case:
+@smallexample
+    jb@var{XX} foo
+@end smallexample
+gives
+@smallexample
+     b@var{NX}s oof
+     jmp foo
+ oof:
+@end smallexample
+
+@end table
+
+