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| author | Nick Clifton <nickc@redhat.com> | 2018-03-28 09:44:45 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2018-03-28 09:44:45 +0100 |
| commit | c8d59609b1cf66eaff3c486e483f5e3d647c66ff (patch) | |
| tree | 66054d403bc11d2c064100c3a159a08a2005233c /gas/config | |
| parent | 9c75b45645acb30c42f09b80cbaadbde391aa7b2 (diff) | |
| download | gdb-c8d59609b1cf66eaff3c486e483f5e3d647c66ff.zip gdb-c8d59609b1cf66eaff3c486e483f5e3d647c66ff.tar.gz gdb-c8d59609b1cf66eaff3c486e483f5e3d647c66ff.tar.bz2 | |
Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register.
PR 22988
opcode * opcode/aarch64.h (enum aarch64_opnd): Add
AARCH64_OPND_SVE_ADDR_R.
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
instructions with only a base address register.
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
handle AARHC64_OPND_SVE_ADDR_R.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64_dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * config/tc-aarch64.c (parse_operands): Add code to handle
AARCH64_OPN_SVE_ADDR_R.
* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
with an assumed XZR offset address register.
* testsuite/gas/aarch64/sve.d: Update expected disassembly.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-aarch64.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 3a0cde9..e857f29 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -3695,6 +3695,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand, set_syntax_error (_("missing offset in the pre-indexed address")); return FALSE; } + operand->addr.preind = 1; inst.reloc.exp.X_op = O_constant; inst.reloc.exp.X_add_number = 0; @@ -6233,6 +6234,25 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->addr.offset.imm = inst.reloc.exp.X_add_number; break; + case AARCH64_OPND_SVE_ADDR_R: + /* [<Xn|SP>{, <R><m>}] + but recognizing SVE registers. */ + po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, + &offset_qualifier)); + if (offset_qualifier == AARCH64_OPND_QLF_NIL) + { + offset_qualifier = AARCH64_OPND_QLF_X; + info->addr.offset.is_reg = 1; + info->addr.offset.regno = 31; + } + else if (base_qualifier != AARCH64_OPND_QLF_X + || offset_qualifier != AARCH64_OPND_QLF_X) + { + set_syntax_error (_("invalid addressing mode")); + goto failure; + } + goto regoff_addr; + case AARCH64_OPND_SVE_ADDR_RR: case AARCH64_OPND_SVE_ADDR_RR_LSL1: case AARCH64_OPND_SVE_ADDR_RR_LSL2: |