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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 01:09:36 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 01:12:10 +0100 |
| commit | a4f89915135f6760917c01dc783de5b674234d84 (patch) | |
| tree | 7361b054783a02df06643a4e1cd23e0607fb4680 /binutils | |
| parent | de428bc53335d88c21eda38a823d5a4008468e52 (diff) | |
| download | gdb-a4f89915135f6760917c01dc783de5b674234d84.zip gdb-a4f89915135f6760917c01dc783de5b674234d84.tar.gz gdb-a4f89915135f6760917c01dc783de5b674234d84.tar.bz2 | |
MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand
in the hexadecimal rather than decimal numeral system and add respective
operandless variants with an implicit 0 operand, making our handling of
these instructions consistent with how we have processed their regular
MIPS and microMIPS counterparts since forever.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
type to hexadecimal.
(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
and SDBBP disassembly.
gas/
* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-sub.d: Likewise.
* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
Diffstat (limited to 'binutils')
| -rw-r--r-- | binutils/ChangeLog | 5 | ||||
| -rw-r--r-- | binutils/testsuite/binutils-all/mips/mips16-extend-insn.d | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index e47d825..5e51572 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2017-05-12 Maciej W. Rozycki <macro@imgtec.com> + + * testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK + and SDBBP disassembly. + 2017-05-10 Maciej W. Rozycki <macro@imgtec.com> * testsuite/binutils-all/mips/mips.exp: Define `tempfile' and diff --git a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d index ef4f5a4..a962320 100644 --- a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d +++ b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d @@ -215,7 +215,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f123 extend 0x123 [0-9a-f]+ <[^>]*> e8c0 jalrc s0 [0-9a-f]+ <[^>]*> f123 extend 0x123 -[0-9a-f]+ <[^>]*> e801 sdbbp 0 +[0-9a-f]+ <[^>]*> e801 sdbbp [0-9a-f]+ <[^>]*> f123 extend 0x123 [0-9a-f]+ <[^>]*> e802 slt s0,s0 [0-9a-f]+ <[^>]*> f123 extend 0x123 @@ -223,7 +223,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f123 extend 0x123 [0-9a-f]+ <[^>]*> e804 sllv s0,s0 [0-9a-f]+ <[^>]*> f123 extend 0x123 -[0-9a-f]+ <[^>]*> e805 break 0 +[0-9a-f]+ <[^>]*> e805 break [0-9a-f]+ <[^>]*> f123 extend 0x123 [0-9a-f]+ <[^>]*> e806 srlv s0,s0 [0-9a-f]+ <[^>]*> f123 extend 0x123 |