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authorAnthony Green <green@moxielogic.com>2014-12-24 08:37:16 -0500
committerAnthony Green <green@moxielogic.com>2014-12-24 08:38:09 -0500
commited4fd7b7f30020dfdcd79cfd1e36672395f905d7 (patch)
tree6af047d7b04c65fc95b4bed0c2d0aed9040aa2c5
parent0be40ae409724495a434de404bda39c53bb167a0 (diff)
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Add support for moxie's mul.x and umul.x instructions
-rw-r--r--sim/moxie/ChangeLog4
-rw-r--r--sim/moxie/interp.c26
2 files changed, 28 insertions, 2 deletions
diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog
index d3331c6..561e8c8 100644
--- a/sim/moxie/ChangeLog
+++ b/sim/moxie/ChangeLog
@@ -1,3 +1,7 @@
+2014-12-24 Anthony Green <green@moxielogic.com>
+
+ * interp.c (sim_resume): Add mul.x and umul.x instructions.
+
2014-12-12 Anthony Green <green@moxielogic.com>
* interp.c (sim_resume): Add zex instructions.
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index fdb6528..fdd94af 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -622,8 +622,30 @@ sim_resume (sd, step, siggnal)
cpu.asregs.regs[a] = (int) bv & 0xffff;
}
break;
- case 0x14: /* bad */
- case 0x15: /* bad */
+ case 0x14: /* mul.x */
+ {
+ int a = (inst >> 4) & 0xf;
+ int b = inst & 0xf;
+ unsigned av = cpu.asregs.regs[a];
+ unsigned bv = cpu.asregs.regs[b];
+ TRACE("mul.x");
+ signed long long r =
+ (signed long long) av * (signed long long) bv;
+ cpu.asregs.regs[a] = r >> 32;
+ }
+ break;
+ case 0x15: /* umul.x */
+ {
+ int a = (inst >> 4) & 0xf;
+ int b = inst & 0xf;
+ unsigned av = cpu.asregs.regs[a];
+ unsigned bv = cpu.asregs.regs[b];
+ TRACE("umul.x");
+ unsigned long long r =
+ (unsigned long long) av * (unsigned long long) bv;
+ cpu.asregs.regs[a] = r >> 32;
+ }
+ break;
case 0x16: /* bad */
case 0x17: /* bad */
case 0x18: /* bad */