* archures.c: Add support for MIPS r5900

	* bfd-in2.h: Add support for MIPS r5900
	* config.bfd: Add support for Sony Playstation 2
	* cpu-mips.c: Add support for MIPS r5900
	* elfxx-mips.c: Add support for MIPS r5900 (extension of r4000)

	* config/tc-mips.c: Add support for MIPS r5900
	Add M_LQ_AB and M_SQ_AB to support large values for instructions lq and sq.
	* config/tc-mips.c (can_swap_branch_p, get_append_method): Detect some conditional short loops to fix a bug on the r5900 by NOP in the branch delay slot.
	* config/tc-mips.c (M_MUL): Support 3 operands in multu on r5900.
	* config/tc-mips.c (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
	* config/tc-mips.c (s_mipsset): Force 32 bit floating point on r5900.
	* configure.in: Detect CPU type when target string contains r5900 (e.g. mips64r5900el-linux-gnu).

	* config/tc-mips.c (mips_ip): Check parameter range of instructions mfps and mtps on r5900.

	* elf/mips.h: Add MIPS machine variant number for r5900 which is compatible with old Playstation 2 software.
	* opcode/mips.h: Add support for r5900 instructions including lq and sq.

	* configure.tgt: Support ELF files for Sony Playstation 2 (for ps2dev and ps2sdk).
	* emulparams/elf32lr5900n32.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI n32.
	* emulparams/elf32lr5900.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI o32.
	* Makefile.am: Add linker scripts for Sony Playstation 2 ELF files.

	* opcodes/mips-dis.c: Add names for CP0 registers of r5900.
	* opcodes/mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for instructions sq and lq.

	* opcodes/mips-opc.c: Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This will confuse less developers and compilers.

29 files changed, 1685 insertions, 191 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index a643721..4e1602b 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,11 @@
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* archures.c (bfd_mach_mips5900): Define.
+	* bfd-in2.h: Regenerate.
+	* config.bfd: Add mips64-ps2-elf and mips-ps2-elf targets.
+	* cpu-mips.c: Add support for MIPS r5900.
+	* elfxx-mips.c: Add support for MIPS r5900 (extension of r4000).
+
 2013-01-03  Nickolai Zeldovich  <nickolai@csail.mit.edu>
 	    Nick Clifton  <nickc@redhat.com>
 
diff --git a/bfd/archures.c b/bfd/archures.c
index c4cefbc..0843f36 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -1,7 +1,7 @@
 /* BFD library support routines for architectures.
    Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
    2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
-   2012 Free Software Foundation, Inc.
+   2012, 2013 Free Software Foundation, Inc.
    Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -161,6 +161,7 @@ DESCRIPTION
 .#define bfd_mach_mips5000		5000
 .#define bfd_mach_mips5400		5400
 .#define bfd_mach_mips5500		5500
+.#define bfd_mach_mips5900		5900
 .#define bfd_mach_mips6000		6000
 .#define bfd_mach_mips7000		7000
 .#define bfd_mach_mips8000		8000
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 82537c1..01f0fa2 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1892,6 +1892,7 @@ enum bfd_architecture
 #define bfd_mach_mips5000              5000
 #define bfd_mach_mips5400              5400
 #define bfd_mach_mips5500              5500
+#define bfd_mach_mips5900              5900
 #define bfd_mach_mips6000              6000
 #define bfd_mach_mips7000              7000
 #define bfd_mach_mips8000              8000
diff --git a/bfd/config.bfd b/bfd/config.bfd
index f72803c..b19abd6 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -974,7 +974,16 @@ case "${targ}" in
     targ_selvecs="bfd_elf32_nlittlemips_vec bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
     want64=true
     ;;
+  mips64*-ps2-elf*)
+    targ_defvec=bfd_elf32_nlittlemips_vec
+    targ_selvecs="bfd_elf32_nlittlemips_vec bfd_elf32_nbigmips_vec bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
+    want64=true
+    ;;
 #endif
+  mips*-ps2-elf*)
+    targ_defvec=bfd_elf32_littlemips_vec
+    targ_selvecs="bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
+    ;;
   mips*-*-irix5*)
     targ_defvec=bfd_elf32_bigmips_vec
     targ_selvecs="bfd_elf32_littlemips_vec ecoff_big_vec ecoff_little_vec"
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index c55cbf0..59a7c16 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -1,6 +1,7 @@
 /* bfd back-end for mips support
    Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001,
-   2002, 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
+   2002, 2003, 2004, 2005, 2007, 2008, 2009, 2013
+   Free Software Foundation, Inc.
    Written by Steve Chamberlain of Cygnus Support.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -75,6 +76,7 @@ enum
   I_mips5000,
   I_mips5400,
   I_mips5500,
+  I_mips5900,
   I_mips6000,
   I_mips7000,
   I_mips8000,
@@ -118,6 +120,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips5000, "mips:5000",      FALSE, NN(I_mips5000)),
   N (64, 64, bfd_mach_mips5400, "mips:5400",      FALSE, NN(I_mips5400)),
   N (64, 64, bfd_mach_mips5500, "mips:5500",      FALSE, NN(I_mips5500)),
+  N (64, 32, bfd_mach_mips5900, "mips:5900",      FALSE, NN(I_mips5900)),
   N (32, 32, bfd_mach_mips6000, "mips:6000",      FALSE, NN(I_mips6000)),
   N (64, 64, bfd_mach_mips7000, "mips:7000",      FALSE, NN(I_mips7000)),
   N (64, 64, bfd_mach_mips8000, "mips:8000",      FALSE, NN(I_mips8000)),
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 4036273..eaeea14 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -1,6 +1,6 @@
 /* MIPS-specific support for ELF
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
+   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
    Free Software Foundation, Inc.
 
    Most of the information added by Ian Lance Taylor, Cygnus Support,
@@ -6294,6 +6294,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_5500:
       return bfd_mach_mips5500;
 
+    case E_MIPS_MACH_5900:
+      return bfd_mach_mips5900;
+
     case E_MIPS_MACH_9000:
       return bfd_mach_mips9000;
 
@@ -11026,6 +11029,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_4 | E_MIPS_MACH_5500;
       break;
 
+    case bfd_mach_mips5900:
+      val = E_MIPS_ARCH_3 | E_MIPS_MACH_5900;
+      break;
+
     case bfd_mach_mips9000:
       val = E_MIPS_ARCH_4 | E_MIPS_MACH_9000;
       break;
@@ -13708,6 +13715,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = {
   { bfd_mach_mips4300, bfd_mach_mips4000 },
   { bfd_mach_mips4100, bfd_mach_mips4000 },
   { bfd_mach_mips4010, bfd_mach_mips4000 },
+  { bfd_mach_mips5900, bfd_mach_mips4000 },
 
   /* MIPS32 extensions.  */
   { bfd_mach_mipsisa32r2, bfd_mach_mipsisa32 },
diff --git a/gas/ChangeLog b/gas/ChangeLog
index a8e3b6a..c78139c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,19 @@
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* config/tc-mips.c: Add support for MIPS r5900.
+	Add M_LQ_AB and M_SQ_AB to support large values for instructions
+	lq and sq.
+	(can_swap_branch_p, get_append_method): Detect some conditional
+	short loops to fix a bug on the r5900 by NOP in the branch delay
+	slot.
+	(M_MUL): Support 3 operands in multu on r5900.
+	(M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
+	(s_mipsset): Force 32 bit floating point on r5900.
+	(mips_ip): Check parameter range of instructions mfps and mtps on
+	r5900.
+	* configure.in: Detect CPU type when target string contains r5900
+	(e.g. mips64r5900el-linux-gnu).
+
 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* as.c (parse_args): Update copyright year to 2013.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 0372b7a..2d8639c 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1,6 +1,6 @@
 /* tc-mips.c -- assemble code for a MIPS chip.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
+   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
    Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
@@ -171,6 +171,10 @@ struct mips_cl_insn
 
   /* True if this instruction is complete.  */
   unsigned int complete_p : 1;
+
+  /* True if this instruction is cleared from history by unconditional
+     branch.  */
+  unsigned int cleared_p : 1;
 };
 
 /* The ABI to use.  */
@@ -518,6 +522,7 @@ static int mips_32bitmode = 0;
    || mips_opts.isa == ISA_MIPS64                     \
    || mips_opts.isa == ISA_MIPS64R2                   \
    || mips_opts.arch == CPU_R4010                     \
+   || mips_opts.arch == CPU_R5900                     \
    || mips_opts.arch == CPU_R10000                    \
    || mips_opts.arch == CPU_R12000                    \
    || mips_opts.arch == CPU_R14000                    \
@@ -535,6 +540,7 @@ static int mips_32bitmode = 0;
 #define gpr_interlocks                                \
   (mips_opts.isa != ISA_MIPS1                         \
    || mips_opts.arch == CPU_R3900                     \
+   || mips_opts.arch == CPU_R5900                     \
    || mips_opts.micromips                             \
    )
 
@@ -1679,6 +1685,7 @@ create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
   insn->noreorder_p = (mips_opts.noreorder > 0);
   insn->mips16_absolute_jump_p = 0;
   insn->complete_p = 0;
+  insn->cleared_p = 0;
 }
 
 /* Record the current MIPS16/microMIPS mode in now_seg.  */
@@ -3735,10 +3742,13 @@ fix_loongson2f (struct mips_cl_insn * ip)
 
 /* IP is a branch that has a delay slot, and we need to fill it
    automatically.   Return true if we can do that by swapping IP
-   with the previous instruction.  */
+   with the previous instruction.
+   ADDRESS_EXPR is an operand of the instruction to be used with
+   RELOC_TYPE.  */
 
 static bfd_boolean
-can_swap_branch_p (struct mips_cl_insn *ip)
+can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
+  bfd_reloc_code_real_type *reloc_type)
 {
   unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
   unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
@@ -3857,13 +3867,64 @@ can_swap_branch_p (struct mips_cl_insn *ip)
       && insn_length (history) != 4)
     return FALSE;
 
+  /* On R5900 short loops need to be fixed by inserting a nop in
+     the branch delay slots.
+     A short loop can be terminated too early.  */
+  if (mips_opts.arch == CPU_R5900
+      /* Check if instruction has a parameter, ignore "j $31". */
+      && (address_expr != NULL)
+      /* Parameter must be 16 bit. */
+      && (*reloc_type == BFD_RELOC_16_PCREL_S2)
+      /* Branch to same segment. */
+      && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
+      /* Branch to same code fragment. */
+      && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
+      /* Can only calculate branch offset if value is known. */
+      && symbol_constant_p(address_expr->X_add_symbol)
+      /* Check if branch is really conditional. */
+      && !((ip->insn_opcode & 0xffff0000) == 0x10000000   /* beq $0,$0 */
+	|| (ip->insn_opcode & 0xffff0000) == 0x04010000   /* bgez $0 */
+	|| (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
+    {
+      int distance;
+      /* Check if loop is shorter than 6 instructions including
+         branch and delay slot.  */
+      distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
+      if (distance <= 20)
+        {
+          int i;
+          int rv;
+
+          rv = FALSE;
+          /* When the loop includes branches or jumps,
+             it is not a short loop. */
+          for (i = 0; i < (distance / 4); i++)
+            {
+              if ((history[i].cleared_p)
+                  || delayed_branch_p(&history[i]))
+                {
+                  rv = TRUE;
+                  break;
+                }
+            }
+          if (rv == FALSE)
+            {
+              /* Insert nop after branch to fix short loop. */
+              return FALSE;
+            }
+        }
+    }
+
   return TRUE;
 }
 
-/* Decide how we should add IP to the instruction stream.  */
+/* Decide how we should add IP to the instruction stream.
+   ADDRESS_EXPR is an operand of the instruction to be used with
+   RELOC_TYPE.  */
 
 static enum append_method
-get_append_method (struct mips_cl_insn *ip)
+get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
+  bfd_reloc_code_real_type *reloc_type)
 {
   unsigned long pinfo;
 
@@ -3879,7 +3940,8 @@ get_append_method (struct mips_cl_insn *ip)
   /* Otherwise, it's our responsibility to fill branch delay slots.  */
   if (delayed_branch_p (ip))
     {
-      if (!branch_likely_p (ip) && can_swap_branch_p (ip))
+      if (!branch_likely_p (ip)
+	  && can_swap_branch_p (ip, address_expr, reloc_type))
 	return APPEND_SWAP;
 
       pinfo = ip->insn_mo->pinfo;
@@ -4260,7 +4322,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	}
     }
 
-  method = get_append_method (ip);
+  method = get_append_method (ip, address_expr, reloc_type);
   branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
 
 #ifdef OBJ_ELF
@@ -4578,8 +4640,17 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
   /* If we have just completed an unconditional branch, clear the history.  */
   if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
       || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
+    {
+      unsigned int i;
+
     mips_no_prev_insn ();
 
+      for (i = 0; i < ARRAY_SIZE (history); i++)
+      {
+        history[i].cleared_p = 1;
+      }
+    }
+
   /* We need to emit a label at the end of branch-likely macros.  */
   if (emit_branch_likely_macro)
     {
@@ -4591,7 +4662,8 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
   mips_clear_insn_labels ();
 }
 
-/* Forget that there was any previous instruction or label.  */
+/* Forget that there was any previous instruction or label.
+   When BRANCH is true, the branch history is also flushed.  */
 
 static void
 mips_no_prev_insn (void)
@@ -8858,7 +8930,8 @@ macro (struct mips_cl_insn *ip)
       s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
       if (strcmp (s, ".lit8") == 0)
 	{
-	  if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+	  if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+	    && (mips_opts.arch != CPU_R5900))
 	    {
 	      macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
 			   BFD_RELOC_MIPS_LITERAL, mips_gp_register);
@@ -8881,7 +8954,8 @@ macro (struct mips_cl_insn *ip)
 	      macro_build_lui (&offset_expr, AT);
 	    }
 
-	  if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+	  if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+	    && (mips_opts.arch != CPU_R5900))
 	    {
 	      macro_build (&offset_expr, "ldc1", "T,o(b)",
 			   treg, BFD_RELOC_LO16, AT);
@@ -8898,7 +8972,8 @@ macro (struct mips_cl_insn *ip)
       r = BFD_RELOC_LO16;
     dob:
       gas_assert (!mips_opts.micromips);
-      gas_assert (mips_opts.isa == ISA_MIPS1);
+      gas_assert ((mips_opts.isa == ISA_MIPS1)
+        || (mips_opts.arch == CPU_R5900));
       macro_build (&offset_expr, "lwc1", "T,o(b)",
 		   target_big_endian ? treg + 1 : treg, r, breg);
       /* FIXME: A possible overflow which I don't know how to deal
@@ -8936,7 +9011,7 @@ macro (struct mips_cl_insn *ip)
       /* Itbl support may require additional care here.  */
       coproc = 1;
       fmt = "T,o(b)";
-      if (mips_opts.isa != ISA_MIPS1)
+      if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
 	{
 	  s = "ldc1";
 	  goto ld_st;
@@ -8949,7 +9024,7 @@ macro (struct mips_cl_insn *ip)
       /* Itbl support may require additional care here.  */
       coproc = 1;
       fmt = "T,o(b)";
-      if (mips_opts.isa != ISA_MIPS1)
+      if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
 	{
 	  s = "sdc1";
 	  goto ld_st;
@@ -8957,6 +9032,16 @@ macro (struct mips_cl_insn *ip)
       s = "swc1";
       goto ldd_std;
 
+    case M_LQ_AB:
+      fmt = "t,o(b)";
+      s = "lq";
+      goto ld;
+
+    case M_SQ_AB:
+      fmt = "t,o(b)";
+      s = "sq";
+      goto ld_st;
+
     case M_LD_AB:
       fmt = "t,o(b)";
       if (HAVE_64BIT_GPRS)
@@ -9269,8 +9354,15 @@ macro (struct mips_cl_insn *ip)
     case M_DMUL:
       dbl = 1;
     case M_MUL:
+      if (mips_opts.arch == CPU_R5900)
+        {
+          macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
+        }
+      else
+        {
       macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
       macro_build (NULL, "mflo", MFHL_FMT, dreg);
+        }
       break;
 
     case M_DMUL_I:
@@ -9833,7 +9925,7 @@ macro (struct mips_cl_insn *ip)
     case M_TRUNCWS:
     case M_TRUNCWD:
       gas_assert (!mips_opts.micromips);
-      gas_assert (mips_opts.isa == ISA_MIPS1);
+      gas_assert ((mips_opts.isa == ISA_MIPS1) || (mips_opts.arch == CPU_R5900));
       used_at = 1;
       sreg = (ip->insn_opcode >> 11) & 0x1f;	/* floating reg */
       dreg = (ip->insn_opcode >> 06) & 0x1f;	/* floating reg */
@@ -10638,7 +10730,7 @@ mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
     /* Let a macro pass, we'll catch it later when it is expanded.  */
     return 1;
 
-  if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
+  if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
     {
       /* Allow odd registers for single-precision ops.  */
       switch (insn->pinfo & (FP_S | FP_D))
@@ -11789,6 +11881,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
 		as_warn (_("Invalid performance register (%lu)"),
 			 (unsigned long) imm_expr.X_add_number);
+	      if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
+	        && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
+	        as_warn (_("Invalid performance register (%lu)"),
+	          (unsigned long) imm_expr.X_add_number);
 	      INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
@@ -16380,7 +16476,14 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 	case ISA_MIPS64:
 	case ISA_MIPS64R2:
 	  mips_opts.gp32 = 0;
+	  if (mips_opts.arch == CPU_R5900)
+	    {
+		mips_opts.fp32 = 1;
+	    }
+	  else
+	    {
 	  mips_opts.fp32 = 0;
+	    }
 	  break;
 	default:
 	  as_bad (_("unknown ISA level %s"), name + 4);
@@ -19082,6 +19185,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "r4600",          0,			ISA_MIPS3,      CPU_R4600 },
   { "orion",          0,			ISA_MIPS3,      CPU_R4600 },
   { "r4650",          0,			ISA_MIPS3,      CPU_R4650 },
+  { "r5900",          0,			ISA_MIPS3,      CPU_R5900 },
   /* ST Microelectronics Loongson 2E and 2F cores */
   { "loongson2e",     0,			ISA_MIPS3,   CPU_LOONGSON_2E },
   { "loongson2f",     0,			ISA_MIPS3,   CPU_LOONGSON_2F },
diff --git a/gas/configure b/gas/configure
index cd9e5a4..382f8d3 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12060,6 +12060,9 @@ _ACEOF
 	  mips64* | mipsisa64* | mipsisa32*)
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
 	    ;;
+	  mips*)
+	    mips_cpu=`echo $target_cpu | sed -e 's/^mips//' -e 's/el$//'`
+	    ;;
 	  *)
 	    as_fn_error "$target_cpu isn't a supported MIPS CPU name" "$LINENO" 5
 	    ;;
diff --git a/gas/configure.in b/gas/configure.in
index a795d0d..88cbff8c 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -3,7 +3,7 @@ dnl
 dnl And be careful when changing it!  If you must add tests with square
 dnl brackets, be sure changequote invocations surround it.
 dnl
-dnl   Copyright 2012 Free Software Foundation
+dnl   Copyright 2012, 2013 Free Software Foundation
 dnl
 dnl This file is free software; you can redistribute it and/or modify
 dnl it under the terms of the GNU General Public License as published by
@@ -247,6 +247,11 @@ changequote(,)dnl
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
 changequote([,])dnl
 	    ;;
+	  mips*)
+changequote(,)dnl
+	    mips_cpu=`echo $target_cpu | sed -e 's/^mips//' -e 's/el$//'`
+changequote([,])dnl
+	    ;;
 	  *)
 	    AC_MSG_ERROR($target_cpu isn't a supported MIPS CPU name)
 	    ;;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 3cc89a6..0cb2856 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* gas/mips/r5900-full.s: New test.
+	* gas/mips/r5900-full.d: Expected disassembly.
+	* gas/mips/r5900.s: New test.
+	* gas/mips/r5900.d: Expected disassembly.
+	* gas/mips/mips.exp: Run new tests.
+
 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 
 	* gas/aarch64/int-insns.d: Update.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 87637a7..8de1cad 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1,4 +1,4 @@
-# Copyright 2012
+# Copyright 2012, 2013
 # Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
@@ -88,6 +88,9 @@
 #		The architecture provides 32- or 64-bit General Purpose
 #		Registers.
 #
+#	singlefloat
+#		The CPU is 64 bit, but only supports 32 bit FPU.
+#
 # as_flags: The assembler flags used when assembling tests for this
 # architecture.
 #
@@ -460,6 +463,9 @@ mips_arch_create octeon2 64	octeonp {} \
 			{ }
 mips_arch_create xlr 	64	mips64	{} \
 			{ -march=xlr -mtune=xlr } { -mmips:xlr }
+mips_arch_create r5900 	64	mips3	{ gpr_ilocks singlefloat } \
+			{ -march=r5900 -mtune=r5900 } { -mmips:5900 } \
+			{ mipsr5900el-*-* mips64r5900el-*-* }
 
 #
 # And now begin the actual tests!  VxWorks uses RELA rather than REL
@@ -563,13 +569,13 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "24k-triple-stores-3" \
 					[mips_arch_list_matching mips2]
     run_dump_test_arches "24k-triple-stores-4" \
-					[mips_arch_list_matching mips2]
+					[mips_arch_list_matching mips2 !singlefloat]
     run_dump_test_arches "24k-triple-stores-5" \
 					[mips_arch_list_matching mips1]
     run_dump_test_arches "24k-triple-stores-6" \
-					[mips_arch_list_matching mips2]
+					[mips_arch_list_matching mips2 !singlefloat]
     run_dump_test_arches "24k-triple-stores-7" \
-					[mips_arch_list_matching mips2]
+					[mips_arch_list_matching mips2 !singlefloat]
     run_dump_test_arches "24k-triple-stores-8" \
 					[mips_arch_list_matching mips1]
     run_dump_test_arches "24k-triple-stores-9" \
@@ -618,18 +624,18 @@ if { [istarget mips*-*-vxworks*] } {
 	run_dump_test_arches "sd"	[mips_arch_list_matching mips1]
 	run_dump_test_arches "sd-forward" \
 					[mips_arch_list_matching mips1]
-	run_dump_test_arches "l_d"	[mips_arch_list_matching mips1]
+	run_dump_test_arches "l_d"	[mips_arch_list_matching mips1 !singlefloat]
 	run_dump_test_arches "l_d-forward" \
-					[mips_arch_list_matching mips1]
-	run_dump_test_arches "s_d"	[mips_arch_list_matching mips1]
+					[mips_arch_list_matching mips1 !singlefloat]
+	run_dump_test_arches "s_d"	[mips_arch_list_matching mips1 !singlefloat]
 	run_dump_test_arches "s_d-forward" \
-					[mips_arch_list_matching mips1]
-	run_dump_test_arches "ldc1"	[mips_arch_list_matching mips2]
+					[mips_arch_list_matching mips1 !singlefloat]
+	run_dump_test_arches "ldc1"	[mips_arch_list_matching mips2 !singlefloat]
 	run_dump_test_arches "ldc1-forward" \
-					[mips_arch_list_matching mips2]
-	run_dump_test_arches "sdc1"	[mips_arch_list_matching mips2]
+					[mips_arch_list_matching mips2 !singlefloat]
+	run_dump_test_arches "sdc1"	[mips_arch_list_matching mips2 !singlefloat]
 	run_dump_test_arches "sdc1-forward" \
-					[mips_arch_list_matching mips2]
+					[mips_arch_list_matching mips2 !singlefloat]
 	if $has_newabi {
 	    run_dump_test_arches "ld-n32" \
 					[mips_arch_list_matching mips3]
@@ -640,21 +646,21 @@ if { [istarget mips*-*-vxworks*] } {
 	    run_dump_test_arches "sd-forward-n32" \
 					[mips_arch_list_matching mips3]
 	    run_dump_test_arches "l_d-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "l_d-forward-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "s_d-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "s_d-forward-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "ldc1-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "ldc1-forward-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "sdc1-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "sdc1-forward-n32" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "ld-n64" \
 					[mips_arch_list_matching mips3]
 	    run_dump_test_arches "ld-forward-n64" \
@@ -664,21 +670,21 @@ if { [istarget mips*-*-vxworks*] } {
 	    run_dump_test_arches "sd-forward-n64" \
 					[mips_arch_list_matching mips3]
 	    run_dump_test_arches "l_d-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "l_d-forward-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "s_d-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "s_d-forward-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "ldc1-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "ldc1-forward-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "sdc1-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	    run_dump_test_arches "sdc1-forward-n64" \
-					[mips_arch_list_matching mips3]
+					[mips_arch_list_matching mips3 !singlefloat]
 	}
     }
     if $elf { run_dump_test "ld-svr4pic" }
@@ -876,7 +882,7 @@ if { [istarget mips*-*-vxworks*] } {
   	run_dump_test "mips-abi32-pic2"
 
 	run_dump_test "elf${el}-rel"
-	run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64]
+	run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64 !singlefloat]
 	run_dump_test "e32${el}-rel2"
 	run_dump_test "elf${el}-rel3"
 	run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64]
@@ -1096,10 +1102,10 @@ if { [istarget mips*-*-vxworks*] } {
 
     run_list_test_arches "mips-hard-float-flag" \
 	"-32 -msoft-float -mhard-float" \
-					[mips_arch_list_matching mips1]
+					[mips_arch_list_matching mips1 !singlefloat]
     run_list_test_arches "mips-double-float-flag" \
 	"-32 -msingle-float -mdouble-float" \
-					[mips_arch_list_matching mips1]
+					[mips_arch_list_matching mips1 !singlefloat]
 
     run_dump_test "mips16-vis-1"
     run_dump_test "call-nonpic-1"
@@ -1148,4 +1154,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "lui"		[mips_arch_list_matching mips1]
     run_list_test_arches "lui-1" "-32"	[mips_arch_list_matching mips1]
     run_list_test_arches "lui-2" "-32"	[mips_arch_list_matching mips1]
+
+    run_dump_test "r5900"
+    run_dump_test "r5900-full"
 }
diff --git a/gas/testsuite/gas/mips/r5900-full.d b/gas/testsuite/gas/mips/r5900-full.d
new file mode 100644
index 0000000..b3cc442
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900-full.d
@@ -0,0 +1,349 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric -mmips:5900
+#name: Full MIPS R5900
+#as: -march=r5900 -mtune=r5900
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 001f0020 	add	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430820 	add	\$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f820 	add	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 201f0000 	addi	\$31,\$0,0
+[0-9a-f]+ <[^>]*> 21410003 	addi	\$1,\$10,3
+[0-9a-f]+ <[^>]*> 23e0ffff 	addi	\$0,\$31,-1
+[0-9a-f]+ <[^>]*> 241f0000 	li	\$31,0
+[0-9a-f]+ <[^>]*> 25410003 	addiu	\$1,\$10,3
+[0-9a-f]+ <[^>]*> 241fffff 	li	\$31,-1
+[0-9a-f]+ <[^>]*> 001f0024 	and	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430824 	and	\$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f824 	and	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 301f0000 	andi	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 31410003 	andi	\$1,\$10,0x3
+[0-9a-f]+ <[^>]*> 33e0ffff 	andi	\$0,\$31,0xffff
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 461f0018 	adda\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f818 	adda\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0034 	c\.lt\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f834 	c\.lt\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0036 	c\.le\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f836 	c\.le\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0032 	c\.eq\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f832 	c\.eq\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0030 	c\.f\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f830 	c\.f\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 4600f824 	trunc\.w\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 460007e4 	trunc\.w\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 42000039 	di
+[0-9a-f]+ <[^>]*> 42000038 	ei
+[0-9a-f]+ <[^>]*> 703f001a 	div1	\$0,\$1,\$31
+[0-9a-f]+ <[^>]*> 73e1001a 	div1	\$0,\$31,\$1
+[0-9a-f]+ <[^>]*> 703f001b 	divu1	\$0,\$1,\$31
+[0-9a-f]+ <[^>]*> 73e1001b 	divu1	\$0,\$31,\$1
+[0-9a-f]+ <[^>]*> 7c000000 	sq	\$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 7c217fff 	sq	\$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 7d088000 	sq	\$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7fffffff 	sq	\$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 78000000 	lq	\$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 78217fff 	lq	\$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 79088000 	lq	\$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7bffffff 	lq	\$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> cc000000 	pref	0x0,0\(\$0\)
+[0-9a-f]+ <[^>]*> cc217fff 	pref	0x1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> cd088000 	pref	0x8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> cfffffff 	pref	0x1f,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 4600f81c 	madd\.s	\$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07dc 	madd\.s	\$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 701f0021 	maddu1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00021 	maddu1	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0021 	maddu1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f821 	maddu1	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0020 	madd1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00020 	madd1	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0020 	madd1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f820 	madd1	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 461f001e 	madda\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f81e 	madda\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 4600f828 	max\.s	\$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07e8 	max\.s	\$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f829 	min\.s	\$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07e9 	min\.s	\$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 401fc801 	mfpc	\$31,0
+[0-9a-f]+ <[^>]*> 4000c803 	mfpc	\$0,1
+[0-9a-f]+ <[^>]*> 4000c800 	mfps	\$0,0
+[0-9a-f]+ <[^>]*> 401fc800 	mfps	\$31,0
+[0-9a-f]+ <[^>]*> 409fc801 	mtpc	\$31,0
+[0-9a-f]+ <[^>]*> 4080c803 	mtpc	\$0,1
+[0-9a-f]+ <[^>]*> 4080c800 	mtps	\$0,0
+[0-9a-f]+ <[^>]*> 409fc800 	mtps	\$31,0
+[0-9a-f]+ <[^>]*> 4000c000 	mfbpc	\$0
+[0-9a-f]+ <[^>]*> 401fc000 	mfbpc	\$31
+[0-9a-f]+ <[^>]*> 4080c000 	mtbpc	\$0
+[0-9a-f]+ <[^>]*> 409fc000 	mtbpc	\$31
+[0-9a-f]+ <[^>]*> 4000c004 	mfdab	\$0
+[0-9a-f]+ <[^>]*> 401fc004 	mfdab	\$31
+[0-9a-f]+ <[^>]*> 4080c004 	mtdab	\$0
+[0-9a-f]+ <[^>]*> 409fc004 	mtdab	\$31
+[0-9a-f]+ <[^>]*> 4000c005 	mfdabm	\$0
+[0-9a-f]+ <[^>]*> 401fc005 	mfdabm	\$31
+[0-9a-f]+ <[^>]*> 4080c005 	mtdabm	\$0
+[0-9a-f]+ <[^>]*> 409fc005 	mtdabm	\$31
+[0-9a-f]+ <[^>]*> 4000c006 	mfdvb	\$0
+[0-9a-f]+ <[^>]*> 401fc006 	mfdvb	\$31
+[0-9a-f]+ <[^>]*> 4080c006 	mtdvb	\$0
+[0-9a-f]+ <[^>]*> 409fc006 	mtdvb	\$31
+[0-9a-f]+ <[^>]*> 4000c007 	mfdvbm	\$0
+[0-9a-f]+ <[^>]*> 401fc007 	mfdvbm	\$31
+[0-9a-f]+ <[^>]*> 4080c007 	mtdvbm	\$0
+[0-9a-f]+ <[^>]*> 409fc007 	mtdvbm	\$31
+[0-9a-f]+ <[^>]*> 4000c002 	mfiab	\$0
+[0-9a-f]+ <[^>]*> 401fc002 	mfiab	\$31
+[0-9a-f]+ <[^>]*> 4080c002 	mtiab	\$0
+[0-9a-f]+ <[^>]*> 409fc002 	mtiab	\$31
+[0-9a-f]+ <[^>]*> 4000c003 	mfiabm	\$0
+[0-9a-f]+ <[^>]*> 401fc003 	mfiabm	\$31
+[0-9a-f]+ <[^>]*> 4080c003 	mtiabm	\$0
+[0-9a-f]+ <[^>]*> 409fc003 	mtiabm	\$31
+[0-9a-f]+ <[^>]*> 70000010 	mfhi1	\$0
+[0-9a-f]+ <[^>]*> 7000f810 	mfhi1	\$31
+[0-9a-f]+ <[^>]*> 70000011 	mthi1	\$0
+[0-9a-f]+ <[^>]*> 73e00011 	mthi1	\$31
+[0-9a-f]+ <[^>]*> 70000012 	mflo1	\$0
+[0-9a-f]+ <[^>]*> 7000f812 	mflo1	\$31
+[0-9a-f]+ <[^>]*> 70000013 	mtlo1	\$0
+[0-9a-f]+ <[^>]*> 73e00013 	mtlo1	\$31
+[0-9a-f]+ <[^>]*> 00000028 	mfsa	\$0
+[0-9a-f]+ <[^>]*> 0000f828 	mfsa	\$31
+[0-9a-f]+ <[^>]*> 00000029 	mtsa	\$0
+[0-9a-f]+ <[^>]*> 03e00029 	mtsa	\$31
+[0-9a-f]+ <[^>]*> 0418ffff 	mtsab	\$0,-1
+[0-9a-f]+ <[^>]*> 05188000 	mtsab	\$8,-32768
+[0-9a-f]+ <[^>]*> 05187fff 	mtsab	\$8,32767
+[0-9a-f]+ <[^>]*> 07f80000 	mtsab	\$31,0
+[0-9a-f]+ <[^>]*> 0419ffff 	mtsah	\$0,-1
+[0-9a-f]+ <[^>]*> 05198000 	mtsah	\$8,-32768
+[0-9a-f]+ <[^>]*> 05197fff 	mtsah	\$8,32767
+[0-9a-f]+ <[^>]*> 07f90000 	mtsah	\$31,0
+[0-9a-f]+ <[^>]*> 001f000b 	movn	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80b 	movn	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f000a 	movz	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80a 	movz	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 4600f81d 	msub\.s	\$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07dd 	msub\.s	\$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 461f001f 	msuba\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f81f 	msuba\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f001a 	mula\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f81a 	mula\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 701f0018 	mult1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f818 	mult1	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0018 	mult1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00018 	mult1	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0019 	multu1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f819 	multu1	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0019 	multu1	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00019 	multu1	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06e8 	qfsrv	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fee8 	qfsrv	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 4600f816 	rsqrt\.s	\$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07d6 	rsqrt\.s	\$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 461f0019 	suba\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f819 	suba\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 701f0168 	pabsh	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f968 	pabsh	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0068 	pabsw	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f868 	pabsw	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0208 	paddb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa08 	paddb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0108 	paddh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f908 	paddh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0608 	paddsb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe08 	paddsb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0508 	paddsh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd08 	paddsh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0408 	paddsw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc08 	paddsw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0628 	paddub	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe28 	paddub	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0528 	padduh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd28 	padduh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0428 	padduw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc28 	padduw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0008 	paddw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f808 	paddw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0128 	padsbh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f928 	padsbh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0489 	pand	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc89 	pand	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f02a8 	pceqb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0faa8 	pceqb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f01a8 	pceqh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f9a8 	pceqh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00a8 	pceqw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa88 	pcgtb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00a8 	pceqw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f8a8 	pceqw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0288 	pcgtb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa88 	pcgtb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0188 	pcgth	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f988 	pcgth	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0088 	pcgtw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f888 	pcgtw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06e9 	pcpyh	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000fee9 	pcpyh	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0389 	pcpyld	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb89 	pcpyld	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f03a9 	pcpyud	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fba9 	pcpyud	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0749 	pdivbw	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00749 	pdivbw	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0369 	pdivuw	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00369 	pdivuw	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0349 	pdivw	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00349 	pdivw	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06a9 	pexch	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000fea9 	pexch	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f07a9 	pexcw	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000ffa9 	pexcw	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0689 	pexeh	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000fe89 	pexeh	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0789 	pexew	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000ff89 	pexew	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0788 	pext5	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000ff88 	pext5	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0688 	pextlb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe88 	pextlb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0588 	pextlh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd88 	pextlh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0488 	pextlw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc88 	pextlw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06a8 	pextub	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fea8 	pextub	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f05a8 	pextuh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fda8 	pextuh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04a8 	pextuw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fca8 	pextuw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0449 	phmadh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc49 	phmadh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0549 	phmsbh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd49 	phmsbh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f02a9 	pinteh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0faa9 	pinteh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0289 	pinth	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa89 	pinth	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e00004 	plzcw	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f804 	plzcw	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0409 	pmaddh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc09 	pmaddh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0029 	pmadduw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f829 	pmadduw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0009 	pmaddw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f809 	pmaddw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f01c8 	pmaxh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f9c8 	pmaxh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00c8 	pmaxw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f8c8 	pmaxw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 70000209 	pmfhi	\$0
+[0-9a-f]+ <[^>]*> 7000fa09 	pmfhi	\$31
+[0-9a-f]+ <[^>]*> 700000f0 	pmfhl\.lh	\$0
+[0-9a-f]+ <[^>]*> 7000f8f0 	pmfhl\.lh	\$31
+[0-9a-f]+ <[^>]*> 70000030 	pmfhl\.lw	\$0
+[0-9a-f]+ <[^>]*> 7000f830 	pmfhl\.lw	\$31
+[0-9a-f]+ <[^>]*> 70000130 	pmfhl\.sh	\$0
+[0-9a-f]+ <[^>]*> 7000f930 	pmfhl\.sh	\$31
+[0-9a-f]+ <[^>]*> 700000b0 	pmfhl\.slw	\$0
+[0-9a-f]+ <[^>]*> 7000f8b0 	pmfhl\.slw	\$31
+[0-9a-f]+ <[^>]*> 70000070 	pmfhl\.uw	\$0
+[0-9a-f]+ <[^>]*> 7000f870 	pmfhl\.uw	\$31
+[0-9a-f]+ <[^>]*> 70000249 	pmflo	\$0
+[0-9a-f]+ <[^>]*> 7000fa49 	pmflo	\$31
+[0-9a-f]+ <[^>]*> 701f01e8 	pminh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f9e8 	pminh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00e8 	pminw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f8e8 	pminw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0509 	pmsubh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd09 	pmsubh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0109 	pmsubw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f909 	pmsubw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 70000229 	pmthi	\$0
+[0-9a-f]+ <[^>]*> 73e00229 	pmthi	\$31
+[0-9a-f]+ <[^>]*> 70000031 	pmthl\.lw	\$0
+[0-9a-f]+ <[^>]*> 73e00031 	pmthl\.lw	\$31
+[0-9a-f]+ <[^>]*> 70000269 	pmtlo	\$0
+[0-9a-f]+ <[^>]*> 73e00269 	pmtlo	\$31
+[0-9a-f]+ <[^>]*> 701f0709 	pmulth	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0ff09 	pmulth	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0329 	pmultuw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb29 	pmultuw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0309 	pmultw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb09 	pmultw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0309 	pmultw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb09 	pmultw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04e9 	pnor	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fce9 	pnor	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04a9 	por	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fca9 	por	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f07c8 	ppac5	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000ffc8 	ppac5	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06c8 	ppacb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fec8 	ppacb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f05c8 	ppach	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fdc8 	ppach	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04c8 	ppacw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fcc8 	ppacw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06c9 	prevh	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000fec9 	prevh	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f07c9 	prot3w	\$0,\$31
+[0-9a-f]+ <[^>]*> 7000ffc9 	prot3w	\$31,\$0
+[0-9a-f]+ <[^>]*> 7000f834 	psllh	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07f4 	psllh	\$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f0089 	psllvw	\$0,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e0f889 	psllvw	\$31,\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f83c 	psllw	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07fc 	psllw	\$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 7000f837 	psrah	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07f7 	psrah	\$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f00e9 	psravw	\$0,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e0f8e9 	psravw	\$31,\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f83f 	psraw	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07ff 	psraw	\$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 7000f836 	psrlh	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07f6 	psrlh	\$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f00c9 	psrlvw	\$0,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e0f8c9 	psrlvw	\$31,\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f83e 	psrlw	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07fe 	psrlw	\$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f0248 	psubb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa48 	psubb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0148 	psubh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f948 	psubh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0648 	psubsb	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe48 	psubsb	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0548 	psubsh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd48 	psubsh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0448 	psubsw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc48 	psubsw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0668 	psubub	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe68 	psubub	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0568 	psubuh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd68 	psubuh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0468 	psubuw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc68 	psubuw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0048 	psubw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f848 	psubw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04c9 	pxor	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fcc9 	pxor	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0018 	mult	\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f818 	mult	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 	multu	\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 	multu	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 	multu	\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 	multu	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 	madd	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f800 	madd	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 	madd	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00000 	madd	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 	maddu	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f801 	maddu	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 	maddu	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00001 	maddu	\$31,\$0
+[0-9a-f]+ <[^>]*> 0000000f 	sync
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r5900-full.s b/gas/testsuite/gas/mips/r5900-full.s
new file mode 100644
index 0000000..c0dc20a
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900-full.s
@@ -0,0 +1,421 @@
+	.text
+
+stuff:
+	.ent stuff
+	.set push
+	.set noreorder
+	.set noat
+
+	add $0, $0, $31
+	add $1, $10, $3
+	add $31, $31, $0
+
+	addi $31, $0, 0
+	addi $1, $10, 3
+	addi $0, $31, -1
+
+	addiu $31, $0, 0
+	addiu $1, $10, 3
+	addiu $31, $0, 0xFFFF
+
+	and $0, $0, $31
+	and $1, $10, $3
+	and $31, $31, $0
+
+	andi $31, $0, 0
+	andi $1, $10, 3
+	andi $0, $31, 0xFFFF
+
+	nop
+
+	# Test R5900 specific instructions:
+	adda.s $f0, $f31
+	adda.s $f31, $f0
+
+	# The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I.
+	c.lt.s $f0, $f31
+	c.lt.s $f31, $f0
+
+	# The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I.
+	c.le.s $f0, $f31
+	c.le.s $f31, $f0
+
+	c.eq.s $f0, $f31
+	c.eq.s $f31, $f0
+
+	c.f.s $f0, $f31
+	c.f.s $f31, $f0
+
+	# The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
+	# The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
+	# For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s.
+	# cvt.w.s should not be used on R5900.
+	trunc.w.s $f0, $f31
+	trunc.w.s $f31, $f0
+
+	# Test ei/di, but not the R5900 has a bug. ei/di should not be used.
+	di
+	ei
+
+	# Like div but result is written to lo1 and hi1 registers (pipeline 1).
+	div1 $0, $1, $31
+	div1 $0, $31, $1
+	divu1 $0, $1, $31
+	divu1 $0, $31, $1
+
+	# 128 bit store instruction.
+	sq $0, 0($0)
+	sq $1, 0x7fff($1)
+	sq $8, -0x8000($8)
+	sq $31, -1($31)
+
+	# 128 bit load instruction.
+	lq $0, 0($0)
+	lq $1, 0x7fff($1)
+	lq $8, -0x8000($8)
+	lq $31, -1($31)
+
+	# Prefetch cache
+	pref 0, 0($0)
+	pref 1, 0x7fff($1)
+	pref 8, -0x8000($8)
+	pref 31, -1($31)
+
+	# Floating point multiply-ADD
+	madd.s $f0, $f31, $f0
+	madd.s $f31, $f0, $f31
+
+	# Like maddu, but pipeline 1
+	maddu1 $0, $31
+	maddu1 $31, $0
+	maddu1 $0, $0, $31
+	maddu1 $31, $31, $0
+
+	# Like madd, but pipeline 1
+	madd1 $0, $31
+	madd1 $31, $0
+	madd1 $0, $0, $31
+	madd1 $31, $31, $0
+
+	# Floating point multiply-ADD
+	madda.s $f0, $f31
+	madda.s $f31, $f0
+
+	# Floating point maximum
+	max.s $f0, $f31, $f0
+	max.s $f31, $f0, $f31
+
+	# Floating point minimum
+	min.s $f0, $f31, $f0
+	min.s $f31, $f0, $f31
+
+	# Preformance counter registers
+	mfpc $31, 0
+	mfpc $0, 1
+	mfps $0, 0
+	mfps $31, 0
+	mtpc $31, 0
+	mtpc $0, 1
+	mtps $0, 0
+	mtps $31, 0
+
+	# Brekpoint register
+	mfbpc $0
+	mfbpc $31
+	mtbpc $0
+	mtbpc $31
+	mfdab $0
+	mfdab $31
+	mtdab $0
+	mtdab $31
+	mfdabm $0
+	mfdabm $31
+	mtdabm $0
+	mtdabm $31
+	mfdvb $0
+	mfdvb $31
+	mtdvb $0
+	mtdvb $31
+	mfdvbm $0
+	mfdvbm $31
+	mtdvbm $0
+	mtdvbm $31
+	mfiab $0
+	mfiab $31
+	mtiab $0
+	mtiab $31
+	mfiabm $0
+	mfiabm $31
+	mtiabm $0
+	mtiabm $31
+
+	# Pipeline1
+	mfhi1 $0
+	mfhi1 $31
+	mthi1 $0
+	mthi1 $31
+	mflo1 $0
+	mflo1 $31
+	mtlo1 $0
+	mtlo1 $31
+
+	# Shift amount register
+	mfsa $0
+	mfsa $31
+	mtsa $0
+	mtsa $31
+	mtsab $0, -1
+	mtsab $8, 0x8000
+	mtsab $8, 0x7FFF
+	mtsab $31, 0
+	mtsah $0, -1
+	mtsah $8, 0x8000
+	mtsah $8, 0x7FFF
+	mtsah $31, 0
+
+	movn $0, $0, $31
+	movn $31, $31, $0
+	movz $0, $0, $31
+	movz $31, $31, $0
+
+	# Floating multiply and subtract
+	msub.s $f0, $f31, $f0
+	msub.s $f31, $f0, $f31
+
+	# Floating multiply and subtract from accumulator
+	msuba.s $f0, $f31
+	msuba.s $f31, $f0
+
+	# Floating point multiply to accumulator
+	mula.s $f0, $f31
+	mula.s $f31, $f0
+
+	# Like mult but pipeline 1
+	mult1 $0, $0, $31
+	mult1 $31, $31, $0
+	mult1 $0, $31
+	mult1 $31, $0
+
+	# Like multu but pipeline 1
+	multu1 $0, $0, $31
+	multu1 $31, $31, $0
+	multu1 $0, $31
+	multu1 $31, $0
+
+	# Quadword funnel shift right variable
+	qfsrv $0, $0, $31
+	qfsrv $31, $31, $0
+
+	# Floating point reciprocal squre root
+	rsqrt.s $f0, $f31, $f0
+	rsqrt.s $f31, $f0, $f31
+
+	# FLoating point subtract to accumulator
+	suba.s $f0, $f31
+	suba.s $f31, $f0
+
+	# Parallel instructions operating on 128 bit registers:
+	pabsh $0, $31
+	pabsh $31, $0
+	pabsw $0, $31
+	pabsw $31, $0
+	paddb $0, $0, $31
+	paddb $31, $31, $0
+	paddh $0, $0, $31
+	paddh $31, $31, $0
+	paddsb $0, $0, $31
+	paddsb $31, $31, $0
+	paddsh $0, $0, $31
+	paddsh $31, $31, $0
+	paddsw $0, $0, $31
+	paddsw $31, $31, $0
+	paddub $0, $0, $31
+	paddub $31, $31, $0
+	padduh $0, $0, $31
+	padduh $31, $31, $0
+	padduw $0, $0, $31
+	padduw $31, $31, $0
+	paddw $0, $0, $31
+	paddw $31, $31, $0
+	padsbh $0, $0, $31
+	padsbh $31, $31, $0
+	pand $0, $0, $31
+	pand $31, $31, $0
+	pceqb $0, $0, $31
+	pceqb $31, $31, $0
+	pceqh $0, $0, $31
+	pceqh $31, $31, $0
+	pceqw $0, $0, $31
+	pcgtb $31, $31, $0
+	pceqw $0, $0, $31
+	pceqw $31, $31, $0
+	pcgtb $0, $0, $31
+	pcgtb $31, $31, $0
+	pcgth $0, $0, $31
+	pcgth $31, $31, $0
+	pcgtw $0, $0, $31
+	pcgtw $31, $31, $0
+	pcpyh $0, $31
+	pcpyh $31, $0
+	pcpyld $0, $0, $31
+	pcpyld $31, $31, $0
+	pcpyud $0, $0, $31
+	pcpyud $31, $31, $0
+	pdivbw $0, $31
+	pdivbw $31, $0
+	pdivuw $0, $31
+	pdivuw $31, $0
+	pdivw $0, $31
+	pdivw $31, $0
+	pexch $0, $31
+	pexch $31, $0
+	pexcw $0, $31
+	pexcw $31, $0
+	pexeh $0, $31
+	pexeh $31, $0
+	pexew $0, $31
+	pexew $31, $0
+	pext5 $0, $31
+	pext5 $31, $0
+	pextlb $0, $0, $31
+	pextlb $31, $31, $0
+	pextlh $0, $0, $31
+	pextlh $31, $31, $0
+	pextlw $0, $0, $31
+	pextlw $31, $31, $0
+	pextub $0, $0, $31
+	pextub $31, $31, $0
+	pextuh $0, $0, $31
+	pextuh $31, $31, $0
+	pextuw $0, $0, $31
+	pextuw $31, $31, $0
+	phmadh $0, $0, $31
+	phmadh $31, $31, $0
+	phmsbh $0, $0, $31
+	phmsbh $31, $31, $0
+	pinteh $0, $0, $31
+	pinteh $31, $31, $0
+	pinth $0, $0, $31
+	pinth $31, $31, $0
+	plzcw $0, $31
+	plzcw $31, $0
+	pmaddh $0, $0, $31
+	pmaddh $31, $31, $0
+	pmadduw $0, $0, $31
+	pmadduw $31, $31, $0
+	pmaddw $0, $0, $31
+	pmaddw $31, $31, $0
+	pmaxh $0, $0, $31
+	pmaxh $31, $31, $0
+	pmaxw $0, $0, $31
+	pmaxw $31, $31, $0
+	pmfhi $0
+	pmfhi $31
+	pmfhl.lh $0
+	pmfhl.lh $31
+	pmfhl.lw $0
+	pmfhl.lw $31
+	pmfhl.sh $0
+	pmfhl.sh $31
+	pmfhl.slw $0
+	pmfhl.slw $31
+	pmfhl.uw $0
+	pmfhl.uw $31
+	pmflo $0
+	pmflo $31
+	pminh $0, $0, $31
+	pminh $31, $31, $0
+	pminw $0, $0, $31
+	pminw $31, $31, $0
+	pmsubh $0, $0, $31
+	pmsubh $31, $31, $0
+	pmsubw $0, $0, $31
+	pmsubw $31, $31, $0
+	pmthi $0
+	pmthi $31
+	pmthl.lw $0
+	pmthl.lw $31
+	pmtlo $0
+	pmtlo $31
+	pmulth $0, $0, $31
+	pmulth $31, $31, $0
+	pmultuw $0, $0, $31
+	pmultuw $31, $31, $0
+	pmultw $0, $0, $31
+	pmultw $31, $31, $0
+	pmultw $0, $0, $31
+	pmultw $31, $31, $0
+	pnor $0, $0, $31
+	pnor $31, $31, $0
+	por $0, $0, $31
+	por $31, $31, $0
+	ppac5 $0, $31
+	ppac5 $31, $0
+	ppacb $0, $0, $31
+	ppacb $31, $31, $0
+	ppach $0, $0, $31
+	ppach $31, $31, $0
+	ppacw $0, $0, $31
+	ppacw $31, $31, $0
+	prevh $0, $31
+	prevh $31, $0
+	prot3w $0, $31
+	prot3w $31, $0
+	psllh $31, $0, 0
+	psllh $0, $31, 31
+	psllvw $0, $31, $0
+	psllvw $31, $0, $31
+	psllw $31, $0, 0
+	psllw $0, $31, 31
+	psrah $31, $0, 0
+	psrah $0, $31, 31
+	psravw $0, $31, $0
+	psravw $31, $0, $31
+	psraw $31, $0, 0
+	psraw $0, $31, 31
+	psrlh $31, $0, 0
+	psrlh $0, $31, 31
+	psrlvw $0, $31, $0
+	psrlvw $31, $0, $31
+	psrlw $31, $0, 0
+	psrlw $0, $31, 31
+	psubb $0, $0, $31
+	psubb $31, $31, $0
+	psubh $0, $0, $31
+	psubh $31, $31, $0
+	psubsb $0, $0, $31
+	psubsb $31, $31, $0
+	psubsh $0, $0, $31
+	psubsh $31, $31, $0
+	psubsw $0, $0, $31
+	psubsw $31, $31, $0
+	psubub $0, $0, $31
+	psubub $31, $31, $0
+	psubuh $0, $0, $31
+	psubuh $31, $31, $0
+	psubuw $0, $0, $31
+	psubuw $31, $31, $0
+	psubw $0, $0, $31
+	psubw $31, $31, $0
+	pxor $0, $0, $31
+	pxor $31, $31, $0
+
+	# G1 instructions
+	mult $0, $0, $31
+	mult $31, $31, $0
+	multu $0, $0, $31
+	multu $31, $31, $0
+	mul $0, $0, $31
+	mul $31, $31, $0
+	madd $0, $0, $31
+	madd $31, $31, $0
+	madd $0, $31
+	madd $31, $0
+	maddu $0, $0, $31
+	maddu $31, $31, $0
+	maddu $0, $31
+	maddu $31, $0
+	sync
+
+	.space	8
+	.end stuff
diff --git a/gas/testsuite/gas/mips/r5900.d b/gas/testsuite/gas/mips/r5900.d
new file mode 100644
index 0000000..7ef9a8a
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900.d
@@ -0,0 +1,93 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric -mmips:5900
+#name: MIPS R5900
+#as: -march=r5900 -mtune=r5900
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 001f0020 	add	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430820 	add	\$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f820 	add	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 201f0000 	addi	\$31,\$0,0
+[0-9a-f]+ <[^>]*> 21410003 	addi	\$1,\$10,3
+[0-9a-f]+ <[^>]*> 23e0ffff 	addi	\$0,\$31,-1
+[0-9a-f]+ <[^>]*> 241f0000 	li	\$31,0
+[0-9a-f]+ <[^>]*> 25410003 	addiu	\$1,\$10,3
+[0-9a-f]+ <[^>]*> 241fffff 	li	\$31,-1
+[0-9a-f]+ <[^>]*> 001f0024 	and	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430824 	and	\$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f824 	and	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 301f0000 	andi	\$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 31410003 	andi	\$1,\$10,0x3
+[0-9a-f]+ <[^>]*> 33e0ffff 	andi	\$0,\$31,0xffff
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 461f0034 	c\.lt\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f834 	c\.lt\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0036 	c\.le\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f836 	c\.le\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0032 	c\.eq\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f832 	c\.eq\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0030 	c\.f\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f830 	c\.f\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 4600f824 	trunc\.w\.s	\$f0,\$f31
+[0-9a-f]+ <[^>]*> 460007e4 	trunc\.w\.s	\$f31,\$f0
+[0-9a-f]+ <[^>]*> 7c000000 	sq	\$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 7c217fff 	sq	\$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 7d088000 	sq	\$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7fffffff 	sq	\$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 78000000 	lq	\$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 78217fff 	lq	\$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 79088000 	lq	\$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7bffffff 	lq	\$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> cc000000 	pref	0x0,0\(\$0\)
+[0-9a-f]+ <[^>]*> cc217fff 	pref	0x1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> cd088000 	pref	0x8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> cfffffff 	pref	0x1f,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 401fc801 	mfpc	\$31,0
+[0-9a-f]+ <[^>]*> 4000c803 	mfpc	\$0,1
+[0-9a-f]+ <[^>]*> 4000c800 	mfps	\$0,0
+[0-9a-f]+ <[^>]*> 401fc800 	mfps	\$31,0
+[0-9a-f]+ <[^>]*> 409fc801 	mtpc	\$31,0
+[0-9a-f]+ <[^>]*> 4080c803 	mtpc	\$0,1
+[0-9a-f]+ <[^>]*> 4080c800 	mtps	\$0,0
+[0-9a-f]+ <[^>]*> 409fc800 	mtps	\$31,0
+[0-9a-f]+ <[^>]*> 70000010 	mfhi1	\$0
+[0-9a-f]+ <[^>]*> 7000f810 	mfhi1	\$31
+[0-9a-f]+ <[^>]*> 70000011 	mthi1	\$0
+[0-9a-f]+ <[^>]*> 73e00011 	mthi1	\$31
+[0-9a-f]+ <[^>]*> 70000012 	mflo1	\$0
+[0-9a-f]+ <[^>]*> 7000f812 	mflo1	\$31
+[0-9a-f]+ <[^>]*> 70000013 	mtlo1	\$0
+[0-9a-f]+ <[^>]*> 73e00013 	mtlo1	\$31
+[0-9a-f]+ <[^>]*> 001f000b 	movn	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80b 	movn	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f000a 	movz	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80a 	movz	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0389 	pcpyld	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb89 	pcpyld	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0588 	pextlh	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd88 	pextlh	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0488 	pextlw	\$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc88 	pextlw	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0018 	mult	\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f818 	mult	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 	multu	\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 	multu	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 	multu	\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 	multu	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 	madd	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f800 	madd	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 	madd	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00000 	madd	\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 	maddu	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f801 	maddu	\$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 	maddu	\$0,\$31
+[0-9a-f]+ <[^>]*> 73e00001 	maddu	\$31,\$0
+[0-9a-f]+ <[^>]*> 0000000f 	sync
+[0-9a-f]+ <[^>]*> 2403012c 	li	\$3,300
+[0-9a-f]+ <[^>]*> 2063ffff 	addi	\$3,\$3,-1
+[0-9a-f]+ <[^>]*> 2084ffff 	addi	\$4,\$4,-1
+[0-9a-f]+ <[^>]*> 1460fffd 	bnez	\$3,[0-9a-f]+ <short_loop1>
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 24040003 	li	\$4,3
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/r5900.s b/gas/testsuite/gas/mips/r5900.s
new file mode 100644
index 0000000..022c4ab
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900.s
@@ -0,0 +1,135 @@
+	.text
+
+stuff:
+	.ent stuff
+	.set push
+	.set noreorder
+	.set noat
+
+	add $0, $0, $31
+	add $1, $10, $3
+	add $31, $31, $0
+
+	addi $31, $0, 0
+	addi $1, $10, 3
+	addi $0, $31, -1
+
+	addiu $31, $0, 0
+	addiu $1, $10, 3
+	addiu $31, $0, 0xFFFF
+
+	and $0, $0, $31
+	and $1, $10, $3
+	and $31, $31, $0
+
+	andi $31, $0, 0
+	andi $1, $10, 3
+	andi $0, $31, 0xFFFF
+
+	nop
+
+	# The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I.
+	c.lt.s $f0, $f31
+	c.lt.s $f31, $f0
+
+	# The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I.
+	c.le.s $f0, $f31
+	c.le.s $f31, $f0
+
+	c.eq.s $f0, $f31
+	c.eq.s $f31, $f0
+
+	c.f.s $f0, $f31
+	c.f.s $f31, $f0
+
+	# The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
+	# The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
+	# For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s.
+	# cvt.w.s should not be used on R5900.
+	trunc.w.s $f0, $f31
+	trunc.w.s $f31, $f0
+
+	# 128 bit store instruction.
+	sq $0, 0($0)
+	sq $1, 0x7fff($1)
+	sq $8, -0x8000($8)
+	sq $31, -1($31)
+
+	# 128 bit load instruction.
+	lq $0, 0($0)
+	lq $1, 0x7fff($1)
+	lq $8, -0x8000($8)
+	lq $31, -1($31)
+
+	# Prefetch cache
+	pref 0, 0($0)
+	pref 1, 0x7fff($1)
+	pref 8, -0x8000($8)
+	pref 31, -1($31)
+
+	# Preformance counter registers
+	mfpc $31, 0
+	mfpc $0, 1
+	mfps $0, 0
+	mfps $31, 0
+	mtpc $31, 0
+	mtpc $0, 1
+	mtps $0, 0
+	mtps $31, 0
+
+	# Pipeline1
+	mfhi1 $0
+	mfhi1 $31
+	mthi1 $0
+	mthi1 $31
+	mflo1 $0
+	mflo1 $31
+	mtlo1 $0
+	mtlo1 $31
+
+	movn $0, $0, $31
+	movn $31, $31, $0
+	movz $0, $0, $31
+	movz $31, $31, $0
+
+	# Parallel instructions operating on 128 bit registers:
+	pcpyld $0, $0, $31
+	pcpyld $31, $31, $0
+	pextlh $0, $0, $31
+	pextlh $31, $31, $0
+	pextlw $0, $0, $31
+	pextlw $31, $31, $0
+
+	# G1 instructions
+	mult $0, $0, $31
+	mult $31, $31, $0
+	multu $0, $0, $31
+	multu $31, $31, $0
+	mul $0, $0, $31
+	mul $31, $31, $0
+	madd $0, $0, $31
+	madd $31, $31, $0
+	madd $0, $31
+	madd $31, $0
+	maddu $0, $0, $31
+	maddu $31, $31, $0
+	maddu $0, $31
+	maddu $31, $0
+	sync
+
+	.set pop
+	.set push
+	.set reorder
+	# Short loop fix.
+	li $3, 300
+short_loop1:
+	addi $3, -1
+	addi $4, -1
+	# NOP should be inserted in branch delay.
+	bne $3, $0, short_loop1
+
+	li $4, 3
+	.set pop
+
+	.space	8
+	.end stuff
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 540d0a7..e49c254 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* mips.h: Add MIPS machine variant number for r5900 which is
+	compatible with old Playstation 2 software.
+
 2012-11-16  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* common.h (DF_1_CONLFAT): Renamed to ...
diff --git a/include/elf/mips.h b/include/elf/mips.h
index c2f362e..ca9fdcd 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1,6 +1,6 @@
 /* MIPS ELF support for BFD.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2008, 2009, 2010
+   2003, 2004, 2005, 2008, 2009, 2010, 2013
    Free Software Foundation, Inc.
 
    By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from
@@ -270,6 +270,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_XLR     	0x008c0000
 #define E_MIPS_MACH_OCTEON2	0x008d0000
 #define E_MIPS_MACH_5400	0x00910000
+#define E_MIPS_MACH_5900	0x00920000
 #define E_MIPS_MACH_5500	0x00980000
 #define E_MIPS_MACH_9000	0x00990000
 #define E_MIPS_MACH_LS2E        0x00A00000
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 891a515..90c313a 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* mips.h: Add support for r5900 instructions including lq and sq.
+
 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 
 	* cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 5691ac5..ef81bbe 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1,6 +1,6 @@
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2008, 2009, 2010
+   2003, 2004, 2005, 2008, 2009, 2010, 2013
    Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -732,7 +732,8 @@ static const unsigned int mips_isa_table[] =
 #define INSN_DSP                  0x00001000
 #define INSN_DSP64                0x00002000
 
-/* 0x00004000 is unused.  */
+/* MIPS R5900 instruction */
+#define INSN_5900                 0x00004000
 
 /* MIPS-3D ASE */
 #define INSN_MIPS3D               0x00008000
@@ -811,6 +812,7 @@ static const unsigned int mips_isa_table[] =
 #define CPU_R5000	5000
 #define CPU_VR5400	5400
 #define CPU_VR5500	5500
+#define CPU_R5900	5900
 #define CPU_R6000	6000
 #define CPU_RM7000	7000
 #define CPU_R8000	8000
@@ -876,6 +878,9 @@ cpu_is_member (int cpu, unsigned int mask)
     case CPU_VR5500:
       return (mask & INSN_5500) != 0;
 
+    case CPU_R5900:
+      return (mask & INSN_5900) != 0;
+
     case CPU_LOONGSON_2E:
       return (mask & INSN_LOONGSON_2E) != 0;
 
@@ -1078,6 +1083,7 @@ enum
   M_LL_OB,
   M_LLD_AB,
   M_LLD_OB,
+  M_LQ_AB,
   M_LS_A,
   M_LW_A,
   M_LW_AB,
@@ -1179,6 +1185,7 @@ enum
   M_SB_AB,
   M_SH_A,
   M_SH_AB,
+  M_SQ_AB,
   M_SW_A,
   M_SW_AB,
   M_SWC0_A,
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 1ef5336..cc3b25a 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,14 @@
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* configure.tgt: Support ELF files for Sony Playstation 2 (for
+	ps2dev and ps2sdk).
+	* emulparams/elf32lr5900n32.sh: Create linker script for Sony
+	Playstation 2 ELF files using MIPS ABI n32.
+	* emulparams/elf32lr5900.sh: Create linker script for Sony
+	Playstation 2 ELF files using MIPS ABI o32.
+	* Makefile.am: Add linker scripts for Sony Playstation 2 ELF
+	files.
+
 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* ldver.c (ldversion): Update copyright year to 2013.
diff --git a/ld/Makefile.am b/ld/Makefile.am
index 995e748..22eac64 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -230,6 +230,8 @@ ALL_EMULATION_SOURCES = \
 	eelf32ebmipvxworks.c \
 	eelf32elmip.c \
 	eelf32elmipvxworks.c \
+	eelf32lr5900.c \
+	eelf32lr5900n32.c \
 	eelf32epiphany.c \
 	eelf32epiphany_4x4.c \
 	eelf32fr30.c \
@@ -1041,6 +1043,16 @@ eelf32elmipvxworks.c: $(srcdir)/emulparams/elf32elmipvxworks.sh \
   $(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
   $(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
+eelf32lr5900.c: $(srcdir)/emulparams/elf32lr5900.sh \
+  $(srcdir)/emulparams/elf32bmip.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} elf32lr5900 "$(tdir_elf32lr5900)"
+eelf32lr5900n32.c: $(srcdir)/emulparams/elf32lr5900n32.sh \
+  $(srcdir)/emulparams/elf32bmipn32-defs.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} elf32lr5900n32 "$(tdir_elf32lr5900n32)"
 eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \
   $(ELF_DEPS) ${GEN_DEPENDS}
 	${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)"
diff --git a/ld/Makefile.in b/ld/Makefile.in
index 4e61665..8d68159 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -538,6 +538,8 @@ ALL_EMULATION_SOURCES = \
 	eelf32ebmipvxworks.c \
 	eelf32elmip.c \
 	eelf32elmipvxworks.c \
+	eelf32lr5900.c \
+	eelf32lr5900n32.c \
 	eelf32epiphany.c \
 	eelf32epiphany_4x4.c \
 	eelf32fr30.c \
@@ -1162,6 +1164,8 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ebmipvxworks.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmipvxworks.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32epiphany.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32epiphany_4x4.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32fr30.Po@am__quote@
@@ -2515,6 +2519,16 @@ eelf32elmipvxworks.c: $(srcdir)/emulparams/elf32elmipvxworks.sh \
   $(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
   $(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
+eelf32lr5900.c: $(srcdir)/emulparams/elf32lr5900.sh \
+  $(srcdir)/emulparams/elf32bmip.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} elf32lr5900 "$(tdir_elf32lr5900)"
+eelf32lr5900n32.c: $(srcdir)/emulparams/elf32lr5900n32.sh \
+  $(srcdir)/emulparams/elf32bmipn32-defs.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} elf32lr5900n32 "$(tdir_elf32lr5900n32)"
 eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \
   $(ELF_DEPS) ${GEN_DEPENDS}
 	${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)"
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 61cc346..ea55895 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -1,3 +1,21 @@
+# configure.tgt
+#
+#   Copyright 2013 Free Software Foundation
+#
+# This file is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
 # This is the linker target specific file.  This is invoked by the
 # autoconf generated configure script.  Putting it in a separate shell
 # file lets us skip running autoconf when modifying target specific
@@ -438,6 +456,12 @@ mips*el-sde-elf*)	targ_emul=elf32ltsmip
 mips*-sde-elf* | mips*-mti-elf*)
 			targ_emul=elf32btsmip
 			targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
+mips64*el-ps2-elf*)	targ_emul=elf32lr5900n32
+			targ_extra_emuls="elf32lr5900"
+			targ_extra_libpath=$targ_extra_emuls ;;
+mips*el-ps2-elf*)	targ_emul=elf32lr5900
+			targ_extra_emuls="elf32lr5900n32"
+			targ_extra_libpath=$targ_extra_emuls ;;
 mips*el-*-elf*)		targ_emul=elf32elmip ;;
 mips*-*-elf*)		targ_emul=elf32ebmip ;;
 mips*-*-rtems*)		targ_emul=elf32ebmip ;;
diff --git a/ld/emulparams/elf32lr5900.sh b/ld/emulparams/elf32lr5900.sh
new file mode 100644
index 0000000..e8745ff
--- /dev/null
+++ b/ld/emulparams/elf32lr5900.sh
@@ -0,0 +1,17 @@
+. ${srcdir}/emulparams/elf32bmip.sh
+
+OUTPUT_FORMAT="elf32-littlemips"
+BIG_OUTPUT_FORMAT="elf32-bigmips"
+LITTLE_OUTPUT_FORMAT="elf32-littlemips"
+
+TEXT_START_ADDR=0x0100000
+ARCH=mips:5900
+MACHINE=
+MAXPAGESIZE=128
+EMBEDDED=yes
+DYNAMIC_LINK=FALSE
+
+unset DATA_ADDR
+SHLIB_TEXT_START_ADDR=0
+unset GENERATE_SHLIB_SCRIPT
+
diff --git a/ld/emulparams/elf32lr5900n32.sh b/ld/emulparams/elf32lr5900n32.sh
new file mode 100644
index 0000000..69f7afb
--- /dev/null
+++ b/ld/emulparams/elf32lr5900n32.sh
@@ -0,0 +1,23 @@
+. ${srcdir}/emulparams/elf32bmipn32-defs.sh
+
+OUTPUT_FORMAT="elf32-nlittlemips"
+BIG_OUTPUT_FORMAT="elf32-nbigmips"
+LITTLE_OUTPUT_FORMAT="elf32-nlittlemips"
+
+TEXT_START_ADDR=0x0100000
+ARCH=mips:5900
+MACHINE=
+MAXPAGESIZE=128
+EMBEDDED=yes
+DYNAMIC_LINK=FALSE
+
+OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
+OTHER_SECTIONS='
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+'
+
+unset DATA_ADDR
+SHLIB_TEXT_START_ADDR=0
+unset GENERATE_SHLIB_SCRIPT
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 26d1e7a..ed0f903 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,23 @@
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* mips-dis.c: Add names for CP0 registers of r5900.
+	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
+	instructions sq and lq.
+	Add support for MIPS r5900 CPU.
+	Add support for 128 bit MMI (Multimedia Instructions).
+	Add support for EE instructions (Emotion Engine).
+	Disable unsupported floating point instructions (64 bit and
+	undefined compare operations).
+	Enable instructions of MIPS ISA IV which are supported by r5900.
+	Disable 64 bit co processor instructions.
+	Disable 64 bit multiplication and division instructions.
+	Disable instructions for co-processor 2 and 3, because these are
+	not supported (preparation for later VU0 support (Vector Unit)).
+	Disable cvt.w.s because this behaves like trunc.w.s and the
+	correct execution can't be ensured on r5900.
+	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
+	will confuse less developers and compilers.
+
 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 
 	* aarch64-opc.c (aarch64_print_operand): Change to print
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index f4a10ee..0bd5fef 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -233,6 +233,30 @@ static const char * const mips_cp0_names_r4000[32] =
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "$31",
 };
 
+static const char * const mips_cp0_names_r5900[32] =
+{
+  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
+  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
+  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
+  "c0_sr",        "c0_cause",     "c0_epc",       "c0_prid",
+  "c0_config",    "$17",          "$18",          "$19",
+  "$20",          "$21",          "$22",          "c0_badpaddr",
+  "c0_depc",      "c0_perfcnt",   "$26",          "$27",
+  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "$31"
+};
+
+static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] =
+{
+  { 24, 2, "c0_iab"			},
+  { 24, 3, "c0_iabm"		},
+  { 24, 4, "c0_dab"			},
+  { 24, 5, "c0_dabm"		},
+  { 24, 6, "c0_dvb"			},
+  { 24, 7, "c0_dvbm"		},
+  { 25, 1, "c0_perfcnt,1"	},
+  { 25, 2, "c0_perfcnt,2"	}
+};
+
 static const char * const mips_cp0_names_mips3264[32] =
 {
   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
@@ -532,6 +556,8 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "vr5500",	1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "r5900",	1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3,
+    mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
   { "r6000",	1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "rm7000",	1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 44cfad2..28c17da 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -115,6 +115,8 @@
 #define L1	INSN_4010
 #define V1	(INSN_4100 | INSN_4111 | INSN_4120)
 #define T3      INSN_3900
+/* Emotion Engine MIPS r5900. */
+#define EE      INSN_5900
 #define M1	INSN_10000
 #define SB1     INSN_SB1
 #define N411	INSN_4111
@@ -128,14 +130,25 @@
 #define XLR     INSN_XLR
 
 #define G1      (T3             \
+                 |EE            \
                  )
 
 #define G2      (T3             \
                  )
 
 #define G3      (I4             \
+                 |EE            \
                  )
 
+/* 64 bit CPU with 32 bit FPU (single float). */
+#define SF	EE
+
+/* Support for 128 bit MMI instructions. */
+#define MMI	EE
+
+/* 64 bit CPU with only 32 bit multiplication/division support. */
+#define M32	EE
+
 /* MIPS DSP ASE support.
    NOTE:
    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
@@ -275,7 +288,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 {"abs",     "d,v",	0,    (int) M_ABS,	INSN_MACRO,		0,		I1	},
 {"abs.s",   "D,V",	0x46000005, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
-{"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
+{"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1,	SF	},
 {"abs.ps",  "D,V",	0x46c00005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5_33|IL2F	},
 {"abs.ps",  "D,V",	0x45600005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		IL2E	},
 {"aclr",    "\\,~(b)",	0x04070000, 0xfc1f8000,	SM|RD_b|NODS,		0,		MC	},
@@ -286,7 +299,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add",	"D,S,T",	0x45c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
 {"add",	"D,S,T",	0x4b40000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
 {"add.s",   "D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
-{"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
+{"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,	SF	},
 {"add.ob",  "X,Y,Q",	0x7800000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"add.ob",  "D,S,T",	0x4ac0000b, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"add.ob",  "D,S,T[e]",	0x4800000b, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -296,6 +309,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add.qh",  "X,Y,Q",	0x7820000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
 {"adda.ob", "Y,Q",	0x78000037, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
 {"adda.qh", "Y,Q",	0x78200037, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
+{"adda.s",  "V,T",	0x46000018, 0xffe007ff,	RD_S|RD_T|FP_S,		0,		EE	},
 {"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
 {"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
 {"addl.ob", "Y,Q",	0x78000437, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
@@ -407,21 +421,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"break",   "",		0x0000000d, 0xffffffff,	TRAP,			0,		I1	},
 {"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,			0,		I1	},
 {"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,			0,		I1	},
-{"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.f.ps",  "S,T",	0x46c00030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.f.ps",  "S,T",	0x45600030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.f.ps",  "M,S,T",	0x46c00030, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.un.d",  "S,T",	0x46200031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.un.d",  "S,T",	0x46200031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.un.ps", "S,T",	0x46c00031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.un.ps", "S,T",	0x45600031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.un.ps", "M,S,T",	0x46c00031, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.eq.d",  "S,T",	0x46200032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.eq.d",  "S,T",	0x46200032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
@@ -433,72 +447,73 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.eq.ps", "S,T",	0x45600032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.eq.ps", "M,S,T",	0x46c00032, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
 {"c.eq.qh", "Y,Q",	0x78200001, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
-{"c.ueq.d", "S,T",	0x46200033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.ueq.d", "S,T",	0x46200033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.ueq.ps","S,T",	0x46c00033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.ueq.ps","S,T",	0x45600033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.ueq.ps","M,S,T",	0x46c00033, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1      },
+{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1,	SF	},
 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.olt.s", "S,T",	0x46000034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
+{"c.olt.s", "S,T",	0x46000034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1,	EE	},
 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.olt.ps","S,T",	0x46c00034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.olt.ps","S,T",	0x45600034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.olt.ps","M,S,T",	0x46c00034, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ult.d", "S,T",	0x46200035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.ult.d", "S,T",	0x46200035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.ult.ps","S,T",	0x46c00035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.ult.ps","S,T",	0x45600035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.ult.ps","M,S,T",	0x46c00035, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1      },
+{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1,	SF	},
 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.ole.ps","S,T",	0x46c00036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.ole.ps","S,T",	0x45600036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.ole.ps","M,S,T",	0x46c00036, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ule.d", "S,T",	0x46200037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.ule.d", "S,T",	0x46200037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.ule.ps","S,T",	0x46c00037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.ule.ps","S,T",	0x45600037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.ule.ps","M,S,T",	0x46c00037, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.sf.d",  "S,T",	0x46200038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.sf.d",  "S,T",	0x46200038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.sf.ps", "S,T",	0x46c00038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.sf.ps", "S,T",	0x45600038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.sf.ps", "M,S,T",	0x46c00038, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ngle.d","S,T",	0x46200039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.ngle.d","S,T",	0x46200039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.ngle.ps","S,T",	0x46c00039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.ngle.ps","S,T",	0x45600039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.ngle.ps","M,S,T",	0x46c00039, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.seq.d", "S,T",	0x4620003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.seq.d", "S,T",	0x4620003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.seq.ps","S,T",	0x46c0003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.seq.ps","S,T",	0x4560003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.seq.ps","M,S,T",	0x46c0003a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ngl.d", "S,T",	0x4620003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.ngl.d", "S,T",	0x4620003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.ngl.ps","S,T",	0x46c0003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.ngl.ps","S,T",	0x4560003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.ngl.ps","M,S,T",	0x46c0003b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.lt.d",  "S,T",	0x4620003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.lt.d",  "S,T",	0x4620003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.lt.s",  "S,T",	0x4600003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
+{"c.lt.s",  "S,T",	0x46000034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		EE	},
+{"c.lt.s",  "S,T",	0x4600003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1,	EE	},
 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.lt.ob", "Y,Q",	0x78000004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"c.lt.ob", "S,T",	0x4ac00004, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
@@ -508,16 +523,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.lt.ps", "S,T",	0x4560003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.lt.ps", "M,S,T",	0x46c0003c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
 {"c.lt.qh", "Y,Q",	0x78200004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
-{"c.nge.d", "S,T",	0x4620003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.nge.d", "S,T",	0x4620003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.nge.ps","S,T",	0x46c0003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.nge.ps","S,T",	0x4560003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.nge.ps","M,S,T",	0x46c0003d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.le.d",  "S,T",	0x4620003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.le.d",  "S,T",	0x4620003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.le.s",  "S,T",	0x4600003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
+{"c.le.s",  "S,T",	0x46000036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		EE	},
+{"c.le.s",  "S,T",	0x4600003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1,	EE	},
 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.le.ob", "Y,Q",	0x78000005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"c.le.ob", "S,T",	0x4ac00005, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
@@ -527,9 +543,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.le.ps", "S,T",	0x4560003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
 {"c.le.ps", "M,S,T",	0x46c0003e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
 {"c.le.qh", "Y,Q",	0x78200005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
-{"c.ngt.d", "S,T",	0x4620003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
+{"c.ngt.d", "S,T",	0x4620003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	SF	},
 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,	EE	},
 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
 {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
 {"c.ngt.ps","S,T",	0x4560003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
@@ -591,8 +607,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cache",   "k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3_32|T3},
 {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
 {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"ceil.w.s", "D,S",	0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
+{"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2,	SF	},
+{"ceil.w.s", "D,S",	0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2,	EE	},
 {"cfc0",    "t,G",	0x40400000, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		I1,		IOCT|IOCTP|IOCT2	},
 {"cfc1",    "t,G",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	0,		I1	},
 {"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	0,		I1	},
@@ -615,17 +631,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cttc1",   "t,S",	0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,		MT32	},
 {"cttc2",   "t,g",	0x41800025, 0xffe007ff,	TRAP|COD|RD_t|WR_CC,	0,		MT32,		IOCT|IOCTP|IOCT2	},
 {"cvt.d.l", "D,S",	0x46a00021, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I3_33	},
-{"cvt.d.s", "D,S",	0x46000021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
-{"cvt.d.w", "D,S",	0x46800021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
+{"cvt.d.s", "D,S",	0x46000021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1,	SF	},
+{"cvt.d.w", "D,S",	0x46800021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1,	SF	},
 {"cvt.l.d", "D,S",	0x46200025, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I3_33	},
 {"cvt.l.s", "D,S",	0x46000025, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
 {"cvt.s.l", "D,S",	0x46a00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"cvt.s.d", "D,S",	0x46200020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
+{"cvt.s.d", "D,S",	0x46200020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1,	SF	},
 {"cvt.s.w", "D,S",	0x46800020, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
 {"cvt.s.pl","D,S",	0x46c00028, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I5_33	},
 {"cvt.s.pu","D,S",	0x46c00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I5_33	},
-{"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
-{"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
+{"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1,	SF	},
+{"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1,	EE	},
 {"cvt.ps.pw", "D,S",	0x46800026, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		M3D	},
 {"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S|FP_D, 0,		I5_33	},
 {"cvt.pw.ps", "D,S",	0x46c00024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		M3D	},
@@ -651,13 +667,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
 /* For ddiv, see the comments about div.  */
-{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3	},
-{"ddiv",    "d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3	},
+{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3,	M32	},
+{"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3,	M32	},
+{"ddiv",    "d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3,	M32	},
 /* For ddivu, see the comments about div.  */
-{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"ddivu",   "d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3	},
-{"ddivu",   "d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3	},
+{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3,	M32	},
+{"ddivu",   "d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3,	M32	},
+{"ddivu",   "d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3,	M32	},
+{"di",      "",		0x42000039, 0xffffffff,	WR_C0,			0,		EE	},
 {"di",      "",		0x41606000, 0xffffffff,	WR_t|WR_C0,		0,		I33	},
 {"di",      "t",	0x41606000, 0xffe0ffff,	WR_t|WR_C0,		0,		I33	},
 {"dins",    "t,r,I,+I",	0,    (int) M_DINS,	INSN_MACRO,		0,		I65	},
@@ -672,7 +689,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
 {"div",     "d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1	},
 {"div",     "d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1	},
-{"div.d",   "D,V,T",	0x46200003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
+{"div1",    "z,s,t",    0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		EE	},
+{"div1",    "z,t",      0x7000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		EE	},
+{"div.d",   "D,V,T",	0x46200003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,	SF	},
 {"div.s",   "D,V,T",	0x46000003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
 {"div.ps",  "D,V,T",	0x46c00003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
 /* For divu, see the comments about div.  */
@@ -680,6 +699,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
 {"divu",    "d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1	},
 {"divu",    "d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1	},
+{"divu1",   "z,s,t",    0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		EE	},
+{"divu1",   "z,t",      0x7000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		EE	},
 {"dla",     "t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,		0,		I3	},
 {"dlca",    "t,A(b)",	0,    (int) M_DLCA_AB,	INSN_MACRO,		0,		I3	},
 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,			0,		I3	}, /* addiu */
@@ -694,40 +715,40 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccu",  "d,s,t",	0x00000069, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
 {"dmaccus", "d,s,t",	0x00000469, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,		N411    },
-{"dmfc0",   "t,G",	0x40200000, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		I3	},
+{"dmfc0",   "t,G",	0x40200000, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		I3,	EE	},
 {"dmfc0",   "t,+D",	0x40200000, 0xffe007f8,	LCD|WR_t|RD_C0,		0,		I64	},
 {"dmfc0",   "t,G,H",	0x40200000, 0xffe007f8,	LCD|WR_t|RD_C0,		0,		I64	},
 {"dmt",     "",		0x41600bc1, 0xffffffff, TRAP,			0,		MT32	},
 {"dmt",     "t",	0x41600bc1, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
-{"dmtc0",   "t,G",	0x40a00000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	0,		I3	},
+{"dmtc0",   "t,G",	0x40a00000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	0,		I3,	EE	},
 {"dmtc0",   "t,+D",	0x40a00000, 0xffe007f8,	COD|RD_t|WR_C0|WR_CC,	0,		I64	},
 {"dmtc0",   "t,G,H",	0x40a00000, 0xffe007f8,	COD|RD_t|WR_C0|WR_CC,	0,		I64	},
-{"dmfc1",   "t,S",	0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,	0,		I3	},
-{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,		I3      },
-{"dmtc1",   "t,S",	0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,	0,		I3	},
-{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,		I3      },
+{"dmfc1",   "t,S",	0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,	0,		I3,	SF	},
+{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,		I3,	SF	},
+{"dmtc1",   "t,S",	0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,	0,		I3,	SF	},
+{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,		I3,	SF	},
 /* dmfc2 is at the bottom of the table.  */
 /* dmtc2 is at the bottom of the table.  */
 /* dmfc3 is at the bottom of the table.  */
 /* dmtc3 is at the bottom of the table.  */
 {"dmul",    "d,v,t",	0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		IOCT	},
-{"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,		I3	},
-{"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,		I3	},
-{"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,		I3	},
-{"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,		I3	},
-{"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,		I3	},
-{"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,		0,		I3	},
-{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3	},
-{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3	},
+{"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,		I3,	M32	},
+{"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,		I3,	M32	},
+{"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,		I3,	M32	},
+{"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,		I3,	M32	},
+{"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,		I3,	M32	},
+{"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,		0,		I3,	M32	},
+{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3,	M32	},
+{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3,	M32	},
 {"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsub 0 */
 {"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsubu 0*/
 {"dpop",    "d,v",	0x7000002d, 0xfc1f07ff, WR_d|RD_s,		0,		IOCT	},
-{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"drem",    "d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,		I3	},
-{"drem",    "d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3	},
-{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"dremu",   "d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3	},
-{"dremu",   "d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3	},
+{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3,	M32	},
+{"drem",    "d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,		I3,	M32	},
+{"drem",    "d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3,	M32	},
+{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3,	M32	},
+{"dremu",   "d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3,	M32	},
+{"dremu",   "d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3,	M32	},
 {"dret",    "",		0x7000003e, 0xffffffff,	0,			0,		N5	},
 {"drol",    "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I3	},
 {"drol",    "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3	},
@@ -773,6 +794,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3	},
 {"dvpe",    "",		0x41600001, 0xffffffff, TRAP,			0,		MT32	},
 {"dvpe",    "t",	0x41600001, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
+{"ei",      "",		0x42000038, 0xffffffff,	WR_C0,			0,		EE	},
 {"ei",      "",		0x41606020, 0xffffffff,	WR_t|WR_C0,		0,		I33	},
 {"ei",      "t",	0x41606020, 0xffe0ffff,	WR_t|WR_C0,		0,		I33	},
 {"emt",     "",		0x41600be1, 0xffffffff, TRAP,			0,		MT32	},
@@ -786,7 +808,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"exts",    "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
 {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
 {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
+{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2,	SF	},
 {"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
 {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
@@ -851,17 +873,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ldaddw",  "t,b",	0x70000010, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
 {"ldaddwu", "t,b",	0x70000011, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
 {"ldaddd",  "t,b",	0x70000012, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
-{"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
-{"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
-{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	}, /* ldc1 */
-{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I2,		IOCT|IOCTP|IOCT2	},
-{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2	},
-{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I2,		IOCT|IOCTP|IOCT2	},
-{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2	},
+{"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2,	SF	},
+{"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2,	SF	},
+{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,	SF	},
+{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,	SF	},
+{"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2,	SF	}, /* ldc1 */
+{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		INSN2_M_FP_D,	I1,	SF	},
+{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1,	SF	},
+{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
+{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
+{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
+{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
 {"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
 {"ldl",	    "t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		0,		I3	},
 {"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
@@ -872,14 +894,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lhu",     "t,o(b)",	0x94000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
 {"lhu",     "t,A(b)",	0,    (int) M_LHU_AB,	INSN_MACRO,		0,		I1	},
 /* li is at the start of the table.  */
-{"li.d",    "t,F",	0,    (int) M_LI_D,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
+{"li.d",    "t,F",	0,    (int) M_LI_D,	INSN_MACRO,		INSN2_M_FP_D,	I1,	SF	},
+{"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO,		INSN2_M_FP_D,	I1,	SF	},
 {"li.s",    "t,f",	0,    (int) M_LI_S,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
 {"li.s",    "T,l",	0,    (int) M_LI_SS,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
 {"ll",	    "t,o(b)",	0xc0000000, 0xfc000000, LDD|RD_b|WR_t,		0,		I2	},
 {"ll",	    "t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,		0,		I2	},
 {"lld",	    "t,o(b)",	0xd0000000, 0xfc000000, LDD|RD_b|WR_t,		0,		I3	},
 {"lld",     "t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,		0,		I3	},
+{"lq",      "t,o(b)",	0x78000000, 0xfc000000, WR_t|RD_b,		0,		MMI	},
+{"lq",      "t,A(b)",	0,    (int) M_LQ_AB,	INSN_MACRO,		0,		MMI	},
 {"lui",     "t,u",	0x3c000000, 0xffe00000,	WR_t,			0,		I1	},
 {"luxc1",   "D,t(b)",	0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I5_33|N55},
 {"lw",      "t,o(b)",	0x8c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
@@ -892,10 +916,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
 {"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	}, /* lwc1 */
 {"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2	},
+{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
 {"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
 {"lwl",     "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I1	},
 {"lcache",  "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I2	}, /* same */
@@ -929,6 +953,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,		I4_33	},
 {"madd.s",	"D,S,T",	0x46000018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
 {"madd.s",	"D,S,T",	0x72000018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
+{"madd.s",  "D,S,T",	0x4600001c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,	     0,		EE	},
 {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I5_33	},
 {"madd.ps",	"D,S,T",	0x45600018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"madd.ps",	"D,S,T",	0x71600018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
@@ -937,20 +962,33 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
 {"madd",    "7,s,t",	0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
+{"madd1",   "s,t",      0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		EE	},
+{"madd1",   "d,s,t",    0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		EE	},
+{"madda.s", "S,T",	0x4600001e, 0xffe007ff, RD_S|RD_T|FP_S,		     0,		EE	},
 {"maddp",   "s,t",      0x70000441, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	     0,		SMT	},
 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
 {"maddu",   "7,s,t",	0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
+{"maddu1",  "s,t",      0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		EE	},
+{"maddu1",  "d,s,t",    0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		EE	},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,	0,		N411    },
 {"max.ob",  "X,Y,Q",	0x78000007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"max.ob",  "D,S,T",	0x4ac00007, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"max.ob",  "D,S,T[e]",	0x48000007, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"max.ob",  "D,S,k",	0x4bc00007, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"max.qh",  "X,Y,Q",	0x78200007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"mfpc",    "t,P",	0x4000c801, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5	},
-{"mfps",    "t,P",	0x4000c800, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5	},
+{"max.s",   "D,S,T",	0x46000028, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,	0,		EE	},
+{"mfbpc",   "t",	0x4000c000, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE	},
+{"mfdab",   "t",	0x4000c004, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE	},
+{"mfdabm",  "t",	0x4000c005, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE	},
+{"mfdvb",   "t",	0x4000c006, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE	},
+{"mfdvbm",  "t",	0x4000c007, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE	},
+{"mfiab",   "t",	0x4000c002, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE	},
+{"mfiabm",  "t",	0x4000c003, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE	},
+{"mfpc",    "t,P",	0x4000c801, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5|EE	},
+{"mfps",    "t,P",	0x4000c800, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5|EE	},
 {"mftacx",  "d",	0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,		0,		MT32	},
 {"mftacx",  "d,*",	0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,		0,		MT32	},
 {"mftc0",   "d,+t",	0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,	0,		MT32	},
@@ -982,16 +1020,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfdr",    "t,G",	0x7000003d, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		N5      },
 {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,		0,		I1	},
 {"mfhi",    "d,9",	0x00000010, 0xff9f07ff, WR_d|RD_HI,		0,		D32	},
+{"mfhi1",   "d",	0x70000010, 0xffff07ff,	WR_d|RD_HI,		0,		EE	},
 {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,		0,		I1	},
 {"mflo",    "d,9",	0x00000012, 0xff9f07ff, WR_d|RD_LO,		0,		D32	},
+{"mflo1",   "d",	0x70000012, 0xffff07ff,	WR_d|RD_LO,		0,		EE	},
 {"mflhxu",  "d",	0x00000052, 0xffff07ff,	WR_d|MOD_HILO,		0,		SMT	},
 {"mfcr",    "t,s",	0x70000018, 0xfc00ffff, WR_t,			0,		XLR 	},
+{"mfsa",    "d",	0x00000028, 0xffff07ff,	WR_d,			0,		EE	},
 {"min.ob",  "X,Y,Q",	0x78000006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"min.ob",  "D,S,T",	0x4ac00006, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"min.ob",  "D,S,T[e]",	0x48000006, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"min.ob",  "D,S,k",	0x4bc00006, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"min.qh",  "X,Y,Q",	0x78200006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
+{"min.s",   "D,S,T",	0x46000029, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,	0,		EE	},
+{"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1,	SF	},
 {"mov.s",   "D,S",	0x46000006, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
 {"mov.ps",  "D,S",	0x46c00006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5_33|IL2F	},
 {"mov.ps",  "D,S",	0x45600006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		IL2E	},
@@ -1001,7 +1043,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.l",  "X,Y,N",	0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		MX|SB1	},
 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4_32	},
 {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5_33	},
-{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4_32|IL2E|IL2F	},
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4_32|IL2E|IL2F|EE	},
 {"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		IL2E|IL2F|IL3A	},
 {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4_32	},
@@ -1015,7 +1057,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		MX|SB1	},
 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4_32	},
 {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5_33	},
-{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4_32|IL2E|IL2F	},
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4_32|IL2E|IL2F|EE	},
 {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4_32	},
 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
@@ -1039,17 +1081,26 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4_33	},
 {"msub.s",	"D,S,T",	0x46000019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
 {"msub.s",	"D,S,T",	0x72000019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
+{"msub.s",  "D,S,T",	0x4600001d, 0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,		EE	},
 {"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5_33	},
 {"msub.ps",	"D,S,T",	0x45600019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"msub.ps",	"D,S,T",	0x71600019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1    	},
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55 },
 {"msub",    "7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
+{"msuba.s", "S,T",	0x4600001f, 0xffe007ff,	RD_S|RD_T|FP_S,		0,		EE	},
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1	},
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55	},
 {"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
-{"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
-{"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
+{"mtbpc",   "t",	0x4080c000, 0xffe0ffff,	COD|RD_t|WR_C0,		0,		EE	},
+{"mtdab",   "t",	0x4080c004, 0xffe0ffff,	COD|RD_t|WR_C0,		0,		EE	},
+{"mtdabm",  "t",	0x4080c005, 0xffe0ffff,	COD|RD_t|WR_C0,		0,		EE	},
+{"mtdvb",   "t",	0x4080c006, 0xffe0ffff,	COD|RD_t|WR_C0,		0,		EE	},
+{"mtdvbm",  "t",	0x4080c007, 0xffe0ffff,	COD|RD_t|WR_C0,		0,		EE	},
+{"mtiab",   "t",	0x4080c002, 0xffe0ffff,	COD|RD_t|WR_C0,		0,		EE	},
+{"mtiabm",  "t",	0x4080c003, 0xffe0ffff,	COD|RD_t|WR_C0,		0,		EE	},
+{"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5|EE	},
+{"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5|EE	},
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	0,		I1	},
 {"mtc0",    "t,+D",	0x40800000, 0xffe007f8,	COD|RD_t|WR_C0|WR_CC,	0,		I32	},
 {"mtc0",    "t,G,H",	0x40800000, 0xffe007f8,	COD|RD_t|WR_C0|WR_CC,	0,		I32	},
@@ -1063,8 +1114,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtdr",    "t,G",	0x7080003d, 0xffe007ff,	COD|RD_t|WR_C0,		0,		N5	},
 {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,		0,		I1	},
 {"mthi",    "s,7",	0x00000011, 0xfc1fe7ff, RD_s|WR_HI,		0,		D32	},
+{"mthi1",   "s",	0x70000011, 0xfc1fffff,	RD_s|WR_HI,		0,		EE	},
 {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,		0,		I1	},
 {"mtlo",    "s,7",	0x00000013, 0xfc1fe7ff, RD_s|WR_LO,		0,		D32	},
+{"mtlo1",   "s",	0x70000013, 0xfc1fffff,	RD_s|WR_LO,		0,		EE	},
 {"mtlhx",   "s",	0x00000053, 0xfc1fffff,	RD_s|MOD_HILO,		0,		SMT	},
 {"mtcr",    "t,s",      0x70000019, 0xfc00ffff, RD_t,			0,		XLR	},
 {"mtm0",    "s",	0x70000008, 0xfc1fffff, RD_s,			0,		IOCT	},
@@ -1073,6 +1126,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtp0",    "s",	0x70000009, 0xfc1fffff, RD_s,			0,		IOCT	},
 {"mtp1",    "s",	0x7000000a, 0xfc1fffff, RD_s,			0,		IOCT	},
 {"mtp2",    "s",	0x7000000b, 0xfc1fffff, RD_s,			0,		IOCT	},
+{"mtsa",    "s",	0x00000029, 0xfc1fffff,	RD_s,			0,		EE	},
+{"mtsab",   "s,j",	0x04180000, 0xfc1f0000,	RD_s,			0,		EE	},
+{"mtsah",   "s,j",	0x04190000, 0xfc1f0000,	RD_s,			0,		EE	},
 {"mttc0",   "t,G",	0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
 {"mttc0",   "t,+D",	0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
 {"mttc0",   "t,G,H",	0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
@@ -1091,7 +1147,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mttlo",   "t",	0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,		0,		MT32	},
 {"mttlo",   "t,&",	0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,		0,		MT32	},
 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,		0,		MT32	},
-{"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
+{"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,	SF	},
 {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
 {"mul.ob",  "X,Y,Q",	0x78000030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"mul.ob",  "D,S,T",	0x4ac00030, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1109,6 +1165,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mula.ob", "S,T[e]",	0x48000033, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
 {"mula.ob", "S,k",	0x4bc00033, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
 {"mula.qh", "Y,Q",	0x78200033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
+{"mula.s",  "V,T",	0x4600001a, 0xffe007ff,	RD_S|RD_T|FP_S,		0,		EE	},
 {"mulhi",   "d,s,t",	0x00000258, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
 {"mulhiu",  "d,s,t",	0x00000259, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
 {"mull.ob", "Y,Q",	0x78000433, 0xfc2007ff,	RD_S|RD_T|FP_D, 	WR_MACC,	MX|SB1	},
@@ -1138,14 +1195,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
 {"mult",    "7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
+{"mult1",   "s,t",      0x70000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		EE	},
+{"mult1",   "d,s,t",    0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		EE	},
 {"multp",   "s,t",	0x00000459, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		SMT	},
 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
 {"multu",   "7,s,t",	0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
+{"multu1",  "s,t",      0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		EE	},
+{"multu1",  "d,s,t",    0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		EE	},
 {"mulu",    "d,s,t",	0x00000059, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
 {"neg",     "d,w",	0x00000022, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* sub 0 */
 {"negu",    "d,w",	0x00000023, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* subu 0 */
-{"neg.d",   "D,V",	0x46200007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
+{"neg.d",   "D,V",	0x46200007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1,	SF	},
 {"neg.s",   "D,V",	0x46000007, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
 {"neg.ps",  "D,V",	0x46c00007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5_33|IL2F	},
 {"neg.ps",  "D,V",	0x45600007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		IL2E	},
@@ -1192,6 +1253,39 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pabsdiffc.ob", "Y,Q",	0x78000035, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	SB1	},
 {"pause",   "",		0x00000140, 0xffffffff, TRAP,			0,		I33	},
 {"pavg.ob", "X,Y,Q",	0x78000008, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
+{"pabsh",   "d,t",	0x70000168, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"pabsw",   "d,t",	0x70000068, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"paddsw",  "d,s,t",	0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"paddub",  "d,s,t",	0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"padduh",  "d,s,t",	0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"padduw",  "d,s,t",	0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"padsbh",  "d,s,t",	0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pand",    "d,s,t",	0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pceqb",   "d,s,t",	0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pceqh",   "d,s,t",	0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pceqw",   "d,s,t",	0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pcgtb",   "d,s,t",	0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pcgth",   "d,s,t",	0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pcgtw",   "d,s,t",	0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pcpyh",   "d,t",	0x700006e9, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"pcpyld",  "d,s,t",	0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pcpyud",  "d,s,t",	0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pdivbw",  "s,t",	0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"pdivuw",  "s,t",	0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"pdivw",   "s,t",	0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"pexch",   "d,t",	0x700006a9, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"pexcw",   "d,t",	0x700007a9, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"pexeh",   "d,t",	0x70000689, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"pexew",   "d,t",	0x70000789, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"pext5",   "d,t",	0x70000788, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"pextlb",  "d,s,t",	0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pextlh",  "d,s,t",	0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pextlw",  "d,s,t",	0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pextub",  "d,s,t",	0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pextuh",  "d,s,t",	0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pextuw",  "d,s,t",	0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"phmadh",  "d,s,t",	0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"phmsbh",  "d,s,t",	0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI	},
 {"pickf.ob", "X,Y,Q",	0x78000002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"pickf.ob", "D,S,T",	0x4ac00002, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1202,13 +1296,55 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"pickt.ob", "D,S,k",	0x4bc00003, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"pickt.qh", "X,Y,Q",	0x78200003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
+{"pinteh",  "d,s,t",	0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pinth",   "d,s,t",	0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
 {"pll.ps",  "D,V,T",	0x46c0002c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
 {"plu.ps",  "D,V,T",	0x46c0002d, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
+{"plzcw",   "d,s",	0x70000004, 0xfc1f07ff, WR_d|RD_s,		0,		MMI	},
+{"pmaddh",  "d,s,t",	0x70000409, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"pmadduw", "d,s,t",	0x70000029, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0,		MMI	},
+{"pmaddw",  "d,s,t",	0x70000009, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0,		MMI	},
+{"pmaxh",   "d,s,t",	0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pmaxw",   "d,s,t",	0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pmfhi",   "d",	0x70000209, 0xffff07ff, WR_d|RD_HI,		0,		MMI	},
+{"pmfhl.lh", "d",	0x700000f0, 0xffff07ff, WR_d|RD_HILO,		0,		MMI	},
+{"pmfhl.lw", "d",	0x70000030, 0xffff07ff, WR_d|RD_HILO,		0,		MMI	},
+{"pmfhl.sh", "d",	0x70000130, 0xffff07ff, WR_d|RD_HILO,		0,		MMI	},
+{"pmfhl.slw", "d",	0x700000b0, 0xffff07ff, WR_d|RD_HILO,		0,		MMI	},
+{"pmfhl.uw", "d",	0x70000070, 0xffff07ff, WR_d|RD_HILO,		0,		MMI	},
+{"pmflo",   "d",	0x70000249, 0xffff07ff, WR_d|RD_LO,		0,		MMI	},
+{"pminh",   "d,s,t",	0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pminw",   "d,s,t",	0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pmsubh",  "d,s,t",	0x70000509, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0,		MMI	},
+{"pmsubw",  "d,s,t",	0x70000109, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0,		MMI	},
+{"pmthi",   "s",	0x70000229, 0xfc1fffff, RD_s|WR_HI,		0,		MMI	},
+{"pmthl.lw", "s",	0x70000031, 0xfc1fffff, RD_s|MOD_HILO,		0,		MMI	},
+{"pmtlo",   "s",	0x70000269, 0xfc1fffff, RD_s|WR_LO,		0,		MMI	},
+{"pmulth",  "d,s,t",	0x70000709, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"pmultuw", "d,s,t",	0x70000329, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"pmultw",  "d,s,t",	0x70000309, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI	},
+{"pnor",    "d,s,t",	0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
 {"pop",     "d,v",	0x7000002c, 0xfc1f07ff, WR_d|RD_s,		0,		IOCT	},
+{"por",     "d,s,t",	0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"ppac5",   "d,t",	0x700007c8, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"ppacb",   "d,s,t",	0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"ppach",   "d,s,t",	0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"ppacw",   "d,s,t",	0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"prevh",   "d,t",	0x700006c9, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"prot3w",  "d,t",	0x700007c9, 0xffe007ff, WR_d|RD_t,		0,		MMI	},
+{"psllvw",  "d,t,s",	0x70000089, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"psravw",  "d,t,s",	0x700000e9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"psrlvw",  "d,t,s",	0x700000c9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"psubsw",  "d,s,t",	0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"psubub",  "d,s,t",	0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"psubuh",  "d,s,t",	0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"psubuw",  "d,s,t",	0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
+{"pxor",    "d,s,t",	0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
   /* pref and prefx are at the start of the table.  */
 {"pul.ps",  "D,V,T",	0x46c0002e, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
 {"puu.ps",  "D,V,T",	0x46c0002f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
 {"pperm",   "s,t",	0x70000481, 0xfc00ffff,	MOD_HILO|RD_s|RD_t,	0,		SMT	},
+{"qfsrv",   "d,s,t",	0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI	},
 {"qmac.00", "s,t",	0x70000412, 0xfc00ffff, MOD_HILO|RD_s|RD_t,	0,		IOCT2	},
 {"qmac.01", "s,t",	0x70000452, 0xfc00ffff, MOD_HILO|RD_s|RD_t,	0,		IOCT2	},
 {"qmac.02", "s,t",	0x70000492, 0xfc00ffff, MOD_HILO|RD_s|RD_t,	0,		IOCT2	},
@@ -1263,11 +1399,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		I33|SMT	},
 {"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
 {"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
+{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2,	SF	},
 {"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
 {"rsqrt.d", "D,S",	0x46200016, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4_33	},
 {"rsqrt.ps","D,S",	0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
 {"rsqrt.s", "D,S",	0x46000016, 0xffff003f, WR_D|RD_S|FP_S,		0,		I4_33	},
+{"rsqrt.s", "D,S,T",	0x46000016, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,	0,		EE	},
 {"rsqrt1.d",  "D,S",	0x4620001e, 0xffff003f,	WR_D|RD_S|FP_D,		0,		M3D	},
 {"rsqrt1.ps", "D,S",	0x46c0001e, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
 {"rsqrt1.s",  "D,S",	0x4600001e, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
@@ -1299,17 +1436,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,			0,		G2	},
 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,           	0,		I32     },
 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           	0,		I32     },
-{"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I2,		IOCT|IOCTP|IOCT2	},
-{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2	},
-{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I2,		IOCT|IOCTP|IOCT2	},
-{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2	},
-{"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
+{"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2,	SF	},
+{"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2,	SF	},
+{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,	SF	},
+{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,	SF	},
+{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
+{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
+{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
+{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2,		IOCT|IOCTP|IOCT2|EE	},
+{"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2,	SF	},
+{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		INSN2_M_FP_D,	I1,	SF	},
+{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1,	SF	},
 {"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
 {"sdl",     "t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		0,		I3	},
 {"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
@@ -1380,7 +1517,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO,		0,		I1	},
 {"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,		0,		I1	},
 {"snei",    "t,r,+Q",	0x7000002f, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
-{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2	},
+{"sq",      "t,o(b)",	0x7c000000, 0xfc000000,	SM|RD_t|RD_b,		0,		MMI	},
+{"sq",      "t,A(b)",	0,    (int) M_SQ_AB,	INSN_MACRO,		0,		MMI	},
+{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2,	SF	},
 {"sqrt.s",  "D,S",	0x46000004, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
 {"sqrt.ps", "D,S",	0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
 {"srav",    "d,t,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
@@ -1404,7 +1543,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1	},
 {"sub",	"D,S,T",	0x45c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
 {"sub",	"D,S,T",	0x4b40000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
-{"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
+{"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,	SF	},
 {"sub.s",   "D,V,T",	0x46000001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
 {"sub.ob",  "X,Y,Q",	0x7800000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"sub.ob",  "D,S,T",	0x4ac0000a, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1417,6 +1556,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"suba.qh", "Y,Q",	0x78200036, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
 {"subl.ob", "Y,Q",	0x78000436, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
 {"subl.qh", "Y,Q",	0x78200436, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
+{"suba.s",  "V,T",	0x46000019, 0xffe007ff,	RD_S|RD_T|FP_S,		0,		EE	},
 {"subu",    "d,v,t",	0x00000023, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"subu",    "d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,		0,		I1	},
 {"subu",	"D,S,T",	0x45800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
@@ -1436,10 +1576,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"swc1",    "E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
 {"s.s",     "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	}, /* swc1 */
 {"s.s",     "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2	},
+{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
 {"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
 {"swl",     "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I1	},
 {"scache",  "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b,		0,		I2	}, /* same */
@@ -1501,11 +1641,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tne",     "s,I",	0,    (int) M_TNE_I,	INSN_MACRO,		0,		I2	},
 {"trunc.l.d", "D,S",	0x46200009, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
 {"trunc.l.s", "D,S",	0x46000009, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO,		INSN2_M_FP_S|INSN2_M_FP_D, I1 },
-{"trunc.w.s", "D,S",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2	},
-{"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2	},
+{"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2,	SF	},
+{"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2,	SF	},
+{"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO,		INSN2_M_FP_S|INSN2_M_FP_D, I1,	SF	},
+{"trunc.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,		0,		EE	},
+{"trunc.w.s", "D,S",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2,	EE	},
+{"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2,	EE	},
 {"trunc.w.s", "D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
 {"uld",     "t,o(b)",	0,    (int) M_ULD,	INSN_MACRO,		0,		I3	},
 {"uld",     "t,A(b)",	0,    (int) M_ULD_A,	INSN_MACRO,		0,		I3	},
@@ -1618,28 +1759,28 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
-{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
+{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
 {"bc2f",    "N,p",	0x49000000, 0xffe30000,	CBD|RD_CC,		0,		I32,		IOCT|IOCTP|IOCT2	},
-{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2	},
+{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2|EE	},
 {"bc2fl",   "N,p",	0x49020000, 0xffe30000,	CBL|RD_CC,		0,		I32,		IOCT|IOCTP|IOCT2	},
-{"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
+{"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
 {"bc2t",    "N,p",	0x49010000, 0xffe30000,	CBD|RD_CC,		0,		I32,		IOCT|IOCTP|IOCT2	},
-{"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2	},
+{"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2|EE	},
 {"bc2tl",   "N,p",	0x49030000, 0xffe30000,	CBL|RD_CC,		0,		I32,		IOCT|IOCTP|IOCT2	},
-{"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"ctc2",    "t,G",	0x48c00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
+{"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"ctc2",    "t,G",	0x48c00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
 {"dmfc2",   "t,i",	0x48200000, 0xffe00000,	LCD|WR_t|RD_C2,		0,		IOCT	},
-{"dmfc2",   "t,G",	0x48200000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I3,		IOCT|IOCTP|IOCT2	},
+{"dmfc2",   "t,G",	0x48200000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I3,		IOCT|IOCTP|IOCT2|EE	},
 {"dmfc2",   "t,G,H",	0x48200000, 0xffe007f8,	LCD|WR_t|RD_C2,		0,		I64,		IOCT|IOCTP|IOCT2	},
 {"dmtc2",   "t,i",	0x48a00000, 0xffe00000,	COD|RD_t|WR_C2|WR_CC,	0,		IOCT	},
-{"dmtc2",   "t,G",	0x48a00000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I3,		IOCT|IOCTP|IOCT2	},
+{"dmtc2",   "t,G",	0x48a00000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I3,		IOCT|IOCTP|IOCT2|EE	},
 {"dmtc2",   "t,G,H",	0x48a00000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	0,		I64,		IOCT|IOCTP|IOCT2	},
-{"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I1,		IOCT|IOCTP|IOCT2	},
+{"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
 {"mfc2",    "t,G,H",	0x48000000, 0xffe007f8,	LCD|WR_t|RD_C2,		0,		I32,		IOCT|IOCTP|IOCT2	},
 {"mfhc2",   "t,G",	0x48600000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I33,		IOCT|IOCTP|IOCT2	},
 {"mfhc2",   "t,G,H",	0x48600000, 0xffe007f8,	LCD|WR_t|RD_C2,		0,		I33,		IOCT|IOCTP|IOCT2	},
 {"mfhc2",   "t,i",	0x48600000, 0xffe00000,	LCD|WR_t|RD_C2,		0,		I33,		IOCT|IOCTP|IOCT2	},
-{"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I1,		IOCT|IOCTP|IOCT2	},
+{"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I1,		IOCT|IOCTP|IOCT2|EE	},
 {"mtc2",    "t,G,H",	0x48800000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	0,		I32,		IOCT|IOCTP|IOCT2	},
 {"mthc2",   "t,G",	0x48e00000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I33,		IOCT|IOCTP|IOCT2	},
 {"mthc2",   "t,G,H",	0x48e00000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	0,		I33,		IOCT|IOCTP|IOCT2	},
@@ -1647,18 +1788,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
    instructions, so they are here for the latters to take precedence.  */
-{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2	},
-{"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2	},
-{"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"ctc3",    "t,G",	0x4cc00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"dmfc3",   "t,G",	0x4c200000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I3,		IOCT|IOCTP|IOCT2	},
-{"dmtc3",   "t,G",	0x4ca00000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	0,		I3,		IOCT|IOCTP|IOCT2	},
-{"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1,		IOCT|IOCTP|IOCT2	},
-{"mfc3",    "t,G,H",	0x4c000000, 0xffe007f8,	LCD|WR_t|RD_C3,		0,		I32,		IOCT|IOCTP|IOCT2	},
-{"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	0,		I1,		IOCT|IOCTP|IOCT2	},
-{"mtc3",    "t,G,H",	0x4c800000, 0xffe007f8,	COD|RD_t|WR_C3|WR_CC,	0,		I32,		IOCT|IOCTP|IOCT2	},
+{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2|EE	},
+{"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3,		IOCT|IOCTP|IOCT2|EE	},
+{"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"ctc3",    "t,G",	0x4cc00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"dmfc3",   "t,G",	0x4c200000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I3,		IOCT|IOCTP|IOCT2|EE	},
+{"dmtc3",   "t,G",	0x4ca00000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	0,		I3,		IOCT|IOCTP|IOCT2|EE	},
+{"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"mfc3",    "t,G,H",	0x4c000000, 0xffe007f8,	LCD|WR_t|RD_C3,		0,		I32,		IOCT|IOCTP|IOCT2|EE	},
+{"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	0,		I1,		IOCT|IOCTP|IOCT2|EE	},
+{"mtc3",    "t,G,H",	0x4c800000, 0xffe007f8,	COD|RD_t|WR_C3|WR_CC,	0,		I32,		IOCT|IOCTP|IOCT2|EE	},
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
@@ -1994,16 +2135,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"packushb",	"D,S,T",	0x4b600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddb",	"D,S,T",	0x47c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"paddb",	"D,S,T",	0x4bc00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"paddb",	"d,s,t",	0x70000208,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"paddh",	"D,S,T",	0x47400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
+{"paddh",	"d,s,t",	0x70000108,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"paddh",	"D,S,T",	0x4b400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddw",	"D,S,T",	0x47600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"paddw",	"D,S,T",	0x4b600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"paddw",	"d,s,t",	0x70000008,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"paddd",	"D,S,T",	0x47e00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"paddd",	"D,S,T",	0x4be00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddsb",	"D,S,T",	0x47800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"paddsb",	"D,S,T",	0x4b800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"paddsb",	"d,s,t",	0x70000608,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"paddsh",	"D,S,T",	0x47000000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"paddsh",	"D,S,T",	0x4b000000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"paddsh",	"d,s,t",	0x70000508,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"paddusb",	"D,S,T",	0x47a00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"paddusb",	"D,S,T",	0x4ba00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddush",	"D,S,T",	0x47200000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
@@ -2064,28 +2210,39 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pshufh",	"D,S,T",	0x4b000002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psllh",	"D,S,T",	0x46600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psllh",	"D,S,T",	0x4b20000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psllh",	"d,t,<",	0x70000034,	0xffe0003f,	WR_d|RD_t,		0,	MMI	},
 {"psllw",	"D,S,T",	0x46400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psllw",	"D,S,T",	0x4b00000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psllw",	"d,t,<",	0x7000003c,	0xffe0003f,	WR_d|RD_t,		0,	MMI	},
 {"psrah",	"D,S,T",	0x46a00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psrah",	"D,S,T",	0x4b60000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psrah",	"d,t,<",	0x70000037,	0xffe0003f,	WR_d|RD_t,		0,	MMI	},
 {"psraw",	"D,S,T",	0x46800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psraw",	"D,S,T",	0x4b40000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psraw",	"d,t,<",	0x7000003f,	0xffe0003f,	WR_d|RD_t,		0,	MMI	},
 {"psrlh",	"D,S,T",	0x46600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psrlh",	"D,S,T",	0x4b20000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psrlh",	"d,t,<",	0x70000036,	0xffe0003f,	WR_d|RD_t,		0,	MMI	},
 {"psrlw",	"D,S,T",	0x46400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psrlw",	"D,S,T",	0x4b00000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psrlw",	"d,t,<",	0x7000003e,	0xffe0003f,	WR_d|RD_t,		0,	MMI	},
 {"psubb",	"D,S,T",	0x47c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psubb",	"D,S,T",	0x4bc00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psubb",	"d,s,t",	0x70000248,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"psubh",	"D,S,T",	0x47400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psubh",	"D,S,T",	0x4b400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psubh",	"d,s,t",	0x70000148,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"psubw",	"D,S,T",	0x47600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psubw",	"D,S,T",	0x4b600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psubw",	"d,s,t",	0x70000048,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"psubd",	"D,S,T",	0x47e00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psubd",	"D,S,T",	0x4be00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubsb",	"D,S,T",	0x47800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psubsb",	"D,S,T",	0x4b800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psubsb",	"d,s,t",	0x70000648,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"psubsh",	"D,S,T",	0x47000001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psubsh",	"D,S,T",	0x4b000001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
+{"psubsh",	"d,s,t",	0x70000548,	0xfc0007ff,	WR_d|RD_s|RD_t,		0,	MMI	},
 {"psubusb",	"D,S,T",	0x47a00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"psubusb",	"D,S,T",	0x4ba00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubush",	"D,S,T",	0x47200001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},