Add iWMMXt support

31 files changed, 1870 insertions, 32 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index e0f41fd..a29b48a 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,26 @@
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* archures.c: Add bfd_mach_arm_iWMMXt.
+	* reloc.c: Add BFD_RELOC_ARM_CP_OFF_IMM_S2.
+	* bfd-in2.h: Regenerate.
+	* libbfd.h: Regenerate.
+	* coff-arm.c (coff_arm_merge_private_bfd_data): Allow iWMMXt
+	object files to be linked with XScale ones.
+	(coff_arm_final_link_postscript): Update note section.
+	* coffcode.h (coff_set_arch_mach_hook): Handle note section.
+	* coffgen.c (coff_real_object_p): Call bfd_coff_set_arch_mach_hook
+	after identifying a coff binary.
+	* cpu-arm.c (processors): Add iWMMXt.
+	(arch_inf): Likewise.
+	* elf32-arm.h (arm_object_p): Handle note section.
+	(elf32_arm_merge_private_bfd_data):  Allow iWMMXt object files to
+	be linked with XScale ones.
+	(elf32_arm_section_flags): New function: Set flags on note section.
+	(elf32_arm_final_write_processing): Handle note section.
+
 2003-03-21  DJ Delorie  <dj@redhat.com>
 
 	* elf32-xstormy16.c (elf32_xstormy16_relocate_section): Call
diff --git a/bfd/archures.c b/bfd/archures.c
index 62edda1..18ebb83 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -235,6 +235,7 @@ DESCRIPTION
 .#define bfd_mach_arm_5TE	9
 .#define bfd_mach_arm_XScale	10
 .#define bfd_mach_arm_ep9312	11
+.#define bfd_mach_arm_iWMMXt	12
 .  bfd_arch_ns32k,     {* National Semiconductors ns32000 *}
 .  bfd_arch_w65,       {* WDC 65816 *}
 .  bfd_arch_tic30,     {* Texas Instruments TMS320C30 *}
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 2385c40..8960f66 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1691,6 +1691,7 @@ enum bfd_architecture
 #define bfd_mach_arm_5TE       9
 #define bfd_mach_arm_XScale    10
 #define bfd_mach_arm_ep9312    11
+#define bfd_mach_arm_iWMMXt    12
   bfd_arch_ns32k,     /* National Semiconductors ns32000 */
   bfd_arch_w65,       /* WDC 65816 */
   bfd_arch_tic30,     /* Texas Instruments TMS320C30 */
@@ -2563,6 +2564,7 @@ field in the instruction.  */
   BFD_RELOC_ARM_SWI,
   BFD_RELOC_ARM_MULTI,
   BFD_RELOC_ARM_CP_OFF_IMM,
+  BFD_RELOC_ARM_CP_OFF_IMM_S2,
   BFD_RELOC_ARM_ADR_IMM,
   BFD_RELOC_ARM_LDR_IMM,
   BFD_RELOC_ARM_LITERAL,
diff --git a/bfd/coff-arm.c b/bfd/coff-arm.c
index 2fadcbe..2401504 100644
--- a/bfd/coff-arm.c
+++ b/bfd/coff-arm.c
@@ -2240,6 +2240,25 @@ coff_arm_merge_private_bfd_data (ibfd, obfd)
   if (ibfd == obfd)
     return TRUE;
 
+  if (bfd_get_mach (obfd) && bfd_get_mach (obfd) != bfd_get_mach (ibfd))
+    {
+      /* For now, allow an output file type of 'xscale' if the
+	 input file type is 'iWMMXt'.  This means that we will
+	 not have to build an entire iWMMXt enabled set of libraries
+	 just to test a iWMMXt enabled binary.  Change the output
+	 type to iWMMXt though.  Similarly allow 'xscale' binaries
+         to be linked into a 'iWMMXt' output binary.  */
+      if (   bfd_get_mach (obfd) == bfd_mach_arm_XScale
+	  && bfd_get_mach (ibfd) == bfd_mach_arm_iWMMXt)
+	bfd_set_arch_mach (obfd, bfd_get_arch (obfd), bfd_mach_arm_iWMMXt);
+      else if (   bfd_get_mach (ibfd) != bfd_mach_arm_XScale
+	       || bfd_get_mach (obfd) != bfd_mach_arm_iWMMXt)
+	{
+	  bfd_set_error (bfd_error_wrong_format);
+	  return FALSE;
+	}
+    }
+
   /* If the two formats are different we cannot merge anything.
      This is not an error, since it is permissable to change the
      input and output formats.  */
@@ -2584,6 +2603,44 @@ coff_arm_final_link_postscript (abfd, pfinfo)
       globals->bfd_of_glue_owner->output_has_begun = TRUE;
     }
 
+  {
+    asection * arm_arch_section;
+
+    /* Look for a .note section.  If one is present check
+       the machine number encoded in it, and set it to the current
+       machine number if it is different.  This allows XScale and
+       iWMMXt binaries to be merged and the resulting output to be set
+       to iWMMXt, even if the first input file had an XScale .note.  */
+
+    arm_arch_section = bfd_get_section_by_name (abfd, ".note");
+
+    if (arm_arch_section != NULL)
+      {
+	char buffer [4];
+
+	if (bfd_get_section_contents (abfd, arm_arch_section, buffer,
+					(file_ptr) 0, sizeof buffer))
+	  {
+	    unsigned long arm_mach;
+
+	    /* We have to extract the value this way to allow for a
+	       host whose endian-ness is different from the target.  */
+	    arm_mach = bfd_get_32 (abfd, buffer);
+  
+	    if (arm_mach != bfd_get_mach (abfd))
+	      {
+		bfd_put_32 (abfd, bfd_get_mach (abfd), buffer);
+
+		if (! bfd_set_section_contents (abfd, arm_arch_section, buffer,
+						(file_ptr) 0, sizeof buffer))
+		  (*_bfd_error_handler)
+		    (_("warning: unable to update contents of .note section in %s"),
+		     bfd_get_filename (abfd));
+	      }
+	  }
+      }
+  }
+
   return TRUE;
 }
 
diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index ee50a10..da8121f 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -1899,6 +1899,27 @@ coff_set_arch_mach_hook (abfd, filehdr)
 	     currently the XScale.  */
         case F_ARM_5:  machine = bfd_mach_arm_XScale;  break;
 	}
+
+      {
+	asection * arm_arch_section;
+  
+	arm_arch_section = bfd_get_section_by_name (abfd, ".note");
+
+	if (arm_arch_section)
+	  {
+	    bfd_byte buffer [4];
+
+	    if (! bfd_get_section_contents (abfd, arm_arch_section, buffer,
+					    (file_ptr) 0, sizeof buffer))
+	      (*_bfd_error_handler)
+		(_("%s: warning: unable to retrieve .note section from %s"),
+		 bfd_get_filename (abfd));
+	      
+	    /* We have to extract the value this way to allow for a
+	       host whose endian-ness is different from the target.  */
+	    machine = bfd_get_32 (abfd, buffer);
+	  }
+      }
       break;
 #endif
 #ifdef MC68MAGIC
diff --git a/bfd/coffgen.c b/bfd/coffgen.c
index c905ab1..a3e3eec 100644
--- a/bfd/coffgen.c
+++ b/bfd/coffgen.c
@@ -226,7 +226,7 @@ coff_real_object_p (abfd, nscns, internal_f, internal_a)
   if (! bfd_coff_set_arch_mach_hook (abfd, (PTR) internal_f))
     goto fail;
 
-  /* Now copy data as required; construct all asections etc */
+  /* Now copy data as required; construct all asections etc.  */
   if (nscns != 0)
     {
       unsigned int i;
@@ -241,6 +241,7 @@ coff_real_object_p (abfd, nscns, internal_f, internal_a)
 	}
     }
 
+  bfd_coff_set_arch_mach_hook (abfd, (PTR) internal_f);
   /*  make_abs_section (abfd); */
 
   return abfd->xvec;
diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c
index 923c250..eb3011d 100644
--- a/bfd/cpu-arm.c
+++ b/bfd/cpu-arm.c
@@ -96,7 +96,8 @@ processors[] =
   { bfd_mach_arm_4,  "strongarm110" },
   { bfd_mach_arm_4,  "strongarm1100" },
   { bfd_mach_arm_XScale, "xscale" },
-  { bfd_mach_arm_ep9312, "ep9312" }
+  { bfd_mach_arm_ep9312, "ep9312" },
+  { bfd_mach_arm_iWMMXt, "iwmmxt" }
 };
 
 static bfd_boolean
@@ -142,7 +143,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (bfd_mach_arm_5T,     "armv5t",  FALSE, & arch_info_struct[8]),
   N (bfd_mach_arm_5TE,    "armv5te", FALSE, & arch_info_struct[9]),
   N (bfd_mach_arm_XScale, "xscale",  FALSE, & arch_info_struct[10]),
-  N (bfd_mach_arm_ep9312, "ep9312",  FALSE, NULL)
+  N (bfd_mach_arm_ep9312, "ep9312",  FALSE, & arch_info_struct[11]),
+  N (bfd_mach_arm_iWMMXt,"iwmmxt",  FALSE, NULL)
 };
 
 const bfd_arch_info_type bfd_arm_arch =
diff --git a/bfd/elf32-arm.h b/bfd/elf32-arm.h
index 509b481..417284b 100644
--- a/bfd/elf32-arm.h
+++ b/bfd/elf32-arm.h
@@ -2119,10 +2119,43 @@ static bfd_boolean
 elf32_arm_object_p (abfd)
      bfd *abfd;
 {
-  /* XXX - we ought to examine a .note section here.  */
+  asection * arm_arch_section;
 
-  if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
-    bfd_default_set_arch_mach (abfd, bfd_arch_arm, bfd_mach_arm_ep9312);
+  arm_arch_section = bfd_get_section_by_name (abfd, ARM_NOTE_SECTION);
+
+  if (arm_arch_section)
+    {
+      char          buffer [4];
+      unsigned long arm_mach;
+
+      if (! bfd_get_section_contents (abfd, arm_arch_section, buffer,
+				      (file_ptr) 0, sizeof buffer))
+	(*_bfd_error_handler)
+	  (_("%s: warning: unable to retrieve %s section from %s"),
+	   ARM_NOTE_SECTION, bfd_get_filename (abfd));
+      else
+	{
+	  /* We have to extract the value this way to allow for a
+	     host whose endian-ness is different from the target.  */
+	  arm_mach = bfd_get_32 (abfd, buffer);
+	  bfd_default_set_arch_mach (abfd, bfd_arch_arm, arm_mach);
+
+	  if (bfd_get_arch (abfd) == bfd_arch_arm)
+	    return TRUE;
+      
+	  /* If the set failed for some reason, do not leave the architecture
+	     type as 0 (unknown), but issue a warning message and force it to
+	     be set to bfd_arch_arm.  */
+	  (*_bfd_error_handler)
+	    (_("%s: warning: unrecognized ARM machine number: %x"),
+	     bfd_get_filename (abfd), arm_mach);
+	}
+    }
+  else
+    {
+      if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
+	bfd_default_set_arch_mach (abfd, bfd_arch_arm, bfd_mach_arm_ep9312);
+    }
 
   return TRUE;
 }
@@ -2263,6 +2296,25 @@ elf32_arm_merge_private_bfd_data (ibfd, obfd)
       return TRUE;
     }
 
+  if (bfd_get_mach (obfd) && bfd_get_mach (obfd) != bfd_get_mach (ibfd))
+    {
+      /* For now, allow an output file type of 'xscale' if the
+	 input file type is 'iWMMXt'.  This means that we will
+	 not have to build an entire iWMMXt enabled set of libraries
+	 just to test a iWMMXt enabled binary.  Change the output
+	 type to iWMMXt though.  Similarly allow 'xscale' binaries
+         to be linked into a 'iWMMXt' output binary.  */
+      if (   bfd_get_mach (obfd) == bfd_mach_arm_XScale
+	  && bfd_get_mach (ibfd) == bfd_mach_arm_iWMMXt)
+	bfd_set_arch_mach (obfd, bfd_get_arch (obfd), bfd_mach_arm_iWMMXt);
+      else if (   bfd_get_mach (ibfd) != bfd_mach_arm_XScale
+	       || bfd_get_mach (obfd) != bfd_mach_arm_iWMMXt)
+	{
+	  bfd_set_error (bfd_error_wrong_format);
+	  return FALSE;
+	}
+    }
+
   /* Identical flags must be compatible.  */
   if (in_flags == out_flags)
     return TRUE;
@@ -3660,6 +3712,65 @@ elf32_arm_reloc_type_class (rela)
     }
 }
 
+static bfd_boolean elf32_arm_section_flags           PARAMS ((flagword *, Elf_Internal_Shdr *));
+static void        elf32_arm_final_write_processing  PARAMS ((bfd *, bfd_boolean));
+
+/* Set the right machine number for an Arm ELF file.  */
+
+static bfd_boolean
+elf32_arm_section_flags (flags, hdr)
+     flagword *flags;
+     Elf_Internal_Shdr *hdr;
+{
+  if (hdr->sh_type == SHT_NOTE)
+    *flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_SAME_CONTENTS;
+
+  return TRUE;
+}
+
+void
+elf32_arm_final_write_processing (abfd, linker)
+     bfd *abfd;
+     bfd_boolean linker ATTRIBUTE_UNUSED;
+{
+  asection *    arm_arch_section;
+  char          buffer [4];
+  unsigned long arm_mach;
+
+  /* Look for a .note.arm.ident section.  If one is present check
+     the machine number encoded in it, and set it to the current
+     machine number if it is different.  This allows XScale and
+     iWMMXt binaries to be merged and the resulting output to be set
+     to iWMMXt, even if the first input file had an XScale .note.  */
+
+  arm_arch_section = bfd_get_section_by_name (abfd, ARM_NOTE_SECTION);
+
+  if (arm_arch_section == NULL)
+    return;
+
+  if (! bfd_get_section_contents (abfd, arm_arch_section, buffer,
+				(file_ptr) 0, sizeof buffer))
+    /* If the ident section does not exist then just skip this check.  */
+    return;
+
+  /* We have to extract the value this way to allow for a
+     host whose endian-ness is different from the target.  */
+  arm_mach = bfd_get_32 (abfd, buffer);
+
+  if (arm_mach == bfd_get_mach (abfd))
+    return;
+
+  bfd_put_32 (abfd, bfd_get_mach (abfd), buffer);
+
+  if (! bfd_set_section_contents (abfd, arm_arch_section, buffer,
+				  (file_ptr) 0, sizeof buffer))
+    (*_bfd_error_handler)
+      (_("warning: unable to update contents of %s section in %s"),
+       ARM_NOTE_SECTION, bfd_get_filename (abfd));
+
+  return;
+}
+
 #define ELF_ARCH			bfd_arch_arm
 #define ELF_MACHINE_CODE		EM_ARM
 #define ELF_MAXPAGESIZE			0x8000
@@ -3685,6 +3796,8 @@ elf32_arm_reloc_type_class (rela)
 #define elf_backend_post_process_headers	elf32_arm_post_process_headers
 #define elf_backend_reloc_type_class		elf32_arm_reloc_type_class
 #define elf_backend_object_p			elf32_arm_object_p
+#define elf_backend_section_flags		elf32_arm_section_flags
+#define elf_backend_final_write_processing      elf32_arm_final_write_processing
 
 #define elf_backend_can_gc_sections 1
 #define elf_backend_plt_readonly    1
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 222b23d..df2ba3e 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1043,6 +1043,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_ARM_SWI",
   "BFD_RELOC_ARM_MULTI",
   "BFD_RELOC_ARM_CP_OFF_IMM",
+  "BFD_RELOC_ARM_CP_OFF_IMM_S2",
   "BFD_RELOC_ARM_ADR_IMM",
   "BFD_RELOC_ARM_LDR_IMM",
   "BFD_RELOC_ARM_LITERAL",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 9f8a952..f4a3321 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -2519,6 +2519,8 @@ ENUMX
 ENUMX
   BFD_RELOC_ARM_CP_OFF_IMM
 ENUMX
+  BFD_RELOC_ARM_CP_OFF_IMM_S2
+ENUMX
   BFD_RELOC_ARM_ADR_IMM
 ENUMX
   BFD_RELOC_ARM_LDR_IMM
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2dc1b47..9adca8b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,29 @@
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* config/tc-arm.c: (ARM_CEXT_IWMMXT, ARM_ARCH_IWMMXT, WR_PREFIX,
+	WC_PREFIX, REG_TYPE_IWMMXT): New constants.
+	(enum wreg_type, enum iwmmxt_insn_type): New types.
+	(wr_register, wc_register, wcg_register): New macros.
+	(iwmmxt_table): New variable.
+	(wreg_required_here, do_iwmmxt_byte_addr, do_iwmmxt_tandc,
+	do_iwmmxt_tbcst, do_iwmmxt_textrc, do_iwmmxt_textrm,
+	do_iwmmxt_tinsr, do_iwmmxt_tmcr, do_iwmmxt_tmcrr, do_iwmmxt_tmia,
+	do_iwmmxt_tmovmsk, do_iwmmxt_tmrc, do_iwmmxt_tmrrc,
+	do_iwmmxt_torc, do_iwmmxt_waligni, do_iwmmxt_wmov,
+	do_iwmmxt_word_addr, do_iwmmxt_wrwr, do_iwmmxt_wrwrwcg,
+	do_iwmmxt_wrwrwr, do_iwmmxt_wshufh, do_iwmmxt_wzero,
+	cp_byte_address_offset, cp_byte_address_required_here,
+	check_iwmmxt_insn): New	functions.
+	(asm_opcode_insns): Add iWMMXt instructions.	
+	(md_begin): Set the mach value for iWMMXt targets.  Create a note
+	section to identify iwmmxt binaries.
+	(md_apply_fix3): Handle BFD_RELOC_ARM_CP_OFF_IMM_S2.
+	* doc/c-arm.texi: Document the support for the iWMMXt.
+	* NEWS: Mention new support.
+
 2003-03-24  Daniel Néri  <dne@mayonnaise.net>
 
 	* doc/as.texinfo: Rename the all occurances of C54X to TIC54X.
diff --git a/gas/NEWS b/gas/NEWS
index 703b4e1..5a92f3c 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Support for Intel's iWMMXt processor (an ARM variant) added.
+
 * An assembler test generator has been contributed and an example file that
   uses it (gas/testsuite/gas/all/test-gen.c and test-exmaple.c).
   
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 40d35d7..b9935e7 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -59,6 +59,7 @@
 /* Co-processor space extensions.  */
 #define ARM_CEXT_XSCALE   0x00800000	/* Allow MIA etc.          */
 #define ARM_CEXT_MAVERICK 0x00400000	/* Use Cirrus/DSP coprocessor.  */
+#define ARM_CEXT_IWMMXT   0x00200000    /* Intel(r) Wireless MMX(tm) technology coprocessor.   */
 
 /* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
    defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@@ -84,6 +85,7 @@
 
 /* Processors with specific extensions in the co-processor space.  */
 #define ARM_ARCH_XSCALE	(ARM_ARCH_V5TE	| ARM_CEXT_XSCALE)
+#define ARM_ARCH_IWMMXT	(ARM_ARCH_V5TE	| ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
 
 /* Some useful combinations:  */
 #define ARM_ANY		0x0000ffff	/* Any basic core.  */
@@ -499,6 +501,35 @@ static const struct asm_psr psrs[] =
   {"SPSR_cxsf",	FALSE, PSR_c | PSR_x | PSR_s | PSR_f},
 };
 
+enum wreg_type
+  {
+    IWMMXT_REG_WR = 0,
+    IWMMXT_REG_WC = 1,
+    IWMMXT_REG_WR_OR_WC = 2,
+    IWMMXT_REG_WCG
+  };
+
+enum iwmmxt_insn_type
+{
+  check_rd,
+  check_wr,
+  check_wrwr,
+  check_wrwrwr,
+  check_wrwrwcg,
+  check_tbcst,
+  check_tmovmsk,
+  check_tmia,
+  check_tmcrr,
+  check_tmrrc,
+  check_tmcr,
+  check_tmrc,
+  check_tinsr,
+  check_textrc,
+  check_waligni,
+  check_textrm,
+  check_wshufh
+};
+
 enum vfp_dp_reg_pos
 {
   VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
@@ -543,6 +574,10 @@ struct reg_entry
 #define REG_LR  14
 #define REG_PC	15
 
+#define wr_register(reg)  ((reg ^ WR_PREFIX) >= 0 && (reg ^ WR_PREFIX) <= 15)
+#define wc_register(reg)  ((reg ^ WC_PREFIX) >= 0 && (reg ^ WC_PREFIX) <= 15)
+#define wcg_register(reg) ((reg ^ WC_PREFIX) >= 8 && (reg ^ WC_PREFIX) <= 11)
+
 /* These are the standard names.  Users can add aliases with .req.  */
 /* Integer Register Numbers.  */
 static const struct reg_entry rn_table[] =
@@ -562,6 +597,40 @@ static const struct reg_entry rn_table[] =
   {NULL, 0}
 };
 
+#define WR_PREFIX 0x200
+#define WC_PREFIX 0x400
+
+static const struct reg_entry iwmmxt_table[] =
+{
+  /* Intel(r) Wireless MMX(tm) technology register names.  */
+  {  "wr0", 0x0 | WR_PREFIX},   {"wr1", 0x1 | WR_PREFIX},
+  {  "wr2", 0x2 | WR_PREFIX},   {"wr3", 0x3 | WR_PREFIX},
+  {  "wr4", 0x4 | WR_PREFIX},   {"wr5", 0x5 | WR_PREFIX},
+  {  "wr6", 0x6 | WR_PREFIX},   {"wr7", 0x7 | WR_PREFIX},
+  {  "wr8", 0x8 | WR_PREFIX},   {"wr9", 0x9 | WR_PREFIX},
+  { "wr10", 0xa | WR_PREFIX},  {"wr11", 0xb | WR_PREFIX},
+  { "wr12", 0xc | WR_PREFIX},  {"wr13", 0xd | WR_PREFIX},
+  { "wr14", 0xe | WR_PREFIX},  {"wr15", 0xf | WR_PREFIX},
+  { "wcid", 0x0 | WC_PREFIX},  {"wcon", 0x1 | WC_PREFIX},
+  {"wcssf", 0x2 | WC_PREFIX}, {"wcasf", 0x3 | WC_PREFIX},
+  {"wcgr0", 0x8 | WC_PREFIX}, {"wcgr1", 0x9 | WC_PREFIX},
+  {"wcgr2", 0xa | WC_PREFIX}, {"wcgr3", 0xb | WC_PREFIX},
+
+  {  "wR0", 0x0 | WR_PREFIX},   {"wR1", 0x1 | WR_PREFIX},
+  {  "wR2", 0x2 | WR_PREFIX},   {"wR3", 0x3 | WR_PREFIX},
+  {  "wR4", 0x4 | WR_PREFIX},   {"wR5", 0x5 | WR_PREFIX},
+  {  "wR6", 0x6 | WR_PREFIX},   {"wR7", 0x7 | WR_PREFIX},
+  {  "wR8", 0x8 | WR_PREFIX},   {"wR9", 0x9 | WR_PREFIX},
+  { "wR10", 0xa | WR_PREFIX},  {"wR11", 0xb | WR_PREFIX},
+  { "wR12", 0xc | WR_PREFIX},  {"wR13", 0xd | WR_PREFIX},
+  { "wR14", 0xe | WR_PREFIX},  {"wR15", 0xf | WR_PREFIX},
+  { "wCID", 0x0 | WC_PREFIX},  {"wCon", 0x1 | WC_PREFIX},
+  {"wCSSF", 0x2 | WC_PREFIX}, {"wCASF", 0x3 | WC_PREFIX},
+  {"wCGR0", 0x8 | WC_PREFIX}, {"wCGR1", 0x9 | WC_PREFIX},
+  {"wCGR2", 0xa | WC_PREFIX}, {"wCGR3", 0xb | WC_PREFIX},
+  {NULL, 0}
+};
+
 /* Co-processor Numbers.  */
 static const struct reg_entry cp_table[] =
 {
@@ -690,6 +759,7 @@ struct reg_map all_reg_maps[] =
   {mav_mvdx_table,  15, NULL, N_("Maverick MVFX register expected")},
   {mav_mvax_table,   3, NULL, N_("Maverick MVAX register expected")},
   {mav_dspsc_table,  0, NULL, N_("Maverick DSPSC register expected")},
+  {iwmmxt_table,    23, NULL, N_("Intel(r) Wireless MMX(tm) technology register expected")},
 };
 
 /* Enumeration matching entries in table above.  */
@@ -708,8 +778,9 @@ enum arm_reg_type
   REG_TYPE_MVDX = 9,
   REG_TYPE_MVAX = 10,
   REG_TYPE_DSPSC = 11,
+  REG_TYPE_IWMMXT = 12,
 
-  REG_TYPE_MAX = 12
+  REG_TYPE_MAX = 13
 };
 
 /* Functions called by parser.  */
@@ -938,6 +1009,31 @@ static symbolS * find_real_start PARAMS ((symbolS *));
 static bfd_reloc_code_real_type	arm_parse_reloc PARAMS ((void));
 #endif
 
+static int wreg_required_here   PARAMS ((char **, int, enum wreg_type));
+static void do_iwmmxt_byte_addr PARAMS ((char *));
+static void do_iwmmxt_tandc     PARAMS ((char *));
+static void do_iwmmxt_tbcst     PARAMS ((char *));
+static void do_iwmmxt_textrc    PARAMS ((char *));
+static void do_iwmmxt_textrm    PARAMS ((char *));
+static void do_iwmmxt_tinsr     PARAMS ((char *));
+static void do_iwmmxt_tmcr      PARAMS ((char *));
+static void do_iwmmxt_tmcrr     PARAMS ((char *));
+static void do_iwmmxt_tmia      PARAMS ((char *));
+static void do_iwmmxt_tmovmsk   PARAMS ((char *));
+static void do_iwmmxt_tmrc      PARAMS ((char *));
+static void do_iwmmxt_tmrrc     PARAMS ((char *));
+static void do_iwmmxt_torc      PARAMS ((char *));
+static void do_iwmmxt_waligni   PARAMS ((char *));
+static void do_iwmmxt_wmov      PARAMS ((char *));
+static void do_iwmmxt_word_addr PARAMS ((char *));
+static void do_iwmmxt_wrwr      PARAMS ((char *));
+static void do_iwmmxt_wrwrwcg   PARAMS ((char *));
+static void do_iwmmxt_wrwrwr    PARAMS ((char *));
+static void do_iwmmxt_wshufh    PARAMS ((char *));
+static void do_iwmmxt_wzero     PARAMS ((char *));
+static int cp_byte_address_offset         PARAMS ((char **));
+static int cp_byte_address_required_here  PARAMS ((char **));
+
 /* ARM instructions take 4bytes in the object file, Thumb instructions
    take 2:  */
 #define INSN_SIZE       4
@@ -981,6 +1077,170 @@ struct asm_opcode
 
 static const struct asm_opcode insns[] =
 {
+  /* Intel(r) Wireless MMX(tm) technology instructions.  */
+  {"tandcb",     0xee130130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
+  {"tandch",     0xee530130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
+  {"tandcw",     0xee930130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
+  {"tbcstb",     0xee400010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
+  {"tbcsth",     0xee400050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
+  {"tbcstw",     0xee400090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
+  {"textrcb",    0xee130170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
+  {"textrch",    0xee530170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
+  {"textrcw",    0xee930170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
+  {"textrmub",   0xee100070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+  {"textrmuh",   0xee500070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+  {"textrmuw",   0xee900070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+  {"textrmsb",   0xee100078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+  {"textrmsh",   0xee500078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+  {"textrmsw",   0xee900078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+  {"tinsrb",     0xee600010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
+  {"tinsrh",     0xee600050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
+  {"tinsrw",     0xee600090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
+  {"tmcr",       0xee000110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmcr},
+  {"tmcrr",      0xec400000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmcrr},
+  {"tmia",       0xee200010, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+  {"tmiaph",     0xee280010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+  {"tmiabb",     0xee2c0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+  {"tmiabt",     0xee2d0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+  {"tmiatb",     0xee2e0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+  {"tmiatt",     0xee2f0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+  {"tmovmskb",   0xee100030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
+  {"tmovmskh",   0xee500030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
+  {"tmovmskw",   0xee900030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
+  {"tmrc",       0xee100110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmrc},
+  {"tmrrc",      0xec500000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmrrc},
+  {"torcb",      0xee130150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
+  {"torch",      0xee530150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
+  {"torcw",      0xee930150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
+  {"waccb",      0xee0001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wacch",      0xee4001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"waccw",      0xee8001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"waddbss",    0xee300180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddb",      0xee000180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddbus",    0xee100180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddhss",    0xee700180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddh",      0xee400180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddhus",    0xee500180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddwss",    0xeeb00180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddw",      0xee800180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waddwus",    0xee900180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"waligni",    0xee000020, 7, ARM_CEXT_IWMMXT, do_iwmmxt_waligni},
+  {"walignr0",   0xee800020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"walignr1",   0xee900020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"walignr2",   0xeea00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"walignr3",   0xeeb00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wand",       0xee200000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wandn",      0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wavg2b",     0xee800000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wavg2br",    0xee900000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wavg2h",     0xeec00000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wavg2hr",    0xeed00000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpeqb",    0xee000060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpeqh",    0xee400060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpeqw",    0xee800060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpgtub",   0xee100060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpgtuh",   0xee500060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpgtuw",   0xee900060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpgtsb",   0xee300060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpgtsh",   0xee700060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wcmpgtsw",   0xeeb00060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wldrb",      0xec100000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+  {"wldrh",      0xec100100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+  {"wldrw",      0xec100200, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+  {"wldrd",      0xec100300, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+  {"wmacs",      0xee600100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmacsz",     0xee700100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmacu",      0xee400100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmacuz",     0xee500100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmadds",     0xeea00100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmaddu",     0xee800100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmaxsb",     0xee200160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmaxsh",     0xee600160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmaxsw",     0xeea00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmaxub",     0xee000160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmaxuh",     0xee400160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmaxuw",     0xee800160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wminsb",     0xee300160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wminsh",     0xee700160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wminsw",     0xeeb00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wminub",     0xee100160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wminuh",     0xee500160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wminuw",     0xee900160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmov",       0xee000000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wmov},
+  {"wmulsm",     0xee300100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmulsl",     0xee200100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmulum",     0xee100100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wmulul",     0xee000100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wor",        0xee000000, 3, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wpackhss",   0xee700080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wpackhus",   0xee500080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wpackwss",   0xeeb00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wpackwus",   0xee900080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wpackdss",   0xeef00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wpackdus",   0xeed00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wrorh",      0xee700040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wrorhg",     0xee700148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wrorw",      0xeeb00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wrorwg",     0xeeb00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wrord",      0xeef00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wrordg",     0xeef00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsadb",      0xee000120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsadbz",     0xee100120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsadh",      0xee400120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsadhz",     0xee500120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wshufh",     0xee0001e0, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wshufh},
+  {"wsllh",      0xee500040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsllhg",     0xee500148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsllw",      0xee900040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsllwg",     0xee900148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wslld",      0xeed00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wslldg",     0xeed00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsrah",      0xee400040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsrahg",     0xee400148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsraw",      0xee800040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsrawg",     0xee800148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsrad",      0xeec00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsradg",     0xeec00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsrlh",      0xee600040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsrlhg",     0xee600148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsrlw",      0xeea00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsrlwg",     0xeea00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wsrld",      0xeee00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsrldg",     0xeee00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+  {"wstrb",      0xec000000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+  {"wstrh",      0xec000100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+  {"wstrw",      0xec000200, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+  {"wstrd",      0xec000300, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+  {"wsubbss",    0xee3001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubb",      0xee0001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubbus",    0xee1001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubhss",    0xee7001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubh",      0xee4001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubhus",    0xee5001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubwss",    0xeeb001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubw",      0xee8001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wsubwus",    0xee9001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wunpckehub", 0xee0000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckehuh", 0xee4000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckehuw", 0xee8000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckehsb", 0xee2000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckehsh", 0xee6000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckehsw", 0xeea000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckihb",  0xee1000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wunpckihh",  0xee5000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wunpckihw",  0xee9000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wunpckelub", 0xee0000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckeluh", 0xee4000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckeluw", 0xee8000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckelsb", 0xee2000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckelsh", 0xee6000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckelsw", 0xeea000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+  {"wunpckilb",  0xee1000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wunpckilh",  0xee5000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wunpckilw",  0xee9000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wxor",       0xee100000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+  {"wzero",      0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wzero},
+
   /* Core ARM Instructions.  */
   {"and",        0xe0000000, 3,  ARM_EXT_V1,       do_arit},
   {"ands",       0xe0100000, 3,  ARM_EXT_V1,       do_arit},
@@ -2739,6 +2999,57 @@ reg_required_here (str, shift)
   return FAIL;
 }
 
+/* A Intel(r) Wireless MMX(tm) technology register
+   must be given at this point.
+   Shift is the place to put it in inst.instruction.
+   Restores input start point on err.
+   Returns the reg#, or FAIL.  */
+
+static int
+wreg_required_here (str, shift, reg_type)
+     char ** str;
+     int     shift;
+     enum wreg_type reg_type;
+{
+  static char buff [128];
+  int    reg;
+  char * start = *str;
+
+  if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_IWMMXT].htab)) != FAIL)
+    {
+      if (wr_register (reg)
+	  && (reg_type == IWMMXT_REG_WR || reg_type == IWMMXT_REG_WR_OR_WC))
+        {
+          if (shift >= 0)
+            inst.instruction |= (reg ^ WR_PREFIX) << shift;
+          return reg;
+        }
+      else if (wc_register (reg)
+	       && (reg_type == IWMMXT_REG_WC || reg_type == IWMMXT_REG_WR_OR_WC))
+        {
+          if (shift >= 0)
+            inst.instruction |= (reg ^ WC_PREFIX) << shift;
+          return reg;
+        }
+      else if ((wcg_register (reg) && reg_type == IWMMXT_REG_WCG))
+        {
+          if (shift >= 0)
+            inst.instruction |= ((reg ^ WC_PREFIX) - 8) << shift;
+          return reg;
+        }
+    }
+
+  /* Restore the start point, we may have got a reg of the wrong class.  */
+  *str = start;
+
+  /* In the few cases where we might be able to accept
+     something else this error can be overridden.  */
+  sprintf (buff, _("Intel(r) Wireless MMX(tm) technology register expected, not '%.100s'"), start);
+  inst.error = buff;
+
+  return FAIL;
+}
+
 static const struct asm_psr *
 arm_psr_parse (ccp)
      register char ** ccp;
@@ -3076,6 +3387,144 @@ cp_address_required_here (str, wb_ok)
   return SUCCESS;
 }
 
+static int
+cp_byte_address_offset (str)
+     char ** str;
+{
+  int offset;
+
+  skip_whitespace (* str);
+
+  if (! is_immediate_prefix (**str))
+    {
+      inst.error = _("immediate expression expected");
+      return FAIL;
+    }
+
+  (*str)++;
+  
+  if (my_get_expression (& inst.reloc.exp, str))
+    return FAIL;
+  
+  if (inst.reloc.exp.X_op == O_constant)
+    {
+      offset = inst.reloc.exp.X_add_number;
+      
+      if (offset > 255 || offset < -255)
+        {
+          inst.error = _("offset too large");
+          return FAIL;
+        }
+
+      if (offset >= 0)
+        inst.instruction |= INDEX_UP;
+      else
+        offset = -offset;
+
+      inst.instruction |= offset;
+    }
+  else
+    inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM_S2;
+
+  return SUCCESS;
+}
+
+static int
+cp_byte_address_required_here (str)
+     char ** str;
+{
+  char * p = * str;
+  int    pre_inc = 0;
+  int    write_back = 0;
+
+  if (*p == '[')
+    {
+      int reg;
+
+      p++;
+      skip_whitespace (p);
+
+      if ((reg = reg_required_here (& p, 16)) == FAIL)
+        return FAIL;
+
+      skip_whitespace (p);
+
+      if (*p == ']')
+        {
+          p++;
+          
+          if (skip_past_comma (& p) == SUCCESS)
+            {
+              /* [Rn], #expr */
+              write_back = WRITE_BACK;
+              
+              if (reg == REG_PC)
+                {
+                  inst.error = _("pc may not be used in post-increment");
+                  return FAIL;
+                }
+
+              if (cp_byte_address_offset (& p) == FAIL)
+                return FAIL;
+            }
+          else
+            pre_inc = PRE_INDEX | INDEX_UP;
+        }
+      else
+        {
+          /* '['Rn, #expr']'[!] */
+
+          if (skip_past_comma (& p) == FAIL)
+            {
+              inst.error = _("pre-indexed expression expected");
+              return FAIL;
+            }
+
+          pre_inc = PRE_INDEX;
+          
+          if (cp_byte_address_offset (& p) == FAIL)
+            return FAIL;
+
+          skip_whitespace (p);
+
+          if (*p++ != ']')
+            {
+              inst.error = _("missing ]");
+              return FAIL;
+            }
+
+          skip_whitespace (p);
+
+          if (*p == '!')
+            {
+              if (reg == REG_PC)
+                {
+                  inst.error = _("pc may not be used with write-back");
+                  return FAIL;
+                }
+
+              p++;
+              write_back = WRITE_BACK;
+            }
+        }
+    }
+  else
+    {
+      if (my_get_expression (&inst.reloc.exp, &p))
+        return FAIL;
+
+      inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM_S2;
+      inst.reloc.exp.X_add_number -= 8;  /* PC rel adjust.  */
+      inst.reloc.pc_rel = 1;
+      inst.instruction |= (REG_PC << 16);
+      pre_inc = PRE_INDEX;
+    }
+
+  inst.instruction |= write_back | pre_inc;
+  *str = p;
+  return SUCCESS;
+}
+
 static void
 do_empty (str)
      char * str;
@@ -4141,6 +4590,449 @@ do_bkpt (str)
   end_of_line (str);
 }
 
+static unsigned long check_iwmmxt_insn PARAMS ((char *, enum iwmmxt_insn_type, int));
+
+/* Parse INSN_TYPE insn STR having a possible IMMEDIATE_SIZE immediate.  */
+
+static unsigned long
+check_iwmmxt_insn (str, insn_type, immediate_size)
+     char * str;
+     enum iwmmxt_insn_type insn_type;
+     int immediate_size;
+{
+  int reg = 0;
+  const char *  inst_error;
+  expressionS expr;
+  unsigned long number;
+
+  inst_error = inst.error;
+  if (!inst.error)
+    inst.error = BAD_ARGS;
+  skip_whitespace (str);
+
+  switch (insn_type)
+    {
+    case check_rd:
+      if ((reg = reg_required_here (&str, 12)) == FAIL)
+	return FAIL;
+      break;
+      
+    case check_wr:
+       if ((wreg_required_here (&str, 0, IWMMXT_REG_WR)) == FAIL)
+	 return FAIL;
+       break;
+       
+    case check_wrwr:
+      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_wrwrwr:
+      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_wrwrwcg:
+      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 0, IWMMXT_REG_WCG) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tbcst:
+      if ((wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 12) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tmovmsk:
+      if ((reg_required_here (&str, 12) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tmia:
+      if ((wreg_required_here (&str, 5, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 0) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 12) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tmcrr:
+      if ((wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 12) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 16) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tmrrc:
+      if ((reg_required_here (&str, 12) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 16) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tmcr:
+      if ((wreg_required_here (&str, 16, IWMMXT_REG_WC) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 12) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tmrc:
+      if ((reg_required_here (&str, 12) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WC) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_tinsr:
+      if ((wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || reg_required_here (&str, 12) == FAIL
+	   || skip_past_comma (&str) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_textrc:
+      if ((reg_required_here (&str, 12) == FAIL
+	   || skip_past_comma (&str) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_waligni:
+      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_textrm:
+      if ((reg_required_here (&str, 12) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL))
+	return FAIL;
+      break;
+      
+    case check_wshufh:
+      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL
+	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+	   || skip_past_comma (&str) == FAIL))
+	return FAIL;
+      break;
+    }
+  
+  if (immediate_size == 0)
+    {
+      end_of_line (str);
+      inst.error = inst_error;
+      return reg;
+    }
+  else
+    {
+      skip_whitespace (str);      
+  
+      /* Allow optional leading '#'. */
+      if (is_immediate_prefix (* str))
+        str++;
+
+      memset (& expr, '\0', sizeof (expr));
+  
+      if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
+        {
+          inst.error = _("bad or missing expression");
+          return FAIL;
+        }
+  
+      number = expr.X_add_number;
+  
+      if (number != (number & immediate_size))
+        {
+          inst.error = _("immediate value out of range");
+          return FAIL;
+        }
+      end_of_line (str);
+      inst.error = inst_error;
+      return number;
+    }
+}
+
+static void
+do_iwmmxt_byte_addr (str)
+     char * str;
+{
+  int op = (inst.instruction & 0x300) >> 8;
+  int reg;
+
+  inst.instruction &= ~0x300;
+  inst.instruction |= (op & 1) << 22 | (op & 2) << 7;  
+
+  skip_whitespace (str);
+
+  if ((reg = wreg_required_here (&str, 12, IWMMXT_REG_WR_OR_WC)) == FAIL
+      || skip_past_comma (& str) == FAIL
+      || cp_byte_address_required_here (&str) == FAIL)
+    {
+      if (! inst.error)
+        inst.error = BAD_ARGS;
+    }
+  else
+    end_of_line (str);
+
+  if (wc_register (reg))
+    {
+      inst.instruction |=  0xf0000100;
+      inst.instruction &= ~0x00400000;
+    }
+}
+
+static void
+do_iwmmxt_tandc (str)
+     char * str;
+{
+  int reg;
+
+  reg = check_iwmmxt_insn (str, check_rd, 0);
+
+  if (reg != REG_PC && !inst.error)
+    inst.error = _("only r15 allowed here");
+  return;
+}
+
+static void
+do_iwmmxt_tbcst (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_tbcst, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_textrc (str)
+     char * str;
+{
+  unsigned long number;
+
+  if ((number = check_iwmmxt_insn (str, check_textrc, 7)) == (unsigned long) FAIL)
+    return;
+
+  inst.instruction |= number & 0x7;
+  return;
+}
+
+static void
+do_iwmmxt_textrm (str)
+     char * str;
+{
+  unsigned long number;
+
+  if ((number = check_iwmmxt_insn (str, check_textrm, 7)) == (unsigned long) FAIL)
+    return;
+
+  inst.instruction |= number & 0x7;
+}
+
+static void
+do_iwmmxt_tinsr (str)
+     char * str;
+{
+  unsigned long number;
+
+  if ((number = check_iwmmxt_insn (str, check_tinsr, 7)) == (unsigned long) FAIL)
+    return;
+
+  inst.instruction |= number & 0x7;
+  return;
+}
+
+static void
+do_iwmmxt_tmcr (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_tmcr, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_tmcrr (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_tmcrr, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_tmia (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_tmia, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_tmovmsk (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_tmovmsk, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_tmrc (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_tmrc, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_tmrrc (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_tmrrc, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_torc (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_rd, 0);
+  return;
+}
+
+static void
+do_iwmmxt_waligni (str)
+     char * str;
+{
+  unsigned long number;
+
+  if ((number = check_iwmmxt_insn (str, check_waligni, 7)) == (unsigned long) FAIL)
+    return;
+
+  inst.instruction |= ((number & 0x7) << 20);
+  return;
+}
+
+static void
+do_iwmmxt_wmov (str)
+     char * str;
+{
+  if (check_iwmmxt_insn (str, check_wrwr, 0) == (unsigned long) FAIL)
+    return;
+  
+  inst.instruction |= ((inst.instruction >> 16) & 0xf);
+  return;
+}
+
+static void
+do_iwmmxt_word_addr (str)
+     char * str;
+{
+  int op = (inst.instruction & 0x300) >> 8;
+  int reg;
+
+  inst.instruction &= ~0x300;
+  inst.instruction |= (op & 1) << 22 | (op & 2) << 7;  
+
+  skip_whitespace (str);
+
+  if ((reg = wreg_required_here (&str, 12, IWMMXT_REG_WR_OR_WC)) == FAIL
+      || skip_past_comma (& str) == FAIL
+      || cp_address_required_here (& str, CP_WB_OK) == FAIL)
+    {
+      if (! inst.error)
+        inst.error = BAD_ARGS;
+    }
+  else
+    end_of_line (str);
+
+  if (wc_register (reg))
+    {
+      inst.instruction |=  0xf0000100;
+      inst.instruction &= ~0x00400000;
+    }
+}
+
+static void
+do_iwmmxt_wrwr (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_wrwr, 0);
+  
+  return;
+}
+
+static void
+do_iwmmxt_wrwrwcg (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_wrwrwcg, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_wrwrwr (str)
+     char * str;
+{
+  check_iwmmxt_insn (str, check_wrwrwr, 0);
+
+  return;
+}
+
+static void
+do_iwmmxt_wshufh (str)
+     char * str;
+{
+  unsigned long number;
+
+  if ((number = check_iwmmxt_insn (str, check_wshufh, 0xff)) == (unsigned long) FAIL)
+    return;
+
+  inst.instruction |= ((number & 0xf0) << 16) | (number & 0xf);
+  return;
+}
+
+static void
+do_iwmmxt_wzero (str)
+     char * str;
+{
+  if (check_iwmmxt_insn (str, check_wr, 0) == (unsigned long) FAIL)
+    return;
+
+  inst.instruction |= ((inst.instruction & 0xf) << 12) | ((inst.instruction & 0xf) << 16);
+  return;
+}
+
 /* Xscale multiply-accumulate (argument parse)
      MIAcc   acc0,Rm,Rs
      MIAPHcc acc0,Rm,Rs
@@ -9329,7 +10221,9 @@ md_begin ()
     }
 
   /* Catch special cases.  */
-  if (cpu_variant & ARM_CEXT_XSCALE)
+  if (cpu_variant & ARM_CEXT_IWMMXT)
+    mach = bfd_mach_arm_iWMMXt;
+  else if (cpu_variant & ARM_CEXT_XSCALE)
     mach = bfd_mach_arm_XScale;
   else if (cpu_variant & ARM_CEXT_MAVERICK)
     mach = bfd_mach_arm_ep9312;
@@ -9352,6 +10246,33 @@ md_begin ()
   else if (cpu_variant & ARM_EXT_V3M)
     mach = bfd_mach_arm_3M;
 
+#if defined (OBJ_ELF) || defined (OBJ_COFF)
+  {
+    expressionS exp;
+    segT current_seg = now_seg;
+    subsegT current_subseg = now_subseg;
+    asection * arm_arch;
+    
+    arm_arch = bfd_make_section_old_way (stdoutput, ARM_NOTE_SECTION);
+
+#ifdef OBJ_COFF
+    bfd_set_section_flags (stdoutput, arm_arch,
+			   SEC_DATA | SEC_ALLOC | SEC_LOAD | SEC_LINK_ONCE \
+			   | SEC_HAS_CONTENTS);
+#endif
+    arm_arch->output_section = arm_arch;
+    subseg_set (arm_arch, 0);
+    exp.X_op = O_constant;
+    exp.X_add_number = mach;
+    exp.X_add_symbol = NULL;
+    exp.X_op_symbol = NULL;
+
+    emit_expr (&exp, 4);
+
+    subseg_set (current_seg, current_subseg);
+  }
+#endif
+
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
 }
 
@@ -10064,6 +10985,18 @@ md_apply_fix3 (fixP, valP, seg)
       md_number_to_chars (buf, newval, INSN_SIZE);
       break;
 
+    case BFD_RELOC_ARM_CP_OFF_IMM_S2:
+      sign = value >= 0;
+      if (value < -255 || value > 255)
+        as_bad_where (fixP->fx_file, fixP->fx_line,
+                      _("Illegal value for co-processor offset"));
+      if (value < 0)
+        value = -value;
+      newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
+      newval |= value | (sign ?  INDEX_UP : 0);
+      md_number_to_chars (buf, newval , INSN_SIZE);
+      break;
+
     case BFD_RELOC_ARM_THUMB_OFFSET:
       newval = md_chars_to_number (buf, THUMB_SIZE);
       /* Exactly what ranges, and where the offset is inserted depends
@@ -10722,6 +11655,7 @@ struct arm_option_table arm_opts[] =
   {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
    N_("use -mcpu=strongarm1110")},
   {"mxscale",	 NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
+  {"miwmmxt",	 NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
   {"mall",	 NULL, &legacy_cpu, ARM_ANY,      N_("use -mcpu=all")},
 
   /* Architecture variants -- don't add any more to this list either.  */
@@ -10826,6 +11760,7 @@ static struct arm_cpu_option_table arm_cpus[] =
   {"arm1020e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2},
   /* ??? XSCALE is really an architecture.  */
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
+  {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
   {"i80200",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
   /* Maverick */
   {"ep9312",		ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_NONE},
@@ -10875,6 +11810,7 @@ static struct arm_arch_extension_table arm_extensions[] =
 {
   {"maverick",		ARM_CEXT_MAVERICK},
   {"xscale",		ARM_CEXT_XSCALE},
+  {"iwmmxt",		ARM_CEXT_IWMMXT},
   {NULL,		0}
 };
 
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 5b67f97..15d928a 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -91,6 +91,7 @@ recognized:
 @code{arm1020e}, 
 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
 @code{i80200} (Intel XScale processor)
+@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
 and
 @code{xscale}.  
 The special name @code{all} may be used to allow the
@@ -102,6 +103,7 @@ co-processor instruction space.  For example, @code{-mcpu=arm920+maverick}
 is equivalent to specifying @code{-mcpu=ep9312}.  The following extensions
 are currently supported: 
 @code{+maverick}
+@code{+iwmmxt}
 and
 @code{+xscale}.
 
@@ -126,6 +128,7 @@ names are recognized:
 @code{armv5txm},
 @code{armv5te},
 @code{armv5texp}
+@code{iwmmxt}
 and
 @code{xscale}.
 If both @code{-mcpu} and
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index a8925de..6f1f320 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* gas/arm/arm.exp: Run iwmmxt test.
+	* gas/arm/iwmmxt.s: New test source file.
+	* gas/arm/iwmmxt.d: New test expected results file.
+	* gas/elf/elf.exp: Fix section2 test to cope with note section.
+	* gas/eld/section2.e-miwxxmt: New test expected results file.
+
 2003-03-12  Alexandre Oliva  <aoliva@redhat.com>
 
 	* gas/mips/branch-misc-2.s: Add branch to symbol in another
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index 152d515..94a5cf9 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -44,7 +44,7 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
 
     gas_test "immed.s" "" $stdoptlist "immediate expressions"
 
-    gas_test "float.s" "" $stdoptlist "Core floating point instructions"
+    gas_test "float.s" "-mcpu=arm7tdmi" $stdoptlist "Core floating point instructions"
 
     run_dump_test "fpa-monadic"
 
@@ -79,3 +79,6 @@ if [istarget arm-*-pe] {
     #run_dump_test "be-fpconst"
 }
 
+if [istarget xscale-*] {
+    run_dump_test "iwmmxt"
+}
diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d
new file mode 100644
index 0000000..1e0f4db
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt.d
@@ -0,0 +1,168 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Intel(r) Wireless MMX(tm) technology instructions
+#as: -mcpu=xscale+iwmmxt -EL
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <iwmmxt> ee13f130[ 	]+tandcb[ 	]+pc
+0+04 <[^>]*> de53f130[ 	]+tandchle[ 	]+pc
+0+08 <[^>]*> ae93f130[ 	]+tandcwge[ 	]+pc
+0+0c <[^>]*> be401010[ 	]+tbcstblt[ 	]+wr0, r1
+0+10 <[^>]*> ee412050[ 	]+tbcsth[ 	]+wr1, r2
+0+14 <[^>]*> ce423090[ 	]+tbcstwgt[ 	]+wr2, r3
+0+18 <[^>]*> ee13f177[ 	]+textrcb[ 	]+pc, #7
+0+1c <[^>]*> 0e53f172[ 	]+textrcheq[ 	]+pc, #2
+0+20 <[^>]*> ee93f170[ 	]+textrcw[ 	]+pc, #0
+0+24 <[^>]*> ee13e076[ 	]+textrmub[ 	]+lr, wr3, #6
+0+28 <[^>]*> 1e14d07d[ 	]+textrmsbne[ 	]+sp, wr4, #5
+0+2c <[^>]*> ee55c072[ 	]+textrmuh[ 	]+ip, wr5, #2
+0+30 <[^>]*> ee56b078[ 	]+textrmsh[ 	]+fp, wr6, #0
+0+34 <[^>]*> 2e97a071[ 	]+textrmuwcs[ 	]+sl, wr7, #1
+0+38 <[^>]*> 2e989078[ 	]+textrmswcs[ 	]+r9, wr8, #0
+0+3c <[^>]*> ee698014[ 	]+tinsrb[ 	]+wr9, r8, #4
+0+40 <[^>]*> 3e6a7050[ 	]+tinsrhcc[ 	]+wr10, r7, #0
+0+44 <[^>]*> ee6b6091[ 	]+tinsrw[ 	]+wr11, r6, #1
+0+48 <[^>]*> 3e005110[ 	]+tmcrcc[ 	]+wcid, r5
+0+4c <[^>]*> ec47600c[ 	]+tmcrr[ 	]+wr12, r6, r7
+0+50 <[^>]*> 3e2041b5[ 	]+tmiacc[ 	]+wr13, r5, r4
+0+54 <[^>]*> 4e2821d3[ 	]+tmiaphmi[ 	]+wr14, r3, r2
+0+58 <[^>]*> ee2c11f0[ 	]+tmiabb[ 	]+wr15, r0, r1
+0+5c <[^>]*> 5e2d31b2[ 	]+tmiabtpl[ 	]+wr13, r2, r3
+0+60 <[^>]*> 6e2d5034[ 	]+tmiabtvs[ 	]+wr1, r4, r5
+0+64 <[^>]*> 7e2f7056[ 	]+tmiattvc[ 	]+wr2, r6, r7
+0+68 <[^>]*> ee138030[ 	]+tmovmskb[ 	]+r8, wr3
+0+6c <[^>]*> 8e549030[ 	]+tmovmskhhi[ 	]+r9, wr4
+0+70 <[^>]*> 9e95a030[ 	]+tmovmskwls[ 	]+sl, wr5
+0+74 <[^>]*> ee11b110[ 	]+tmrc[ 	]+fp, wcon
+0+78 <[^>]*> ac5dc006[ 	]+tmrrcge[ 	]+ip, sp, wr6
+0+7c <[^>]*> ee13f150[ 	]+torcb[ 	]+pc
+0+80 <[^>]*> be53f150[ 	]+torchlt[ 	]+pc
+0+84 <[^>]*> ee93f150[ 	]+torcw[ 	]+pc
+0+88 <[^>]*> ee0871c0[ 	]+waccb[ 	]+wr7, wr8
+0+8c <[^>]*> be4a91c0[ 	]+wacchlt[ 	]+wr9, wr10
+0+90 <[^>]*> ce8cb1c0[ 	]+waccwgt[ 	]+wr11, wr12
+0+94 <[^>]*> de0ed18f[ 	]+waddble[ 	]+wr13, wr14, wr15
+0+98 <[^>]*> ee120184[ 	]+waddbus[ 	]+wr0, wr2, wr4
+0+9c <[^>]*> ee38618a[ 	]+waddbss[ 	]+wr6, wr8, wr10
+0+a0 <[^>]*> ee4ec18f[ 	]+waddh[ 	]+wr12, wr14, wr15
+0+a4 <[^>]*> fe5cd18b[ 	]+waddhusnv[ 	]+wr13, wr12, wr11
+0+a8 <[^>]*> 0e79a188[ 	]+waddhsseq[ 	]+wr10, wr9, wr8
+0+ac <[^>]*> 1e867185[ 	]+waddwne[ 	]+wr7, wr6, wr5
+0+b0 <[^>]*> ee934182[ 	]+waddwus[ 	]+wr4, wr3, wr2
+0+b4 <[^>]*> 2eb0118f[ 	]+waddwsscs[ 	]+wr1, wr0, wr15
+0+b8 <[^>]*> ee553027[ 	]+waligni[ 	]+wr3, wr5, wr7, #5
+0+bc <[^>]*> 2e8b902d[ 	]+walignr0cs[ 	]+wr9, wr11, wr13
+0+c0 <[^>]*> ee967025[ 	]+walignr1[ 	]+wr7, wr6, wr5
+0+c4 <[^>]*> 3ea42028[ 	]+walignr2cc[ 	]+wr2, wr4, wr8
+0+c8 <[^>]*> 3eb95021[ 	]+walignr3cc[ 	]+wr5, wr9, wr1
+0+cc <[^>]*> ee283001[ 	]+wand[ 	]+wr3, wr8, wr1
+0+d0 <[^>]*> ee323006[ 	]+wandn[ 	]+wr3, wr2, wr6
+0+d4 <[^>]*> ee887009[ 	]+wavg2b[ 	]+wr7, wr8, wr9
+0+d8 <[^>]*> decba00c[ 	]+wavg2hle[ 	]+wr10, wr11, wr12
+0+dc <[^>]*> ae9ed00f[ 	]+wavg2brge[ 	]+wr13, wr14, wr15
+0+e0 <[^>]*> eed1000c[ 	]+wavg2hr[ 	]+wr0, wr1, wr12
+0+e4 <[^>]*> ee04d065[ 	]+wcmpeqb[ 	]+wr13, wr4, wr5
+0+e8 <[^>]*> 0e474060[ 	]+wcmpeqheq[ 	]+wr4, wr7, wr0
+0+ec <[^>]*> be896068[ 	]+wcmpeqwlt[ 	]+wr6, wr9, wr8
+0+f0 <[^>]*> 3e121063[ 	]+wcmpgtubcc[ 	]+wr1, wr2, wr3
+0+f4 <[^>]*> ee354066[ 	]+wcmpgtsb[ 	]+wr4, wr5, wr6
+0+f8 <[^>]*> 3e587069[ 	]+wcmpgtuhcc[ 	]+wr7, wr8, wr9
+0+fc <[^>]*> ee7ba06d[ 	]+wcmpgtsh[ 	]+wr10, wr11, wr13
+0+100 <[^>]*> ee942063[ 	]+wcmpgtuw[ 	]+wr2, wr4, wr3
+0+104 <[^>]*> 8eb65063[ 	]+wcmpgtswhi[ 	]+wr5, wr6, wr3
+0+108 <[^>]*> ed901024[ 	]+wldrb[ 	]+wr1, \[r0, #36\]
+0+10c <[^>]*> 0df12018[ 	]+wldrheq[ 	]+wr2, \[r1, #24\]!
+0+110 <[^>]*> 1cb23104[ 	]+wldrwne[ 	]+wr3, \[r2\], #16
+0+114 <[^>]*> 6dd34102[ 	]+wldrdvs[ 	]+wr4, \[r3, #8\]
+0+118 <[^>]*> fdb12105[ 	]+wldrw[ 	]+wcssf, \[r1, #20\]!
+0+11c <[^>]*> ee474109[ 	]+wmacu[ 	]+wr4, wr7, wr9
+0+120 <[^>]*> 2e6a810e[ 	]+wmacscs[ 	]+wr8, wr10, wr14
+0+124 <[^>]*> ee5cf10b[ 	]+wmacuz[ 	]+wr15, wr12, wr11
+0+128 <[^>]*> ee78310a[ 	]+wmacsz[ 	]+wr3, wr8, wr10
+0+12c <[^>]*> ee8bc107[ 	]+wmaddu[ 	]+wr12, wr11, wr7
+0+130 <[^>]*> cea3510f[ 	]+wmaddsgt[ 	]+wr5, wr3, wr15
+0+134 <[^>]*> 2e043165[ 	]+wmaxubcs[ 	]+wr3, wr4, wr5
+0+138 <[^>]*> ee243165[ 	]+wmaxsb[ 	]+wr3, wr4, wr5
+0+13c <[^>]*> 5e443165[ 	]+wmaxuhpl[ 	]+wr3, wr4, wr5
+0+140 <[^>]*> 4e643165[ 	]+wmaxshmi[ 	]+wr3, wr4, wr5
+0+144 <[^>]*> ae843165[ 	]+wmaxuwge[ 	]+wr3, wr4, wr5
+0+148 <[^>]*> fea43165[ 	]+wmaxswnv[ 	]+wr3, wr4, wr5
+0+14c <[^>]*> 3e1c416a[ 	]+wminubcc[ 	]+wr4, wr12, wr10
+0+150 <[^>]*> ee3c416a[ 	]+wminsb[ 	]+wr4, wr12, wr10
+0+154 <[^>]*> 7e5c416a[ 	]+wminuhvc[ 	]+wr4, wr12, wr10
+0+158 <[^>]*> ee7c416a[ 	]+wminsh[ 	]+wr4, wr12, wr10
+0+15c <[^>]*> ee9c416a[ 	]+wminuw[ 	]+wr4, wr12, wr10
+0+160 <[^>]*> 3ebc416a[ 	]+wminswcc[ 	]+wr4, wr12, wr10
+0+164 <[^>]*> 0e043004[ 	]+woreq[ 	]+wr3, wr4, wr4
+0+168 <[^>]*> ee112108[ 	]+wmulum[ 	]+wr2, wr1, wr8
+0+16c <[^>]*> ee312108[ 	]+wmulsm[ 	]+wr2, wr1, wr8
+0+170 <[^>]*> ee012108[ 	]+wmulul[ 	]+wr2, wr1, wr8
+0+174 <[^>]*> de212108[ 	]+wmulslle[ 	]+wr2, wr1, wr8
+0+178 <[^>]*> 0e08b00e[ 	]+woreq[ 	]+wr11, wr8, wr14
+0+17c <[^>]*> 0e510083[ 	]+wpackhuseq[ 	]+wr0, wr1, wr3
+0+180 <[^>]*> ee910083[ 	]+wpackwus[ 	]+wr0, wr1, wr3
+0+184 <[^>]*> eed10083[ 	]+wpackdus[ 	]+wr0, wr1, wr3
+0+188 <[^>]*> 8e710083[ 	]+wpackhsshi[ 	]+wr0, wr1, wr3
+0+18c <[^>]*> eeb10083[ 	]+wpackwss[ 	]+wr0, wr1, wr3
+0+190 <[^>]*> 0ef10083[ 	]+wpackdsseq[ 	]+wr0, wr1, wr3
+0+194 <[^>]*> ee754046[ 	]+wrorh[ 	]+wr4, wr5, wr6
+0+198 <[^>]*> 4eb54046[ 	]+wrorwmi[ 	]+wr4, wr5, wr6
+0+19c <[^>]*> eef54046[ 	]+wrord[ 	]+wr4, wr5, wr6
+0+1a0 <[^>]*> ee7a9148[ 	]+wrorhg[ 	]+wr9, wr10, wcgr0
+0+1a4 <[^>]*> aeba9149[ 	]+wrorwgge[ 	]+wr9, wr10, wcgr1
+0+1a8 <[^>]*> eefa914a[ 	]+wrordg[ 	]+wr9, wr10, wcgr2
+0+1ac <[^>]*> ee00212a[ 	]+wsadb[ 	]+wr2, wr0, wr10
+0+1b0 <[^>]*> ee40212a[ 	]+wsadh[ 	]+wr2, wr0, wr10
+0+1b4 <[^>]*> ee10212a[ 	]+wsadbz[ 	]+wr2, wr0, wr10
+0+1b8 <[^>]*> fe50212a[ 	]+wsadhznv[ 	]+wr2, wr0, wr10
+0+1bc <[^>]*> 0ef941eb[ 	]+wshufheq[ 	]+wr4, wr9, #251
+0+1c0 <[^>]*> ee592044[ 	]+wsllh[ 	]+wr2, wr9, wr4
+0+1c4 <[^>]*> ee992044[ 	]+wsllw[ 	]+wr2, wr9, wr4
+0+1c8 <[^>]*> 0ed92044[ 	]+wslldeq[ 	]+wr2, wr9, wr4
+0+1cc <[^>]*> 0e59214b[ 	]+wsllhgeq[ 	]+wr2, wr9, wcgr3
+0+1d0 <[^>]*> 7e99214a[ 	]+wsllwgvc[ 	]+wr2, wr9, wcgr2
+0+1d4 <[^>]*> eed92149[ 	]+wslldg[ 	]+wr2, wr9, wcgr1
+0+1d8 <[^>]*> ee451047[ 	]+wsrah[ 	]+wr1, wr5, wr7
+0+1dc <[^>]*> ee851047[ 	]+wsraw[ 	]+wr1, wr5, wr7
+0+1e0 <[^>]*> 0ec51047[ 	]+wsradeq[ 	]+wr1, wr5, wr7
+0+1e4 <[^>]*> ee45114b[ 	]+wsrahg[ 	]+wr1, wr5, wcgr3
+0+1e8 <[^>]*> 4e851148[ 	]+wsrawgmi[ 	]+wr1, wr5, wcgr0
+0+1ec <[^>]*> eec51149[ 	]+wsradg[ 	]+wr1, wr5, wcgr1
+0+1f0 <[^>]*> ee651047[ 	]+wsrlh[ 	]+wr1, wr5, wr7
+0+1f4 <[^>]*> eea51047[ 	]+wsrlw[ 	]+wr1, wr5, wr7
+0+1f8 <[^>]*> 0ee51047[ 	]+wsrldeq[ 	]+wr1, wr5, wr7
+0+1fc <[^>]*> ee65114b[ 	]+wsrlhg[ 	]+wr1, wr5, wcgr3
+0+200 <[^>]*> 4ea51148[ 	]+wsrlwgmi[ 	]+wr1, wr5, wcgr0
+0+204 <[^>]*> eee51149[ 	]+wsrldg[ 	]+wr1, wr5, wcgr1
+0+208 <[^>]*> ed811004[ 	]+wstrb[ 	]+wr1, \[r1, #4\]
+0+20c <[^>]*> ede11004[ 	]+wstrh[ 	]+wr1, \[r1, #4\]!
+0+210 <[^>]*> eca11101[ 	]+wstrw[ 	]+wr1, \[r1\], #4
+0+214 <[^>]*> edc11101[ 	]+wstrd[ 	]+wr1, \[r1, #4\]
+0+218 <[^>]*> fca13101[ 	]+wstrw[ 	]+wcasf, \[r1\], #4
+0+21c <[^>]*> 3e1311ae[ 	]+wsubbuscc[ 	]+wr1, wr3, wr14
+0+220 <[^>]*> ee5311ae[ 	]+wsubhus[ 	]+wr1, wr3, wr14
+0+224 <[^>]*> 3e9311ae[ 	]+wsubwuscc[ 	]+wr1, wr3, wr14
+0+228 <[^>]*> 3e3311ae[ 	]+wsubbsscc[ 	]+wr1, wr3, wr14
+0+22c <[^>]*> 3e7311ae[ 	]+wsubhsscc[ 	]+wr1, wr3, wr14
+0+230 <[^>]*> eeb311ae[ 	]+wsubwss[ 	]+wr1, wr3, wr14
+0+234 <[^>]*> ee0630c0[ 	]+wunpckehub[ 	]+wr3, wr6
+0+238 <[^>]*> 4e4630c0[ 	]+wunpckehuhmi[ 	]+wr3, wr6
+0+23c <[^>]*> ee8630c0[ 	]+wunpckehuw[ 	]+wr3, wr6
+0+240 <[^>]*> ee2630c0[ 	]+wunpckehsb[ 	]+wr3, wr6
+0+244 <[^>]*> ee6630c0[ 	]+wunpckehsh[ 	]+wr3, wr6
+0+248 <[^>]*> 0ea630c0[ 	]+wunpckehsweq[ 	]+wr3, wr6
+0+24c <[^>]*> ee1c50ca[ 	]+wunpckihb[ 	]+wr5, wr12, wr10
+0+250 <[^>]*> 8e5c50ca[ 	]+wunpckihhhi[ 	]+wr5, wr12, wr10
+0+254 <[^>]*> ee9c50ca[ 	]+wunpckihw[ 	]+wr5, wr12, wr10
+0+258 <[^>]*> ee0530e0[ 	]+wunpckelub[ 	]+wr3, wr5
+0+25c <[^>]*> 1e4530e0[ 	]+wunpckeluhne[ 	]+wr3, wr5
+0+260 <[^>]*> ee8530e0[ 	]+wunpckeluw[ 	]+wr3, wr5
+0+264 <[^>]*> ce2530e0[ 	]+wunpckelsbgt[ 	]+wr3, wr5
+0+268 <[^>]*> ee6530e0[ 	]+wunpckelsh[ 	]+wr3, wr5
+0+26c <[^>]*> eea530e0[ 	]+wunpckelsw[ 	]+wr3, wr5
+0+270 <[^>]*> ee1540ea[ 	]+wunpckilb[ 	]+wr4, wr5, wr10
+0+274 <[^>]*> ee5540ea[ 	]+wunpckilh[ 	]+wr4, wr5, wr10
+0+278 <[^>]*> 0e9540ea[ 	]+wunpckilweq[ 	]+wr4, wr5, wr10
+0+27c <[^>]*> 1e143005[ 	]+wxorne[ 	]+wr3, wr4, wr5
+0+280 <[^>]*> ae377007[ 	]+wandnge[ 	]+wr7, wr7, wr7
diff --git a/gas/testsuite/gas/arm/iwmmxt.s b/gas/testsuite/gas/arm/iwmmxt.s
new file mode 100644
index 0000000..b3e7a85
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt.s
@@ -0,0 +1,204 @@
+	.text
+	.global iwmmxt
+iwmmxt:
+	
+	tandcb		r15
+	TANDCHLE	r15
+	TANDCWge	r15
+
+	TBCSTBlt	wr0, r1
+	tbcsth		wr1, r2
+	TBCSTWGT	wr2, r3
+
+	textrcb		r15, #7
+	textrcheq	r15, #2
+	TEXTRCW		r15, #0
+
+	TEXTRMUB	r14, wr3, #6
+	textrmsbne	r13, wr4, #5
+	textrmUH	r12, wr5, #2
+	textrmSh	r11, wr6, #0
+	TEXTRMUWcs	r10, wr7, #1
+	textrmswhs	r9,  wr8, #0
+
+	TINSRB		wr9,  r8, #4
+	tinsrhcc	wr10, r7, #0
+	tinsrw		wr11, r6, #1
+
+	tmcrul		wcid, r5
+	TMCRR		wr12, r6, r7
+	tmialo		wr13, r5, r4
+	tmiaphMI	wr14, r3, r2
+	
+	TMIAbb		wr15, r0, r1
+	TMIAbTpl	wr13, r2, r3
+	tmiaBtvs	wr1, r4, r5
+	tmiaTTvc	wr2, r6, r7
+
+	tmovmskB	r8, wr3
+	TMOVMSKHhi	r9, wr4
+	tmovmskwls	r10, wr5
+
+	tmrc		r11, wcon
+	TMRRCge		r12, r13, wr6
+	
+	torcb		r15
+	torchlt		r15
+	TORCW		r15
+
+	waccb		wr7,  wr8
+	WACCHlt		wr9,  wr10
+	WACCWGT		wr11, wr12
+
+	waddble		wr13, wr14, wr15
+	waddBUS		wr0,  wr2,  wr4
+	waddbssal	wr6,  wr8,  wr10
+	waddH		wr12, wr14, wr15
+	WADDHUSNV	wr13, wr12, wr11
+	WADDHSSeq	wr10, wr9,  wr8
+	WADDWne		wr7,  wr6, wr5
+	waddwus		wr4,  wr3, wr2
+	waddwsscs	wr1,  wr0, wr15
+
+	waligni		wr3,  wr5, wr7, #5
+	WALIGNR0hs	wr9,  wr11, wr13
+	walignr1	wr7,  wr6, wr5
+	walignr2cc	wr2,  wr4, wr8
+	WALIGNR3ul	wr5,  wr9, wr1
+
+	wand		wr3, wr8, wr1
+	wandn		wr3, wr2, wr6
+
+	wavg2b		wr7, wr8, wr9
+	wavg2hle	wr10, wr11, wr12
+	wavg2brge	wr13, wr14, wr15
+	wavg2hr		wr0, wr1, wr12
+
+	wcmpeqb		wr13, wr4, wr5
+	wcmpeqheq	wr4, wr7, wr0
+	wcmpeqWlt	wr6, wr9, wr8
+
+	wcmpgtUbul	wr1, wr2, wr3
+	wcmpgtsb	wr4, wr5, wr6
+	wcmpgtuhcc	wr7, wr8, wr9
+	wcmpgtsh	wr10, wr11, wr13
+	wcmpgtuw	wr2, wr4, wr3
+	wcmpgtswhi	wr5, wr6, wr3
+
+	wldrb		wr1, [r0, #36]
+	wldrheq		wr2, [r1, #24]!
+	wldrwne		wr3, [r2], #16
+	wldrdvs		wr4, [r3, #8]
+	wldrw		wcssf, [r1, #20]!
+	
+	wmacu		wr4, wr7, wr9
+	wmacscs		wr8, wr10, wr14
+	wmacuzal	wr15, wr12, wr11
+	wmacsz		wr3, wr8, wr10
+
+	wmaddu		wr12, wr11, wr7
+	wmaddsgt	wr5, wr3, wr15
+
+	wmaxubhs	wr3, wr4, wr5
+	wmaxsb		wr3, wr4, wr5
+	wmaxuhpl	wr3, wr4, wr5
+	wmaxshmi	wr3, wr4, wr5
+	wmaxuwge	wr3, wr4, wr5
+	wmaxswnv	wr3, wr4, wr5
+
+	wminubul	wr4, wr12, wr10
+	wminsb		wr4, wr12, wr10
+	wminuhvc	wr4, wr12, wr10
+	wminsh		wr4, wr12, wr10
+	wminuw		wr4, wr12, wr10
+	wminswcc	wr4, wr12, wr10
+
+	wmoveq		wr3, wr4
+
+	wmulum		wr2, wr1, wr8
+	wmulsm		wr2, wr1, wr8
+	wmulul		wr2, wr1, wr8
+	wmulslle	wr2, wr1, wr8
+
+	woreq		wr11, wr8, wr14
+
+	wpackhuseq	wr0, wr1, wr3
+	wpackwus	wr0, wr1, wr3
+	wpackdusal	wr0, wr1, wr3
+	wpackhsshi	wr0, wr1, wr3
+	wpackwss	wr0, wr1, wr3
+	wpackdsseq	wr0, wr1, wr3
+
+	wrorh		wr4, wr5, wr6
+	wrorwmi		wr4, wr5, wr6
+	wrord		wr4, wr5, wr6
+	wrorhg		wr9, wr10, wcgr0
+	wrorwgge	wr9, wr10, wcgr1
+	wrordg		wr9, wr10, wcgr2
+
+	wsadb		wr2, wr0, wr10
+	wsadhal		wr2, wr0, wr10
+	wsadbz		wr2, wr0, wr10
+	wsadhznv	wr2, wr0, wr10
+
+	wshufheq	wr4, wr9, #251
+
+	wsllh		wr2, wr9, wr4
+	wsllw		wr2, wr9, wr4
+	wslldeq		wr2, wr9, wr4
+	wsllhgeq	wr2, wr9, wcgr3
+	wsllwgvc	wr2, wr9, wcgr2
+	wslldg		wr2, wr9, wcgr1
+
+	wsrah		wr1, wr5, wr7
+	wsraw		wr1, wr5, wr7
+	wsradeq		wr1, wr5, wr7
+	wsrahg		wr1, wr5, wcgr3
+	wsrawgmi	wr1, wr5, wcgr0
+	wsradg		wr1, wr5, wcgr1
+
+	wsrlh		wr1, wr5, wr7
+	wsrlw		wr1, wr5, wr7
+	wsrldeq		wr1, wr5, wr7
+	wsrlhg		wr1, wr5, wcgr3
+	wsrlwgmi	wr1, wr5, wcgr0
+	wsrldg		wr1, wr5, wcgr1
+
+	wstrb		wr1, [r1, #4]
+	wstrh		wr1, [r1, #4]!
+	wstrw		wr1, [r1], #4
+	wstrd		wr1, [r1, #4]
+	wstrw		wcasf, [r1], #4
+
+	wsubbusul	wr1, wr3, wr14
+	wsubhus		wr1, wr3, wr14
+	wsubwusul	wr1, wr3, wr14
+	wsubbssul	wr1, wr3, wr14
+	wsubhssul	wr1, wr3, wr14
+	wsubwss		wr1, wr3, wr14
+
+	wunpckehub	wr3, wr6
+	wunpckehuhmi	wr3, wr6
+	wunpckehuw	wr3, wr6
+	wunpckehsb	wr3, wr6
+	wunpckehsh	wr3, wr6
+	wunpckehsweq	wr3, wr6
+
+	wunpckihb	wr5, wr12, wr10
+	wunpckihhhi	wr5, wr12, wr10
+	wunpckihw	wr5, wr12, wr10
+
+	wunpckelub	wr3, wr5
+	wunpckeluhne	wr3, wr5
+	wunpckeluw	wr3, wr5
+	wunpckelsbgt	wr3, wr5
+	wunpckelsh	wr3, wr5
+	wunpckelsw	wr3, wr5
+
+	wunpckilb	wr4, wr5, wr10
+	wunpckilh	wr4, wr5, wr10
+	wunpckilweq	wr4, wr5, wr10
+
+	wxorne		wr3, wr4, wr5
+
+	wzeroge		wr7
diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp
index 0df76fe..a967cb7 100644
--- a/gas/testsuite/gas/elf/elf.exp
+++ b/gas/testsuite/gas/elf/elf.exp
@@ -46,6 +46,9 @@ if { ([istarget "*-*-elf*"]
     if {[istarget m32r*-*-*]} then {
 	set target_machine -m32r
     }
+    if {[istarget xscale*-*-elf]} then {
+	set target_machine -miwmmxt
+    }
     run_dump_test "ehopt0"
     run_dump_test "section0" 
     run_dump_test "section1" 
diff --git a/gas/testsuite/gas/elf/section2.e-miwmmxt b/gas/testsuite/gas/elf/section2.e-miwmmxt
new file mode 100644
index 0000000..dafccf7
--- /dev/null
+++ b/gas/testsuite/gas/elf/section2.e-miwmmxt
@@ -0,0 +1,10 @@
+
+Symbol table '.symtab' contains 6 entries:
+   Num:    Value[ 	]* Size Type    Bind   Vis      Ndx Name
+     0: 0+0     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+0     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+0     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+0     0 SECTION LOCAL  DEFAULT    3 
+     4: 0+0     0 SECTION LOCAL  DEFAULT    5 
+     5: 0+0     0 SECTION LOCAL  DEFAULT    4 
+
diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog
index b2eec4c..be6154d 100644
--- a/include/coff/ChangeLog
+++ b/include/coff/ChangeLog
@@ -1,3 +1,10 @@
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* arm.h (ARM_NOTE_SECTION): Define.
+
 2002-11-30  Alan Modra  <amodra@bigpond.net.au>
 
 	* ecoff.h: Replace boolean with bfd_boolean.
diff --git a/include/coff/arm.h b/include/coff/arm.h
index bcfdcbe..8b90228 100644
--- a/include/coff/arm.h
+++ b/include/coff/arm.h
@@ -124,3 +124,5 @@ struct external_reloc
 #define RELOC struct external_reloc
 #define RELSZ 14
 #endif
+
+#define ARM_NOTE_SECTION ".note"
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index e87cdd2..5411f76 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,4 +1,11 @@
-Mon Mar  3 20:35:58 2003  J"orn Rennecke <joern.rennecke@superh.com>
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* arm.h (ARM_NOTE_SECTION): Define.
+
+2003-03-03  J"orn Rennecke <joern.rennecke@superh.com>
 
 	* sh.h (EF_SH_MERGE_MACH): Make sure SH2E & SH3/SH3E merge to SH3E,
 	and SH2E & SH4 merge to SH4, not SH2E.
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 5347017..3b3f8d0 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -140,4 +140,7 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
   RELOC_NUMBER (R_ARM_RBASE,          255)
 END_RELOC_NUMBERS (R_ARM_max)
 
+/* The name of the note section used to identify arm variants.  */
+#define ARM_NOTE_SECTION ".note.arm.ident"
+     
 #endif /* _ELF_ARM_H */
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 715ce95..5a547ff 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,13 @@
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* emulparams/armelf.sh (OTHER_READONLY_SECTIONS): Define.
+	* emulparams/armelf_linux.sh (OTHER_READONLY_SECTIONS): Define.
+	* scripttempl/armcoff.sc (.data): Ensure 8 byte alignment.
+	(.bss): Likewise.
+
 2003-03-25  Alexandre Oliva  <aoliva@redhat.com>
 
 	* ldmain.h (ld_canon_sysroot, ld_canon_sysroot_len): Declare.
diff --git a/ld/emulparams/armelf.sh b/ld/emulparams/armelf.sh
index 0e8ebc5..fd723bc 100644
--- a/ld/emulparams/armelf.sh
+++ b/ld/emulparams/armelf.sh
@@ -7,6 +7,7 @@ TEXT_START_ADDR=0x8000
 TEMPLATE_NAME=elf32
 EXTRA_EM_FILE=armelf
 OTHER_TEXT_SECTIONS='*(.glue_7t) *(.glue_7)'
+OTHER_READONLY_SECTIONS='.note.arm.ident : { KEEP (*(.note.arm.ident)) }'
 OTHER_BSS_SYMBOLS='__bss_start__ = .;'
 OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;'
 
diff --git a/ld/emulparams/armelf_linux.sh b/ld/emulparams/armelf_linux.sh
index d04d967..734e92c 100644
--- a/ld/emulparams/armelf_linux.sh
+++ b/ld/emulparams/armelf_linux.sh
@@ -10,6 +10,7 @@ GENERATE_SHLIB_SCRIPT=yes
 
 DATA_START_SYMBOLS='__data_start = . ;';
 OTHER_TEXT_SECTIONS='*(.glue_7t) *(.glue_7)'
+OTHER_READONLY_SECTIONS='.note.arm.ident : { KEEP (*(.note.arm.ident)) }'
 OTHER_BSS_SYMBOLS='__bss_start__ = .;'
 OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;'
 
diff --git a/ld/scripttempl/armcoff.sc b/ld/scripttempl/armcoff.sc
index c61f734..781301c 100644
--- a/ld/scripttempl/armcoff.sc
+++ b/ld/scripttempl/armcoff.sc
@@ -44,7 +44,7 @@ SECTIONS
     ${RELOCATING+ etext  =  .;}
     ${RELOCATING+ _etext =  .;}
   }
-  .data ${RELOCATING+${DATA_ADDR-0x40000 + (. & 0xfffc0fff)}} : {
+  .data ${RELOCATING+${DATA_ADDR-0x40000 + (ALIGN(0x8) & 0xfffc0fff)}} : {
     ${RELOCATING+  __data_start__ = . ;}
     *(.data*)
         
@@ -60,7 +60,7 @@ SECTIONS
   }
   ${CONSTRUCTING+${RELOCATING-$CTOR}}
   ${CONSTRUCTING+${RELOCATING-$DTOR}}
-  .bss ${RELOCATING+ SIZEOF(.data) + ADDR(.data)} :
+  .bss ${RELOCATING+ ALIGN(0x8)} :
   { 					
     ${RELOCATING+ __bss_start__ = . ;}
     *(.bss)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d316279..b133896 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* arm-dis.c (regnames): Add iWMMXt register names.
+	(set_iwmmxt_regnames): New function.
+	(print_insn_arm): Handle iWMMXt formatters.
+	* arm-opc.h: Document iWMMXt formatters.
+	(arm_opcod): Add iWMMXt instructions.
+
 2003-03-22  Doug Evans  <dje@sebabeach.org>
 
 	* i386-dis.c (dis386): Recognize icebp (0xf1).
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 62a2a39..8fb9702 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1,24 +1,24 @@
 /* Instruction printing code for the ARM
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
 
-This file is part of libopcodes.
+   This file is part of libopcodes.
 
-This program is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2 of the License, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 2 of the License, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-more details.
+   This program is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -70,7 +70,21 @@ static arm_regname regnames[] =
   { "atpcs", "Select register names used in the ATPCS",
     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
   { "special-atpcs", "Select special register names used in the ATPCS",
-    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
+    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
+  { "iwmmxt_regnames", "Select register names used on the Intel(r) Wireless MMX(tm) technology coprocessor",
+    { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"}},
+  { "iwmmxt_Cregnames", "Select control register names used on the Intel(r) Wireless MMX(tm) technology coprocessor",
+    {"wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"}}
+};
+
+static char * iwmmxt_wwnames[] =
+{"b", "h", "w", "d"};
+
+static char * iwmmxt_wwssnames[] =
+{"b", "bus", "b", "bss",
+ "h", "hus", "h", "hss",
+ "w", "wus", "w", "wss",
+ "d", "dus", "d", "dss"
 };
 
 /* Default to GCC register name set.  */
@@ -98,11 +112,15 @@ static void parse_disassembler_options
   PARAMS ((char *));
 static int  print_insn
   PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean));
-int get_arm_regname_num_options (void);
-int set_arm_regname_option (int option);
-int get_arm_regnames (int option, const char **setname,
-		      const char **setdescription,
-		      const char ***register_names);
+static int set_iwmmxt_regnames
+  PARAMS ((void));
+
+int get_arm_regname_num_options
+  PARAMS ((void));
+int set_arm_regname_option
+  PARAMS ((int));
+int get_arm_regnames
+  PARAMS ((int, const char **, const char **, const char ***));
 
 /* Functions.  */
 int
@@ -167,6 +185,24 @@ arm_decode_shift (given, func, stream)
     }
 }
 
+static int
+set_iwmmxt_regnames ()
+{
+  const char * setname;
+  const char * setdesc;
+  const char ** regnames;
+  int iwmmxt_regnames = 0;
+  int num_regnames = get_arm_regname_num_options ();
+
+  get_arm_regnames (iwmmxt_regnames, &setname,
+		    &setdesc, &regnames);
+  while ((strcmp ("iwmmxt_regnames", setname))
+	 && (iwmmxt_regnames < num_regnames))
+    get_arm_regnames (++iwmmxt_regnames, &setname, &setdesc, &regnames);
+
+  return iwmmxt_regnames;
+}
+			  
 /* Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (always 4 on ARM). */
 
@@ -179,9 +215,15 @@ print_insn_arm (pc, info, given)
   const struct arm_opcode *insn;
   void *stream = info->stream;
   fprintf_ftype func   = info->fprintf_func;
+  static int iwmmxt_regnames = 0;
 
   for (insn = arm_opcodes; insn->assembler; insn++)
     {
+      if (insn->value == FIRST_IWMMXT_INSN
+	  && info->mach != bfd_mach_arm_XScale
+	  && info->mach != bfd_mach_arm_iWMMXt)
+	insn = insn + IWMMXT_INSN_COUNT;
+
       if ((given & insn->mask) == insn->value)
 	{
 	  char * c;
@@ -629,6 +671,63 @@ print_insn_arm (pc, info, given)
 				    func (stream, "f%d", reg);
 				}
 				break;
+
+			      case 'w':
+				{
+				  long reg;
+
+				  if (bitstart != bitend)
+				    {
+				      reg = given >> bitstart;
+				      reg &= (2 << (bitend - bitstart)) - 1;
+				      if (bitend - bitstart == 1)
+					func (stream, "%s", iwmmxt_wwnames[reg]);
+				      else
+					func (stream, "%s", iwmmxt_wwssnames[reg]);
+				    }
+				  else
+				    {
+				      reg = (((given >> 8)  & 0x1) |
+					     ((given >> 22) & 0x1));
+				      func (stream, "%s", iwmmxt_wwnames[reg]);
+				    }
+				}
+				break;
+
+			      case 'g':
+				{
+				  long reg;
+				  int current_regnames;
+
+				  if (! iwmmxt_regnames)
+				    iwmmxt_regnames = set_iwmmxt_regnames ();
+				  current_regnames = set_arm_regname_option
+				    (iwmmxt_regnames);
+
+				  reg = given >> bitstart;
+				  reg &= (2 << (bitend - bitstart)) - 1;
+				  func (stream, "%s", arm_regnames[reg]);
+				  set_arm_regname_option (current_regnames);
+				}
+				break;
+
+			      case 'G':
+				{
+				  long reg;
+				  int current_regnames;
+
+				  if (! iwmmxt_regnames)
+				    iwmmxt_regnames = set_iwmmxt_regnames ();
+				  current_regnames = set_arm_regname_option
+				    (iwmmxt_regnames + 1);
+
+				  reg = given >> bitstart;
+				  reg &= (2 << (bitend - bitstart)) - 1;
+				  func (stream, "%s", arm_regnames[reg]);
+				  set_arm_regname_option (current_regnames);
+				}
+				break;
+
 			      default:
 				abort ();
 			      }
@@ -734,6 +833,54 @@ print_insn_arm (pc, info, given)
 			  }
 			break;
 
+		      case 'L':
+			switch (given & 0x00400100)
+			  {
+			  case 0x00000000: func (stream, "b"); break;
+			  case 0x00400000: func (stream, "h"); break;
+			  case 0x00000100: func (stream, "w"); break;
+			  case 0x00400100: func (stream, "d"); break;
+			  default:
+			    break;
+			  }
+			break;
+
+		      case 'Z':
+			{
+			  int value;
+			  /* given (20, 23) | given (0, 3) */
+			  value = ((given >> 16) & 0xf0) | (given & 0xf);
+			  func (stream, "%d", value);
+			}
+			break;
+
+		      case 'l':
+			/* This is like the 'A' operator, except that if
+			   the width field "M" is zero, then the offset is
+			   *not* multiplied by four.  */
+			{
+			  int offset = given & 0xff;
+			  int multiplier = (given & 0x00000100) ? 4 : 1;
+
+			  func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+
+			  if (offset)
+			    {
+			      if ((given & 0x01000000) != 0)
+				func (stream, ", %s#%d]%s",
+				      ((given & 0x00800000) == 0 ? "-" : ""),
+				      offset * multiplier,
+				      ((given & 0x00200000) != 0 ? "!" : ""));
+			      else
+				func (stream, "], %s#%d",
+				      ((given & 0x00800000) == 0 ? "-" : ""),
+				      offset * multiplier);
+			    }
+			  else
+			    func (stream, "]");
+			}
+			break;
+
 		      default:
 			abort ();
 		      }
diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h
index 213d4f0..233a830 100644
--- a/opcodes/arm-opc.h
+++ b/opcodes/arm-opc.h
@@ -1,6 +1,6 @@
 /* Opcode table for the ARM.
 
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003
    Free Software Foundation, Inc.
    
    This program is free software; you can redistribute it and/or modify
@@ -60,6 +60,13 @@ struct thumb_opcode
    %m			print register mask for ldm/stm instruction
    %C			print the PSR sub type.
    %F			print the COUNT field of a LFM/SFM instruction.
+IWMMXT specific format options:
+   %<bitfield>g         print as an iWMMXt 64-bit register
+   %<bitfield>G         print as an iWMMXt general purpose or control register
+   %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
+   %Z			print the Immediate of a WSHUFH instruction.
+   %L			print as an iWMMXt N/M width field.
+   %l			like 'A' except use byte offsets for 'B' & 'H' versions
 Thumb specific format options:
    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
@@ -101,6 +108,59 @@ static const struct arm_opcode arm_opcodes[] =
     {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
     {0xf450f000, 0xfc70f000, "pld\t%a"},
     
+    /* Intel(r) Wireless MMX(tm) technology instructions.  */
+#define FIRST_IWMMXT_INSN 0x0e130130
+#define IWMMXT_INSN_COUNT 47
+    {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
+    {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
+    {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
+    {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
+    {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
+    {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
+    {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
+    {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
+    {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
+    {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
+    {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
+    {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
+    {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
+    {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
+    {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
+    {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
+    {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
+    {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
+    {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
+    {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
+    {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
+    {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
+    {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
+    {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
+
     /* V5 Instructions.  */
     {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
     {0xfa000000, 0xfe000000, "blx\t%B"},