RISC-V: drop stray INSN_ALIAS flags

FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but
presently they aren't. This fixes disassembly of these insns with
-Mno-aliases.

3 files changed, 38 insertions, 3 deletions

diff --git a/gas/testsuite/gas/riscv/fence-tso-na.d b/gas/testsuite/gas/riscv/fence-tso-na.d
new file mode 100644
index 0000000..5dee416
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fence-tso-na.d
@@ -0,0 +1,12 @@
+#as: -march=rv32ic
+#source: fence-tso.s
+#objdump: -dr -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+8330000f[ 	]+fence.tso
+#pass
diff --git a/gas/testsuite/gas/riscv/zbkb-32-na.d b/gas/testsuite/gas/riscv/zbkb-32-na.d
new file mode 100644
index 0000000..a7b67ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32-na.d
@@ -0,0 +1,23 @@
+#as: -march=rv32i_zbkb
+#source: zbkb-32.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+68755513[ 	]+brev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+08f51513[ 	]+zip[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+08f55513[ 	]+unzip[ 	]+a0,a0
+#pass
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 5bb49b4..5f447a2 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -450,7 +450,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fence",       0, INSN_CLASS_I, "",          MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
 {"fence",       0, INSN_CLASS_I, "P,Q",       MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
 {"fence.i",     0, INSN_CLASS_ZIFENCEI, "",   MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
-{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, INSN_ALIAS },
+{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 },
 {"rdcycle",     0, INSN_CLASS_I, "d",         MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
 {"rdinstret",   0, INSN_CLASS_I, "d",         MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
 {"rdtime",      0, INSN_CLASS_I, "d",         MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
@@ -975,8 +975,8 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cpopw",     64, INSN_CLASS_ZBB,  "d,s",   MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
 {"brev8",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
 {"brev8",     64, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
-{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
 {"pack",       0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
 {"packh",      0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
 {"packw",     64, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },