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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2025-01-06 09:14:34 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-01-06 11:04:40 +0800 |
| commit | a61beb42b0a12a8495755f95f9f4b97d7652b589 (patch) | |
| tree | 7f127e2904fa0b1fc11fe30b4d1f73ba47e1cbae | |
| parent | 6a83ffd4e93607684c2036681f0de1641870ef52 (diff) | |
| download | gdb-a61beb42b0a12a8495755f95f9f4b97d7652b589.zip gdb-a61beb42b0a12a8495755f95f9f4b97d7652b589.tar.gz gdb-a61beb42b0a12a8495755f95f9f4b97d7652b589.tar.bz2 | |
RISC-V: Eliminate redundant instruction macro
include/ChangeLog:
* opcode/riscv.h: Eliminate redundant instruction macro M_j.
Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 384107f..de4c13f 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -643,7 +643,6 @@ enum M_FLx, M_Sx_FSx, M_CALL, - M_J, M_LI, M_EXTH, M_ZEXTW, |