[BFD, AArch64] Improve bti/pac plts.

This patch aims to improve the definitions of BTI and PAC based PLTs.
The following changes are made:
   * PLT0 does not need PAC instructions since the PLTGOT[2] (and PLTGOT[1])
     are readonly so they cannot be corrupted at runtime. Thus both PAC plt0
     and BTI+PAC plt0 are removed and we can use basic plt0 and BTI plt0
     instead, respectively.
   * We can remove the extra padding nops when we add the new bti instructions.
     BTI plt0 and BTI TLSDESC plt are updated.
   * For better performance PLTn could be padded to 24bytes. Both BTI pltn and
     PAC pltn are updated.

*** bfd/ChangeLog ***

2019-04-25  Sudakshina Das  <sudi.das@arm.com>

	* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove.
	(PLT_BTI_TLSDESC_ENTRY_SIZE): Remove.
	(PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove.
	(PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update.
	(elfNN_aarch64_small_plt0_pac_entry): Remove.
	(elfNN_aarch64_small_plt0_bti_pac_entry): Remove.
	(elfNN_aarch64_small_plt0_bti_entry): Update.
	(elfNN_aarch64_small_plt_bti_entry): Update.
	(elfNN_aarch64_small_plt_pac_entry): Update.
	(elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update.
	(setup_plt_values): Setup new entries.
	(elfNN_aarch64_finish_dynamic_sections): Remove size change.
	(elfNN_aarch64_plt_sym_val): Likewise.

*** ld/ChangeLog ***

2019-04-25  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/ld-aarch64/bti-pac-plt-1.d: Update.
	* testsuite/ld-aarch64/bti-pac-plt-2.d: Update.
	* testsuite/ld-aarch64/bti-plt-1.d: Update.
	* testsuite/ld-aarch64/bti-plt-3.d: Update.
	* testsuite/ld-aarch64/bti-plt-5.d: Update.
	* testsuite/ld-aarch64/pac-plt-1.d: Update.
	* testsuite/ld-aarch64/pac-plt-2.d: Update.

10 files changed, 45 insertions, 73 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index d49fb7f..7539773 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,19 @@
+2019-04-25  Sudakshina Das  <sudi.das@arm.com>
+
+	* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove.
+	(PLT_BTI_TLSDESC_ENTRY_SIZE): Remove.
+	(PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove.
+	(PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update.
+	(elfNN_aarch64_small_plt0_pac_entry): Remove.
+	(elfNN_aarch64_small_plt0_bti_pac_entry): Remove.
+	(elfNN_aarch64_small_plt0_bti_entry): Update.
+	(elfNN_aarch64_small_plt_bti_entry): Update.
+	(elfNN_aarch64_small_plt_pac_entry): Update.
+	(elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update.
+	(setup_plt_values): Setup new entries.
+	(elfNN_aarch64_finish_dynamic_sections): Remove size change.
+	(elfNN_aarch64_plt_sym_val): Likewise.
+
 2019-04-22  Jim Wilson  <jimw@sifive.com>
 
 	* elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index 9d4df11..8940f4e 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -268,14 +268,10 @@
 #define PLT_SMALL_ENTRY_SIZE		(16)
 #define PLT_TLSDESC_ENTRY_SIZE		(32)
 /* PLT sizes with BTI insn.  */
-#define PLT_BTI_ENTRY_SIZE		(36)
-#define PLT_BTI_SMALL_ENTRY_SIZE	(20)
-#define PLT_BTI_TLSDESC_ENTRY_SIZE	(36)
+#define PLT_BTI_SMALL_ENTRY_SIZE	(24)
 /* PLT sizes with PAC insn.  */
-#define PLT_PAC_ENTRY_SIZE		(36)
-#define PLT_PAC_SMALL_ENTRY_SIZE	(20)
+#define PLT_PAC_SMALL_ENTRY_SIZE	(24)
 /* PLT sizes with BTI and PAC insn.  */
-#define PLT_BTI_PAC_ENTRY_SIZE		(40)
 #define PLT_BTI_PAC_SMALL_ENTRY_SIZE	(24)
 
 /* Encoding of the nop instruction.  */
@@ -307,7 +303,7 @@ static const bfd_byte elfNN_aarch64_small_plt0_entry[PLT_ENTRY_SIZE] =
   0x1f, 0x20, 0x03, 0xd5,	/* nop */
 };
 
-static const bfd_byte elfNN_aarch64_small_plt0_bti_entry[PLT_BTI_ENTRY_SIZE] =
+static const bfd_byte elfNN_aarch64_small_plt0_bti_entry[PLT_ENTRY_SIZE] =
 {
   0x5f, 0x24, 0x03, 0xd5,	/* bti c.  */
   0xf0, 0x7b, 0xbf, 0xa9,	/* stp x16, x30, [sp, #-16]!  */
@@ -322,45 +318,6 @@ static const bfd_byte elfNN_aarch64_small_plt0_bti_entry[PLT_BTI_ENTRY_SIZE] =
   0x20, 0x02, 0x1f, 0xd6,	/* br x17  */
   0x1f, 0x20, 0x03, 0xd5,	/* nop */
   0x1f, 0x20, 0x03, 0xd5,	/* nop */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
-};
-
-static const bfd_byte elfNN_aarch64_small_plt0_pac_entry[PLT_PAC_ENTRY_SIZE] =
-{
-  0xf0, 0x7b, 0xbf, 0xa9,	/* stp x16, x30, [sp, #-16]!  */
-  0x10, 0x00, 0x00, 0x90,	/* adrp x16, (GOT+16)  */
-#if ARCH_SIZE == 64
-  0x11, 0x0A, 0x40, 0xf9,	/* ldr x17, [x16, #PLT_GOT+0x10]  */
-  0x10, 0x42, 0x00, 0x91,	/* add x16, x16,#PLT_GOT+0x10   */
-#else
-  0x11, 0x0A, 0x40, 0xb9,	/* ldr w17, [x16, #PLT_GOT+0x8]  */
-  0x10, 0x22, 0x00, 0x11,	/* add w16, w16,#PLT_GOT+0x8   */
-#endif
-  0x9f, 0x21, 0x03, 0xd5,	/* autia1716 */
-  0x20, 0x02, 0x1f, 0xd6,	/* br x17  */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
-};
-
-static const bfd_byte
-elfNN_aarch64_small_plt0_bti_pac_entry[PLT_BTI_PAC_ENTRY_SIZE] =
-{
-  0x5f, 0x24, 0x03, 0xd5,	/* bti c.  */
-  0xf0, 0x7b, 0xbf, 0xa9,	/* stp x16, x30, [sp, #-16]!  */
-  0x10, 0x00, 0x00, 0x90,	/* adrp x16, (GOT+16)  */
-#if ARCH_SIZE == 64
-  0x11, 0x0A, 0x40, 0xf9,	/* ldr x17, [x16, #PLT_GOT+0x10]  */
-  0x10, 0x42, 0x00, 0x91,	/* add x16, x16,#PLT_GOT+0x10   */
-#else
-  0x11, 0x0A, 0x40, 0xb9,	/* ldr w17, [x16, #PLT_GOT+0x8]  */
-  0x10, 0x22, 0x00, 0x11,	/* add w16, w16,#PLT_GOT+0x8   */
-#endif
-  0x9f, 0x21, 0x03, 0xd5,	/* autia1716 */
-  0x20, 0x02, 0x1f, 0xd6,	/* br x17  */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
 };
 
 /* Per function entry in a procedure linkage table looks like this
@@ -392,6 +349,7 @@ elfNN_aarch64_small_plt_bti_entry[PLT_BTI_SMALL_ENTRY_SIZE] =
   0x10, 0x02, 0x00, 0x11,	/* add w16, w16, :lo12:PLTGOT + n * 4  */
 #endif
   0x20, 0x02, 0x1f, 0xd6,	/* br x17.  */
+  0x1f, 0x20, 0x03, 0xd5,	/* nop */
 };
 
 static const bfd_byte
@@ -407,6 +365,7 @@ elfNN_aarch64_small_plt_pac_entry[PLT_PAC_SMALL_ENTRY_SIZE] =
 #endif
   0x9f, 0x21, 0x03, 0xd5,	/* autia1716 */
   0x20, 0x02, 0x1f, 0xd6,	/* br x17.  */
+  0x1f, 0x20, 0x03, 0xd5,	/* nop */
 };
 
 static const bfd_byte
@@ -444,7 +403,7 @@ elfNN_aarch64_tlsdesc_small_plt_entry[PLT_TLSDESC_ENTRY_SIZE] =
 };
 
 static const bfd_byte
-elfNN_aarch64_tlsdesc_small_plt_bti_entry[PLT_BTI_TLSDESC_ENTRY_SIZE] =
+elfNN_aarch64_tlsdesc_small_plt_bti_entry[PLT_TLSDESC_ENTRY_SIZE] =
 {
   0x5f, 0x24, 0x03, 0xd5,	/* bti c.  */
   0xe2, 0x0f, 0xbf, 0xa9,	/* stp x2, x3, [sp, #-16]! */
@@ -459,7 +418,6 @@ elfNN_aarch64_tlsdesc_small_plt_bti_entry[PLT_BTI_TLSDESC_ENTRY_SIZE] =
 #endif
   0x40, 0x00, 0x1f, 0xd6,	/* br x2 */
   0x1f, 0x20, 0x03, 0xd5,	/* nop */
-  0x1f, 0x20, 0x03, 0xd5,	/* nop */
 };
 
 #define elf_info_to_howto		elfNN_aarch64_info_to_howto
@@ -4758,9 +4716,7 @@ setup_plt_values (struct bfd_link_info *link_info,
 
   if (plt_type == PLT_BTI_PAC)
     {
-      globals->plt_header_size = PLT_BTI_PAC_ENTRY_SIZE;
-      globals->plt0_entry = elfNN_aarch64_small_plt0_bti_pac_entry;
-      globals->tlsdesc_plt_entry_size = PLT_BTI_TLSDESC_ENTRY_SIZE;
+      globals->plt0_entry = elfNN_aarch64_small_plt0_bti_entry;
 
       /* Only in ET_EXEC we need PLTn with BTI.  */
       if (bfd_link_pde (link_info))
@@ -4776,9 +4732,7 @@ setup_plt_values (struct bfd_link_info *link_info,
     }
   else if (plt_type == PLT_BTI)
     {
-      globals->plt_header_size = PLT_BTI_ENTRY_SIZE;
       globals->plt0_entry = elfNN_aarch64_small_plt0_bti_entry;
-      globals->tlsdesc_plt_entry_size = PLT_BTI_TLSDESC_ENTRY_SIZE;
 
       /* Only in ET_EXEC we need PLTn with BTI.  */
       if (bfd_link_pde (link_info))
@@ -4789,9 +4743,6 @@ setup_plt_values (struct bfd_link_info *link_info,
     }
   else if (plt_type == PLT_PAC)
     {
-      globals->plt_header_size = PLT_PAC_ENTRY_SIZE;
-      globals->plt0_entry = elfNN_aarch64_small_plt0_pac_entry;
-      globals->tlsdesc_plt_entry_size = PLT_TLSDESC_ENTRY_SIZE;
       globals->plt_entry_size = PLT_PAC_SMALL_ENTRY_SIZE;
       globals->plt_entry = elfNN_aarch64_small_plt_pac_entry;
     }
@@ -9720,7 +9671,6 @@ elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
 	  if (type == PLT_BTI || type == PLT_BTI_PAC)
 	    {
 	      entry = elfNN_aarch64_tlsdesc_small_plt_bti_entry;
-	      htab->tlsdesc_plt_entry_size = PLT_BTI_TLSDESC_ENTRY_SIZE;
 	    }
 
 	  memcpy (htab->root.splt->contents + htab->tlsdesc_plt,
@@ -9896,7 +9846,6 @@ elfNN_aarch64_plt_sym_val (bfd_vma i, const asection *plt,
 
   if (elf_aarch64_tdata (plt->owner)->plt_type == PLT_BTI_PAC)
     {
-      plt0_size = PLT_BTI_PAC_ENTRY_SIZE;
       if (elf_elfheader (plt->owner)->e_type == ET_EXEC)
 	pltn_size = PLT_BTI_PAC_SMALL_ENTRY_SIZE;
       else
@@ -9904,13 +9853,11 @@ elfNN_aarch64_plt_sym_val (bfd_vma i, const asection *plt,
     }
   else if (elf_aarch64_tdata (plt->owner)->plt_type == PLT_BTI)
     {
-      plt0_size = PLT_BTI_ENTRY_SIZE;
       if (elf_elfheader (plt->owner)->e_type == ET_EXEC)
 	pltn_size = PLT_BTI_SMALL_ENTRY_SIZE;
     }
   else if (elf_aarch64_tdata (plt->owner)->plt_type == PLT_PAC)
     {
-      plt0_size = PLT_PAC_ENTRY_SIZE;
       pltn_size = PLT_PAC_SMALL_ENTRY_SIZE;
     }
 
diff --git a/ld/ChangeLog b/ld/ChangeLog
index a62a6c5..8756b2e9 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,13 @@
+2019-04-25  Sudakshina Das  <sudi.das@arm.com>
+
+	* testsuite/ld-aarch64/bti-pac-plt-1.d: Update.
+	* testsuite/ld-aarch64/bti-pac-plt-2.d: Update.
+	* testsuite/ld-aarch64/bti-plt-1.d: Update.
+	* testsuite/ld-aarch64/bti-plt-3.d: Update.
+	* testsuite/ld-aarch64/bti-plt-5.d: Update.
+	* testsuite/ld-aarch64/pac-plt-1.d: Update.
+	* testsuite/ld-aarch64/pac-plt-2.d: Update.
+
 2019-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 
 	* testsuite/config/default.exp: Use [check_compiler_available]
diff --git a/ld/testsuite/ld-aarch64/bti-pac-plt-1.d b/ld/testsuite/ld-aarch64/bti-pac-plt-1.d
index 8d780ca..1ac2806 100644
--- a/ld/testsuite/ld-aarch64/bti-pac-plt-1.d
+++ b/ld/testsuite/ld-aarch64/bti-pac-plt-1.d
@@ -13,11 +13,9 @@ Disassembly of section \.plt:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
 .*:	f9400e11 	ldr	x17, \[x16, #24\]
 .*:	91006210 	add	x16, x16, #0x18
-.*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
 .*:	d503201f 	nop
 .*:	d503201f 	nop
-.*:	d503201f 	nop
 
 [0-9a-f]+ <.*>:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
@@ -25,6 +23,7 @@ Disassembly of section \.plt:
 .*:	91008210 	add	x16, x16, #0x20
 .*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop
 
 [0-9a-f]+ <.*>:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
@@ -32,3 +31,4 @@ Disassembly of section \.plt:
 .*:	9100a210 	add	x16, x16, #0x28
 .*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop
diff --git a/ld/testsuite/ld-aarch64/bti-pac-plt-2.d b/ld/testsuite/ld-aarch64/bti-pac-plt-2.d
index d1264ea..e0ac1df1 100644
--- a/ld/testsuite/ld-aarch64/bti-pac-plt-2.d
+++ b/ld/testsuite/ld-aarch64/bti-pac-plt-2.d
@@ -13,11 +13,9 @@ Disassembly of section \.plt:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
 .*:	f9400e11 	ldr	x17, \[x16, #24\]
 .*:	91006210 	add	x16, x16, #0x18
-.*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
 .*:	d503201f 	nop
 .*:	d503201f 	nop
-.*:	d503201f 	nop
 
 [0-9]+ <.*>:
 .*:	d503245f 	bti	c
diff --git a/ld/testsuite/ld-aarch64/bti-plt-1.d b/ld/testsuite/ld-aarch64/bti-plt-1.d
index b7b58a8..618a6a9 100644
--- a/ld/testsuite/ld-aarch64/bti-plt-1.d
+++ b/ld/testsuite/ld-aarch64/bti-plt-1.d
@@ -17,7 +17,6 @@ Disassembly of section \.plt:
 .*:	d61f0220 	br	x17
 .*:	d503201f 	nop
 .*:	d503201f 	nop
-.*:	d503201f 	nop
 
 [0-9]+ <.*>:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
diff --git a/ld/testsuite/ld-aarch64/bti-plt-3.d b/ld/testsuite/ld-aarch64/bti-plt-3.d
index 0d4c467..08914de 100644
--- a/ld/testsuite/ld-aarch64/bti-plt-3.d
+++ b/ld/testsuite/ld-aarch64/bti-plt-3.d
@@ -17,7 +17,6 @@ Disassembly of section \.plt:
 .*:	d61f0220 	br	x17
 .*:	d503201f 	nop
 .*:	d503201f 	nop
-.*:	d503201f 	nop
 
 [0-9]+ <.*>:
 .*:	d503245f 	bti	c
@@ -25,6 +24,7 @@ Disassembly of section \.plt:
 .*:	f9401211 	ldr	x17, \[x16, #32\]
 .*:	91008210 	add	x16, x16, #0x20
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop
 
 [0-9]+ <.*>:
 .*:	d503245f 	bti	c
@@ -32,3 +32,4 @@ Disassembly of section \.plt:
 .*:	f9401611 	ldr	x17, \[x16, #40\]
 .*:	9100a210 	add	x16, x16, #0x28
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop
diff --git a/ld/testsuite/ld-aarch64/bti-plt-5.d b/ld/testsuite/ld-aarch64/bti-plt-5.d
index 01231b6..12abbc2 100644
--- a/ld/testsuite/ld-aarch64/bti-plt-5.d
+++ b/ld/testsuite/ld-aarch64/bti-plt-5.d
@@ -12,17 +12,17 @@ Disassembly of section \.plt:
 [0-9a-f]+ <.*>:
 .*:	d503245f 	bti	c
 .*:	a9bf7bf0 	stp	x16, x30, \[sp, #-16\]!
-.*:	90000090 	adrp	x16, 410000 <_start\+0xfd28>
+.*:	90000090 	adrp	x16, 410000 <.*>
 .*:	f9421611 	ldr	x17, \[x16, #1064\]
 .*:	9110a210 	add	x16, x16, #0x428
 .*:	d61f0220 	br	x17
 .*:	d503201f 	nop
 .*:	d503201f 	nop
-.*:	d503201f 	nop
 
 [0-9a-f]+ <.*>:
 .*:	d503245f 	bti	c
-.*:	90000090 	adrp	x16, 410000 <_start\+0xfd28>
+.*:	90000090 	adrp	x16, 410000 <.*>
 .*:	f9421a11 	ldr	x17, \[x16, #1072\]
 .*:	9110c210 	add	x16, x16, #0x430
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop
diff --git a/ld/testsuite/ld-aarch64/pac-plt-1.d b/ld/testsuite/ld-aarch64/pac-plt-1.d
index 47be949..9c4a676 100644
--- a/ld/testsuite/ld-aarch64/pac-plt-1.d
+++ b/ld/testsuite/ld-aarch64/pac-plt-1.d
@@ -12,7 +12,6 @@ Disassembly of section \.plt:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
 .*:	f9400e11 	ldr	x17, \[x16, #24\]
 .*:	91006210 	add	x16, x16, #0x18
-.*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
 .*:	d503201f 	nop
 .*:	d503201f 	nop
@@ -24,6 +23,7 @@ Disassembly of section \.plt:
 .*:	91008210 	add	x16, x16, #0x20
 .*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop
 
 [0-9]+ <.*>:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
@@ -31,3 +31,4 @@ Disassembly of section \.plt:
 .*:	9100a210 	add	x16, x16, #0x28
 .*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop
diff --git a/ld/testsuite/ld-aarch64/pac-plt-2.d b/ld/testsuite/ld-aarch64/pac-plt-2.d
index 42bfdca..7ebc81d 100644
--- a/ld/testsuite/ld-aarch64/pac-plt-2.d
+++ b/ld/testsuite/ld-aarch64/pac-plt-2.d
@@ -4,21 +4,21 @@
 #...
 Disassembly of section .plt:
 
-0000000000018000 \<.plt\>:
+.* \<.plt\>:
 .*:	a9bf7bf0 	stp	x16, x30, \[sp, #-16\]!
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
 .*:	f9401a11 	ldr	x17, \[x16, #48\]
 .*:	9100c210 	add	x16, x16, #0x30
-.*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
 .*:	d503201f 	nop
 .*:	d503201f 	nop
 .*:	d503201f 	nop
 
 
-0000000000018024 \<__tls_get_addr@plt\>:
+.* \<__tls_get_addr@plt\>:
 .*:	90000090 	adrp	x16, 28000 <_GLOBAL_OFFSET_TABLE_>
 .*:	f9401e11 	ldr	x17, \[x16, #56\]
 .*:	9100e210 	add	x16, x16, #0x38
 .*:	d503219f 	autia1716
 .*:	d61f0220 	br	x17
+.*:	d503201f 	nop