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authorAndreas Krebbel <krebbel@linux.ibm.com>2021-02-03 12:01:12 +0100
committerAndreas Krebbel <krebbel@linux.ibm.com>2021-02-03 12:35:33 +0100
commit61ecbbae8eb1d161316380ca0175912f414725ce (patch)
treefee516e16170222951a4a7ecb2e1e8bbab7b010f
parentf01fb44c0621b064996493bb5acd5077646ea84e (diff)
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IBM Z: Add missing vector formats to .insn docs
gas/ * doc/c-s390.texi: Document vector instruction formats.
-rw-r--r--gas/ChangeLog4
-rw-r--r--gas/doc/c-s390.texi50
2 files changed, 53 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c95c3e1..4d675dc 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2021-02-03 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * doc/c-s390.texi: Document vector instruction formats.
+
2021-02-01 Emery Hemingway <ehmry@posteo.net>
* configure.tgt: Add *-*-genode* as a target for AArch64 and x86.
diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi
index c1b46a1..02881c3 100644
--- a/gas/doc/c-s390.texi
+++ b/gas/doc/c-s390.texi
@@ -312,7 +312,7 @@ field. The notation changes as follows:
@cindex instruction formats, s390
@cindex s390 instruction formats
-The Principles of Operation manuals lists 26 instruction formats where
+The Principles of Operation manuals lists 35 instruction formats where
some of the formats have multiple variants. For the @samp{.insn}
pseudo directive the assembler recognizes some of the formats.
Typically, the most general variant of the instruction format is used
@@ -544,6 +544,54 @@ with the @samp{.insn} pseudo directive:
0 8 12 16 20 32 36 47
@end verbatim
+@item VRV format: <insn> V1,D2(V2,B2),M3
+@verbatim
++--------+----+----+----+-------------+----+------------+
+| OpCode | V1 | V2 | B2 | D2 | M3 | Opcode |
++--------+----+----+----+-------------+----+------------+
+0 8 12 16 20 32 36 47
+@end verbatim
+
+@item VRI format: <insn> V1,V2,I3,M4,M5
+@verbatim
++--------+----+----+-------------+----+----+------------+
+| OpCode | V1 | V2 | I3 | M5 | M4 | Opcode |
++--------+----+----+-------------+----+----+------------+
+0 8 12 16 28 32 36 47
+@end verbatim
+
+@item VRX format: <insn> V1,D2(R2,B2),M3
+@verbatim
++--------+----+----+----+-------------+----+------------+
+| OpCode | V1 | R2 | B2 | D2 | M3 | Opcode |
++--------+----+----+----+-------------+----+------------+
+0 8 12 16 20 32 36 47
+@end verbatim
+
+@item VRS format: <insn> R1,V3,D2(B2),M4
+@verbatim
++--------+----+----+----+-------------+----+------------+
+| OpCode | R1 | V3 | B2 | D2 | M4 | Opcode |
++--------+----+----+----+-------------+----+------------+
+0 8 12 16 20 32 36 47
+@end verbatim
+
+@item VRR format: <insn> V1,V2,V3,M4,M5,M6
+@verbatim
++--------+----+----+----+---+----+----+----+------------+
+| OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode |
++--------+----+----+----+---+----+----+----+------------+
+0 8 12 16 24 28 32 36 47
+@end verbatim
+
+@item VSI format: <insn> V1,D2(B2),I3
+@verbatim
++--------+---------+----+-------------+----+------------+
+| OpCode | I3 | B2 | D2 | V1 | Opcode |
++--------+---------+----+-------------+----+------------+
+0 8 16 20 32 36 47
+@end verbatim
+
@end table
For the complete list of all instruction format variants see the