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| author | David Guillen Fandos <david@davidgf.net> | 2024-06-11 09:36:11 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@redhat.com> | 2024-06-11 09:36:11 +0100 |
| commit | 60e221e9b7fae5ff40b79b93bdbff909989c2bae (patch) | |
| tree | 7182cd55c7d812f09e07bc35f73eb4d94e09bf3e | |
| parent | 1ded0d12e0ee5399a3c1d8606fd23491e00fc60f (diff) | |
| download | gdb-60e221e9b7fae5ff40b79b93bdbff909989c2bae.zip gdb-60e221e9b7fae5ff40b79b93bdbff909989c2bae.tar.gz gdb-60e221e9b7fae5ff40b79b93bdbff909989c2bae.tar.bz2 | |
MIPS/opcodes: Add MIPS Allegrex DBREAK instruction
This complements the debug instruction set and uses the same encoding as
the VR5400/VR5500 devices.
| -rw-r--r-- | gas/testsuite/gas/mips/allegrex.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/allegrex.s | 1 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 2 |
3 files changed, 4 insertions, 2 deletions
diff --git a/gas/testsuite/gas/mips/allegrex.d b/gas/testsuite/gas/mips/allegrex.d index d0f7967..b535c6d 100644 --- a/gas/testsuite/gas/mips/allegrex.d +++ b/gas/testsuite/gas/mips/allegrex.d @@ -46,5 +46,6 @@ Disassembly of section .text: 0x00000094 7002003d mfdr \$2,\$0 0x00000098 7002083d mfdr \$2,\$1 0x0000009c 7083083d mtdr \$3,\$1 -0x000000a0 7000003e dret +0x000000a0 7000003f dbreak +0x000000a4 7000003e dret \.\.\. diff --git a/gas/testsuite/gas/mips/allegrex.s b/gas/testsuite/gas/mips/allegrex.s index c367458..df05f97 100644 --- a/gas/testsuite/gas/mips/allegrex.s +++ b/gas/testsuite/gas/mips/allegrex.s @@ -40,6 +40,7 @@ mfdr $v0, $0 mfdr $v0, $1 mtdr $v1, $1 + dbreak dret # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index a31a17d..c6cbb66 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1030,7 +1030,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, -{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, +{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL, 0, 0 }, {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, |