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| author | Nathan Huckleberry <nhuck@google.com> | 2023-06-30 22:44:23 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:29:58 -0600 |
| commit | 5dfb644f9340bad1a4e8abaa512a637d39056649 (patch) | |
| tree | dbab1b14d8931f7e577576af8ef45cb14d698148 | |
| parent | 48558a5e5471a5b6d084dbb836af333b85b4123c (diff) | |
| download | gdb-5dfb644f9340bad1a4e8abaa512a637d39056649.zip gdb-5dfb644f9340bad1a4e8abaa512a637d39056649.tar.gz gdb-5dfb644f9340bad1a4e8abaa512a637d39056649.tar.bz2 | |
RISC-V: Add support for the Zvkng ISA extension
Zvkng is part of the vector crypto extensions.
Zvkng is shorthand for the following set of extensions:
- Zvkn
- Zvkg
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkng extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkng.d: New test.
* testsuite/gas/riscv/zvkng.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
| -rw-r--r-- | bfd/elfxx-riscv.c | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvkng.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvkng.s | 4 |
3 files changed, 19 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index f7fb7d8..60cd74f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1160,6 +1160,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvkn", "zvknha", check_implicit_always}, {"zvkn", "zvknhb", check_implicit_always}, {"zvkn", "zvbb", check_implicit_always}, + {"zvkng", "zvkn", check_implicit_always}, + {"zvkng", "zvkg", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1270,6 +1272,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/testsuite/gas/riscv/zvkng.d b/gas/testsuite/gas/riscv/zvkng.d new file mode 100644 index 0000000..1206350 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkng.d @@ -0,0 +1,12 @@ +#as: -march=rv64gc_zvkng +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12 diff --git a/gas/testsuite/gas/riscv/zvkng.s b/gas/testsuite/gas/riscv/zvkng.s new file mode 100644 index 0000000..5c24ffd --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkng.s @@ -0,0 +1,4 @@ + vaesdf.vv v4, v8 + vsha2ch.vv v4, v8, v12 + vghsh.vv v4, v8, v12 + vgmul.vv v4, v12 |