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authorNick Clifton <nickc@redhat.com>2001-02-15 02:38:15 +0000
committerNick Clifton <nickc@redhat.com>2001-02-15 02:38:15 +0000
commit44e23e575b7a78c3c9a6a65f49abbf8f6abf52fb (patch)
tree8ff88fd7c95c08fea28e797654d579cc56369ddc
parentad995491f834d95f3671f8fb96938be3f633f7de (diff)
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Add code to preserve processor mode when a prefetch
abort is signalled after processing a breakpoint.
-rw-r--r--sim/arm/ChangeLog3
-rw-r--r--sim/arm/armemu.c11
2 files changed, 14 insertions, 0 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 32e1056..4b1331a 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,5 +1,8 @@
2001-02-14 Nick Clifton <nickc@redhat.com>
+ * armemu.c: Add code to preserve processor mode when a prefetch
+ abort is signalled after processing a breakpoint.
+
* wrapper.c (sim_create_inferior): Reset processor into ARM mode
for any machine type except the early ARMs.
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 166f3aa..f0a6103 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -1340,6 +1340,7 @@ ARMul_Emulate26 (register ARMul_State * state)
{
ARMword value;
extern int SWI_vector_installed;
+ int in_thumb_mode;
/* Hardware is allowed to optionally override this
instruction and treat it as a breakpoint. Since
@@ -1377,7 +1378,17 @@ ARMul_Emulate26 (register ARMul_State * state)
}
}
+ /* We must signal an abort to mark the next instruction as
+ invalid and in need of refetching. This is because if this
+ the instruction was a breakpoint inserted by the debugger,
+ the instruction could be changed back to its original value.
+ The abort however, will automatically reset the processor into
+ ARM mode, so we have to preserve the mode flag and resort it
+ after singalling the abort. */
+ in_thumb_mode = TFLAG;
ARMul_Abort (state, ARMul_PrefetchAbortV);
+ ASSIGNT (in_thumb_mode);
+
break;
}
}