aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAlan Modra <amodra@gmail.com>2021-03-29 09:44:48 +1030
committerAlan Modra <amodra@gmail.com>2021-03-29 11:22:21 +1030
commit3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e (patch)
treea8319153e59bc6cc27da4ff12bfa95ee923019ff
parentf4f9ede04272c1417b187afe6964e5c0687f1904 (diff)
downloadgdb-3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e.zip
gdb-3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e.tar.gz
gdb-3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e.tar.bz2
opcodes int vs bfd_boolean fixes
cpu/ * frv.opc (frv_is_branch_major, frv_is_float_major), (frv_is_media_major, frv_is_branch_insn, frv_is_float_insn), (frv_is_media_insn, spr_valid): Correct prototypes. include/ * opcode/aarch64.h (aarch64_opcode_encode): Correct prototype. opcodes/ * arc-dis.c (extract_operand_value): Correct NULL cast. * frv-opc.h: Regenerate.
-rw-r--r--cpu/ChangeLog6
-rw-r--r--cpu/frv.opc18
-rw-r--r--include/ChangeLog4
-rw-r--r--include/opcode/aarch64.h2
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/arc-dis.c2
-rw-r--r--opcodes/frv-opc.h18
7 files changed, 35 insertions, 20 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 6384506..1684d26 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,9 @@
+2021-03-29 Alan Modra <amodra@gmail.com>
+
+ * frv.opc (frv_is_branch_major, frv_is_float_major),
+ (frv_is_media_major, frv_is_branch_insn, frv_is_float_insn),
+ (frv_is_media_insn, spr_valid): Correct prototypes.
+
2021-01-09 Nick Clifton <nickc@redhat.com>
* 2.36 release branch crated.
diff --git a/cpu/frv.opc b/cpu/frv.opc
index 1b0b05c..7863462 100644
--- a/cpu/frv.opc
+++ b/cpu/frv.opc
@@ -66,15 +66,15 @@ typedef struct
const CGEN_INSN * insn[FRV_VLIW_SIZE];
} FRV_VLIW;
-int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_branch_insn (const CGEN_INSN *);
-int frv_is_float_insn (const CGEN_INSN *);
-int frv_is_media_insn (const CGEN_INSN *);
-void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
-int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
-int spr_valid (long);
+bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_branch_insn (const CGEN_INSN *);
+bfd_boolean frv_is_float_insn (const CGEN_INSN *);
+bfd_boolean frv_is_media_insn (const CGEN_INSN *);
+void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
+int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
+bfd_boolean spr_valid (long);
/* -- */
/* -- opc.c */
diff --git a/include/ChangeLog b/include/ChangeLog
index 5fa6b09..afc1ac9 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2021-03-29 Alan Modra <amodra@gmail.com>
+
+ * opcode/aarch64.h (aarch64_opcode_encode): Correct prototype.
+
2021-03-25 Nick Alcock <nick.alcock@oracle.com>
PR libctf/27628
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f998691..dd4ab22 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1264,7 +1264,7 @@ struct aarch64_instr_sequence
/* Encoding entrypoint. */
-extern int
+extern bfd_boolean
aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
aarch64_insn *, aarch64_opnd_qualifier_t *,
aarch64_operand_error *, aarch64_instr_sequence *);
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0e2e94c..7a531b3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2021-03-29 Alan Modra <amodra@gmail.com>
+
+ * arc-dis.c (extract_operand_value): Correct NULL cast.
+ * frv-opc.h: Regenerate.
+
2021-03-26 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 0c9b379..a7e2db1 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -694,7 +694,7 @@ extract_operand_value (const struct arc_operand *operand,
else
{
if (operand->extract)
- value = (*operand->extract) (insn, (int *) NULL);
+ value = (*operand->extract) (insn, (bfd_boolean *) NULL);
else
{
if (operand->flags & ARC_OPERAND_ALIGNED32)
diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h
index 9fc6922..95f4797 100644
--- a/opcodes/frv-opc.h
+++ b/opcodes/frv-opc.h
@@ -58,15 +58,15 @@ typedef struct
const CGEN_INSN * insn[FRV_VLIW_SIZE];
} FRV_VLIW;
-int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_branch_insn (const CGEN_INSN *);
-int frv_is_float_insn (const CGEN_INSN *);
-int frv_is_media_insn (const CGEN_INSN *);
-void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
-int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
-int spr_valid (long);
+bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_branch_insn (const CGEN_INSN *);
+bfd_boolean frv_is_float_insn (const CGEN_INSN *);
+bfd_boolean frv_is_media_insn (const CGEN_INSN *);
+void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
+int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
+bfd_boolean spr_valid (long);
/* -- */
/* Enum declaration for frv instruction types. */
typedef enum cgen_insn_type {