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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-13 12:46:33 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-14 09:23:18 -0700 |
| commit | 2c232b8361a044d689d12161b7a645d238586f5e (patch) | |
| tree | 13d9921279be84a076b200f61f5b606d113ef0dc | |
| parent | 9216a6f33592c350ad50696d5571c82e47b71a5e (diff) | |
| download | gdb-2c232b8361a044d689d12161b7a645d238586f5e.zip gdb-2c232b8361a044d689d12161b7a645d238586f5e.tar.gz gdb-2c232b8361a044d689d12161b7a645d238586f5e.tar.bz2 | |
RISC-V: Fix [dis]assembly of srai/srli
These were simple copy/paste errors from the compressed left shift
pattern, which can't have a 0-register.
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 8 |
2 files changed, 11 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f9f2c04..622ccf4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2017-03-13 Andrew Waterman <andrew@sifive.com> + + * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. + <srl> Likewise. + <srai> Likewise. + <sra> Likewise. + 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Replace S with Load. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 61d0159..1bb90ee 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -210,14 +210,14 @@ const struct riscv_opcode riscv_opcodes[] = {"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, {"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, {"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, -{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, {"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, -{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, {"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, {"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, -{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, {"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, -{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, {"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, {"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, {"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, |