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path: root/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
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/* { dg-do compile } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */
/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_
xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
xtheadmemidx_xtheadmempair_xtheadsync */

#if !((__riscv_xlen == 64)		\
      && !defined(__riscv_32e)		\
      && defined(__riscv_mul)		\
      && defined(__riscv_atomic)	\
      && (__riscv_flen == 64)		\
      && defined(__riscv_compressed)	\
      && defined(__riscv_zicntr)		\
      && defined(__riscv_zicsr)		\
      && defined(__riscv_zifencei)		\
      && defined(__riscv_zihpm)		\
      && defined(__riscv_zfh)		\
      && defined(__riscv_xtheadba)		\
      && defined(__riscv_xtheadbb)		\
      && defined(__riscv_xtheadbs)		\
      && defined(__riscv_xtheadcmo)		\
      && defined(__riscv_xtheadcondmov)		\
      && defined(__riscv_xtheadfmemidx)		\
      && defined(__riscv_xtheadmac)		\
      && defined(__riscv_xtheadmemidx)		\
      && defined(__riscv_xtheadmempair)		\
      && defined(__riscv_xtheadsync))
#error "unexpected arch"
#endif

int main()
{
  return 0;
}