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path: root/gcc/config/i386/i386-expand.c
AgeCommit message (Expand)AuthorFilesLines
2022-10-17Remove accidential commitsJeff Law1-20310/+0
2022-10-17Enable REE for H8Jeff Law1-0/+20310
2022-01-17Rename .c files to .cc files.Martin Liska1-23280/+0
2022-01-17widening_mul, i386: Improve spaceship expansion on x86 [PR103973]Jakub Jelinek1-0/+49
2022-01-15i386: Improve and optimize ix86_expand_sse_movccUros Bizjak1-77/+61
2022-01-14x86_64: Improvements to arithmetic right shifts of V1TImode values.Roger Sayle1-169/+96
2022-01-12i386: Add CC clobber and splits for 32-bit vector mode logic insns [PR100673,...Uros Bizjak1-13/+28
2022-01-11i386: Introduce V2QImode vector cmove for -msse4.1 [PR103861]Uros Bizjak1-4/+12
2022-01-10i386: Introduce V2QImode vector compares [PR103861]Uros Bizjak1-0/+7
2022-01-08x86_64: Improve (interunit) moves from TImode to V1TImode.Roger Sayle1-0/+17
2022-01-07Optimize V16HF vector insert to element 0 for AVX2.liuhongt1-2/+3
2022-01-05i386: Fix expand_vec_perm_pshufb for narrow modes [PR103905]Uros Bizjak1-11/+12
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-14i386: Implement VxHF vector set/insert/extract with lower ABI levelsUros Bizjak1-35/+83
2021-12-03x86: Add -mmove-max=bits and -mstore-max=bitsH.J. Lu1-0/+1
2021-12-03Add TARGET_IFUNC_REF_LOCAL_OKH.J. Lu1-1/+1
2021-12-01i386: Improve V8HI and V8HF inserts [PR102811]Uros Bizjak1-11/+1
2021-11-29x86_64: Improved V1TImode rotations by non-constant amounts.Roger Sayle1-1/+11
2021-11-18i386: Fix wrong codegen for -mrelax-cmpxchg-loopHongyu Wang1-1/+6
2021-11-15PR target/103069: Relax cmpxchg loop for x86 targetHongyu Wang1-0/+76
2021-11-02x86_64: Expand ashrv1ti (and PR target/102986)Roger Sayle1-5/+523
2021-10-29Enable vectorization for _Float16 floor/ceil/trunc/nearbyint/rint operations.liuhongt1-0/+3
2021-10-26x86_64: Implement V1TI mode shifts/rotates by a constantRoger Sayle1-0/+163
2021-10-15AVX512FP16: Enhance vector shuffle builtinsHongyu Wang1-0/+24
2021-10-15AVX512FP16: Fix ICE for 2 v4hf vector concatHongyu Wang1-1/+2
2021-10-14AVX512FP16: Adjust builtin for mask complex fmaHongyu Wang1-1/+21
2021-10-13x86_64: Some SUBREG related optimization tweaks to i386 backend.Roger Sayle1-2/+16
2021-10-12Support reduc_{plus,smax,smin,umax,umin}_scal_v4qi.liuhongt1-0/+5
2021-10-09Refine movhfcc.liuhongt1-4/+15
2021-10-08Support reduc_{plus,smax,smin,umax,min}_scal_v4hi.liuhongt1-0/+5
2021-09-28Support 128/256/512-bit vector plus/smin/smax reduction for _Float16.liuhongt1-0/+3
2021-09-23AVX512FP16: Enable vec_cmpmn/vcondmn expanders for HF modes.Hongyu Wang1-0/+2
2021-09-22AVX512FP16: Add vfcmaddcph/vfmaddcph/vfcmulcph/vfmulcphliuhongt1-0/+5
2021-09-18AVX512FP16: Add scalar fma instructions.liuhongt1-0/+1
2021-09-18AVX512FP16: Add scalar/vector bitwise operations, includingH.J. Lu1-4/+12
2021-09-17AVX512FP16: Add vcvtsh2ss/vcvtsh2sd/vcvtss2sh/vcvtsd2sh.liuhongt1-0/+4
2021-09-17AVX512FP16: Add vcvtph2pd/vcvtph2psx/vcvtpd2ph/vcvtps2phx.liuhongt1-0/+12
2021-09-17AVX512FP16: Add vcvtsh2si/vcvtsh2usi/vcvtsi2sh/vcvtusi2sh.liuhongt1-0/+8
2021-09-16AVX512FP16: Add vcvtuw2ph/vcvtw2ph/vcvtdq2ph/vcvtudq2ph/vcvtqq2ph/vcvtuqq2phliuhongt1-0/+9
2021-09-16AVX512FP16: Add vcvtph2dq/vcvtph2qq/vcvtph2w/vcvtph2uw/vcvtph2uqq/vcvtph2udqliuhongt1-0/+9
2021-09-16AVX512FP16: Add vmovw/vmovsh.liuhongt1-0/+11
2021-09-15Optimize for V{8,16,32}HFmode vec_set/extract/init.liuhongt1-36/+59
2021-09-14AVX512FP16: Add fpclass/getexp/getmant instructions.liuhongt1-0/+7
2021-09-14AVX512FP16: Add vreduceph/vreducesh/vrndscaleph/vrndscalesh.liuhongt1-0/+4
2021-09-14AVX512FP16: Add vsqrtph/vrsqrtph/vsqrtsh/vrsqrtsh.liuhongt1-0/+4
2021-09-10AVX512FP16: Add vcmpph/vcmpsh/vcomish/vucomish.liuhongt1-0/+10
2021-09-10AVX512FP16: Add vmaxph/vminph/vmaxsh/vminsh.liuhongt1-0/+2
2021-09-10AVX512FP16: Add vaddsh/vsubsh/vmulsh/vdivsh.Liu, Hongtao1-0/+2
2021-09-10AVX512FP16: Enable _Float16 autovectorizationH.J. Lu1-0/+4
2021-09-10Remove copysign post_reload splitter for scalar modes.liuhongt1-126/+26