diff options
Diffstat (limited to 'gcc/testsuite/lib')
| -rw-r--r-- | gcc/testsuite/lib/gcc-defs.exp | 16 | ||||
| -rw-r--r-- | gcc/testsuite/lib/gcc-dg.exp | 4 | ||||
| -rw-r--r-- | gcc/testsuite/lib/multiline.exp | 3 | ||||
| -rw-r--r-- | gcc/testsuite/lib/profopt.exp | 2 | ||||
| -rw-r--r-- | gcc/testsuite/lib/rust.exp | 5 | ||||
| -rw-r--r-- | gcc/testsuite/lib/sarif.py | 2 | ||||
| -rw-r--r-- | gcc/testsuite/lib/scanasm.exp | 4 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 246 |
8 files changed, 211 insertions, 71 deletions
diff --git a/gcc/testsuite/lib/gcc-defs.exp b/gcc/testsuite/lib/gcc-defs.exp index 2f8b7d4..d66c833 100644 --- a/gcc/testsuite/lib/gcc-defs.exp +++ b/gcc/testsuite/lib/gcc-defs.exp @@ -599,15 +599,16 @@ proc aarch64-arch-dg-options { args } { set add_arch 1 set add_tune 1 + set add_override 1 set checks_output [string equal [lindex $do_what 0] "compile"] set options [lindex $args 1] foreach option [split $options] { switch -glob -- $option { -march=* { set add_arch 0 } - -mcpu=* { set add_arch 0; set add_tune 0 } - -mtune=* { set add_tune 0 } - -moverride=* { set add_tune 0 } + -mcpu=* { set add_arch 0; set add_tune 0; set add_override 0} + -mtune=* { set add_tune 0; set add_override 0 } + -moverride=* { set add_override 0 } -save-temps { set checks_output 1 } --save-temps { set checks_output 1 } -fdump* { set checks_output 1 } @@ -619,9 +620,14 @@ proc aarch64-arch-dg-options { args } { append options " $aarch64_default_testing_arch" } - if { $add_tune && $checks_output } { + if { $checks_output } { # Turn off any default tuning and codegen tweaks. - append options " -mtune=generic -moverride=tune=none" + if { $add_tune } { + append options " -mtune=generic" + } + if { $add_override } { + append options " -moverride=tune=none" + } } uplevel 1 aarch64-old-dg-options [lreplace $args 1 1 $options] diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp index 312c4b8..859a943 100644 --- a/gcc/testsuite/lib/gcc-dg.exp +++ b/gcc/testsuite/lib/gcc-dg.exp @@ -1338,8 +1338,8 @@ proc dg-missed { args } { } # Look for messages with 'note: ' prefixes. -# In addition to standard compiler diagnostics ('DK_NOTE', 'inform' functions, -# "for additional details on an error message"), +# In addition to standard compiler diagnostics (diagnostics::kind::note, +# 'inform' functions, "for additional details on an error message"), # this also includes output from '-fopt-info' for 'MSG_NOTE': # a general optimization info. # By default, any *excess* notes are pruned, meaning their appearance doesn't diff --git a/gcc/testsuite/lib/multiline.exp b/gcc/testsuite/lib/multiline.exp index 08fd969..6865047 100644 --- a/gcc/testsuite/lib/multiline.exp +++ b/gcc/testsuite/lib/multiline.exp @@ -153,6 +153,9 @@ proc handle-multiline-outputs { text } { # If dg-enable-nn-line-numbers was provided, then obscure source-margin # line numbers by converting them to "NN" form. set text [maybe-handle-nn-line-numbers $text] + + # Remove Windows .exe suffix + regsub -all "(as|cc1|cc1plus|collect2|f951|ld|lto-wrapper)\.exe?:" $text {\1:} text set index 0 foreach entry $multiline_expected_outputs { diff --git a/gcc/testsuite/lib/profopt.exp b/gcc/testsuite/lib/profopt.exp index b4d244b..81d86c6 100644 --- a/gcc/testsuite/lib/profopt.exp +++ b/gcc/testsuite/lib/profopt.exp @@ -382,6 +382,7 @@ proc profopt-execute { src } { unsupported "$testcase" unset testname_with_flags verbose "$src not supported on this target, skipping it" 3 + cleanup-after-saved-dg-test return } @@ -458,6 +459,7 @@ proc profopt-execute { src } { unsupported "$testcase -fauto-profile: cannot run create_gcov" unset testname_with_flags set status "fail" + cleanup-after-saved-dg-test return } set status [remote_wait "" 300] diff --git a/gcc/testsuite/lib/rust.exp b/gcc/testsuite/lib/rust.exp index 9513e1c..692030c 100644 --- a/gcc/testsuite/lib/rust.exp +++ b/gcc/testsuite/lib/rust.exp @@ -168,10 +168,7 @@ proc rust_target_compile { source dest type options } { global gluefile wrap_flags global ALWAYS_RUSTFLAGS global RUST_UNDER_TEST - global individual_timeout - - # HACK: guard against infinite loops in the compiler - set individual_timeout 10 + if { [target_info needs_status_wrapper] != "" && [info exists gluefile] } { lappend options "libs=${gluefile}" diff --git a/gcc/testsuite/lib/sarif.py b/gcc/testsuite/lib/sarif.py index 06d05c0..d75a87e 100644 --- a/gcc/testsuite/lib/sarif.py +++ b/gcc/testsuite/lib/sarif.py @@ -30,7 +30,7 @@ def get_result_by_index(sarif, idx): return results[idx] def get_state_graph(events, event_idx): - graph = events[event_idx]['properties']['gcc/diagnostic_event/state_graph'] + graph = events[event_idx]['properties']['gcc/diagnostics/paths/event/state_graph'] if 0: print(graph) assert graph is not None diff --git a/gcc/testsuite/lib/scanasm.exp b/gcc/testsuite/lib/scanasm.exp index a2311de..51952a6 100644 --- a/gcc/testsuite/lib/scanasm.exp +++ b/gcc/testsuite/lib/scanasm.exp @@ -896,6 +896,10 @@ proc configure_check-function-bodies { config } { set up_config(fluff) {^\s*(?://)} } elseif { [istarget *-*-darwin*] } { set up_config(fluff) {^\s*(?:\.|//|@)|^L[0-9ABCESV]} + } elseif { [istarget s390*-*-*] } { + # Additionally to the defaults skip lines beginning with a # resulting + # from inline asm. + set up_config(fluff) {^\s*(?:\.|//|@|$|#)} } else { # Skip lines beginning with labels ('.L[...]:') or other directives # ('.align', '.cfi_startproc', '.quad [...]', '.text', etc.), '//' or diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 9ab46a0..957fa7f 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1017,6 +1017,18 @@ proc check_effective_target_label_values {} { return 1 } + +# Return 1 if builtin_trap expands not into a call but an instruction, +# 0 otherwise. +proc check_effective_target_trap { } { + return [check_no_messages_and_pattern trap "!\\(call" rtl-expand { + void foo () + { + return __builtin_trap (); + } + } "" ] +} + # Return 1 if builtin_return_address and builtin_frame_address are # supported, 0 otherwise. @@ -2242,6 +2254,32 @@ proc check_effective_target_riscv_xtheadvector { } { } +# Return 1 if we can execute code when using dg-add-options riscv_b + +proc check_effective_target_riscv_b_ok { } { + # If the target already supports zbb without any added options, + # we may assume we can execute just fine. + # Technically we should really check for zba/zbs too, but I haven't + # seen a design that implements a subset of zba/zbb/zbs yet. + if { [check_effective_target_riscv_zbb] } { + return 1 + } + + # check if we can execute bitmanip insns with the given hardware or + # simulator + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &b] + if { [check_runtime ${gcc_march}_exec { + int main() { asm("sh2add t0, a0, a1"); return 0; } } "-march=${gcc_march}"] } { + return 1 + } + + # Possible future extensions: If the target is a simulator, dg-add-options + # might change its config to make it allow vector insns, or we might use + # options to set special elf flags / sections to effect that. + + return 0 +} + # Return 1 if we can execute code when using dg-add-options riscv_v proc check_effective_target_riscv_v_ok { } { @@ -2304,7 +2342,7 @@ proc check_effective_target_riscv_zvfh_ok { } { # check if we can execute vector insns with the given hardware or # simulator - set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v] + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &zvfh] if { [check_runtime ${gcc_march}_zvfh_exec { int main() { @@ -2428,7 +2466,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; asm ("vsetivli zero,7,e8,m1,ta,ma"); asm ("addi a7,%0,1" : : "r" (a) : "a7" ); - asm ("vle8.v v8,0(a7)" : : : "v8"); + asm ("vle16.v v8,0(a7)" : : : "v8"); return 0; } } "-march=${gcc_march}"] } { return 1 } @@ -2673,10 +2711,6 @@ proc remove_options_for_riscv_ztso { flags } { return [remove_options_for_riscv_z_ext ztso $flags] } -proc remove_options_for_riscv_zvfh { flags } { - return [add_options_for_riscv_z_ext zvfh $flags] -} - proc add_options_for_riscv_zvbb { flags } { return [add_options_for_riscv_z_ext zvbb $flags] } @@ -2685,6 +2719,14 @@ proc remove_options_for_riscv_zvbb { flags } { return [add_options_for_riscv_z_ext zvbb $flags] } +proc add_options_for_riscv_zvfh { flags } { + return [add_options_for_riscv_z_ext zvfh $flags] +} + +proc remove_options_for_riscv_zvfh { flags } { + return [remove_options_for_riscv_z_ext zvfh $flags] +} + # Return 1 if the target is ia32 or x86_64. proc check_effective_target_x86 { } { @@ -4597,7 +4639,7 @@ proc add_options_for_vect_early_break { flags } { if { [check_effective_target_arm_v8_neon_ok] } { global et_arm_v8_neon_flags - return "$flags $et_arm_v8_neon_flags -mcpu=unset -march=armv8-a" + return "$flags $et_arm_v8_neon_flags" } if { [check_effective_target_sse4] } { @@ -5420,7 +5462,7 @@ proc add_options_for_arm_v8_neon { flags } { return "$flags" } global et_arm_v8_neon_flags - return "$flags $et_arm_v8_neon_flags -mcpu=unset -march=armv8-a" + return "$flags $et_arm_v8_neon_flags" } # Add the options needed for ARMv8.1 Adv.SIMD. Also adds the ARMv8 NEON @@ -5491,25 +5533,26 @@ proc add_options_for_arm_vfp3 { flags } { # best options to add. proc check_effective_target_arm_neon_ok_nocache { } { + if { ![istarget arm*-*-*] } { + return 0 + } global et_arm_neon_flags set et_arm_neon_flags "" - if { [check_effective_target_arm32] } { - foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -mcpu=unset -march=armv7-a" "-mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard -mcpu=unset -march=armv7-a"} { - if { [check_no_compiler_messages_nocache arm_neon_ok object { - #include <arm_neon.h> - int dummy; - #ifndef __ARM_NEON__ - #error not NEON - #endif - /* Avoid the case where a test adds -mfpu=neon, but the toolchain is - configured for -mcpu=arm926ej-s, for example. */ - #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M' - #error Architecture does not support NEON. - #endif - } "$flags"] } { - set et_arm_neon_flags $flags - return 1 - } + foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -mcpu=unset -march=armv7-a" "-mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard -mcpu=unset -march=armv7-a"} { + if { [check_no_compiler_messages_nocache arm_neon_ok object { + #include <arm_neon.h> + int dummy; + #ifndef __ARM_NEON__ + #error not NEON + #endif + /* Avoid the case where a test adds -mfpu=neon, but the toolchain is + configured for -mcpu=arm926ej-s, for example. */ + #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M' + #error Architecture does not support NEON. + #endif + } "$flags"] } { + set et_arm_neon_flags $flags + return 1 } } @@ -5695,8 +5738,7 @@ proc check_effective_target_arm_neon_fp16_ok_nocache { } { global et_arm_neon_fp16_flags global et_arm_neon_flags set et_arm_neon_fp16_flags "" - if { [check_effective_target_arm32] - && [check_effective_target_arm_neon_ok] } { + if { [check_effective_target_arm_neon_ok] } { foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp" "-mfp16-format=ieee" @@ -5734,8 +5776,7 @@ proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } { global et_arm_neon_softfp_fp16_flags global et_arm_neon_flags set et_arm_neon_softfp_fp16_flags "" - if { [check_effective_target_arm32] - && [check_effective_target_arm_neon_ok] } { + if { [check_effective_target_arm_neon_ok] } { foreach flags {"-mfpu=neon-fp16 -mfloat-abi=softfp" "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} { if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object { @@ -5800,6 +5841,13 @@ proc add_options_for_aarch64_sve { flags } { return "$flags -march=armv8.2-a+sve" } +proc add_options_for_aarch64_sme { flags } { + if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sme] } { + return "$flags" + } + return "$flags -march=armv9-a+sme" +} + # Return 1 if this is an ARM target supporting the FP16 alternative # format. Some multilibs may be incompatible with the options needed. Also # set et_arm_fp16_alternative_flags to the best options to add. @@ -5871,22 +5919,20 @@ proc check_effective_target_arm_fp16_none_ok { } { proc check_effective_target_arm_v8_neon_ok_nocache { } { global et_arm_v8_neon_flags set et_arm_v8_neon_flags "" - if { [check_effective_target_arm32] } { - foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} { - if { [check_no_compiler_messages_nocache arm_v8_neon_ok object { - #if __ARM_ARCH < 8 - #error not armv8 or later - #endif - #include "arm_neon.h" - void - foo () - { - __asm__ volatile ("vrintn.f32 q0, q0"); - } - } "$flags -mcpu=unset -march=armv8-a"] } { - set et_arm_v8_neon_flags $flags - return 1 + foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} { + if { [check_no_compiler_messages_nocache arm_v8_neon_ok object { + #if __ARM_ARCH < 8 + #error not armv8 or later + #endif + #include "arm_neon.h" + void + foo () + { + __asm__ volatile ("vrintn.f32 q0, q0"); } + } "$flags -mcpu=unset -march=armv8-a"] } { + set et_arm_v8_neon_flags "$flags -mcpu=unset -march=armv8-a" + return 1 } } @@ -5907,8 +5953,7 @@ proc check_effective_target_arm_neonv2_ok_nocache { } { global et_arm_neonv2_flags global et_arm_neon_flags set et_arm_neonv2_flags "" - if { [check_effective_target_arm32] - && [check_effective_target_arm_neon_ok] } { + if { [check_effective_target_arm_neon_ok] } { foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} { if { [check_no_compiler_messages_nocache arm_neonv2_ok object { #include "arm_neon.h" @@ -6073,6 +6118,7 @@ foreach { armfunc armflag armdefs } { v6z_arm "-march=armv6z+fp -marm" "__ARM_ARCH_6Z__ && !__thumb__" v6z_thumb "-march=armv6z+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6Z__ && __thumb__" v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__ + v7 "-march=armv7+fp" __ARM_ARCH_7__ v7a "-march=armv7-a+fp" __ARM_ARCH_7A__ v7a_arm "-march=armv7-a+fp -marm" "__ARM_ARCH_7A__ && !__thumb__" v7a_fp_hard "-march=armv7-a+fp -mfpu=auto -mfloat-abi=hard" __ARM_ARCH_7A__ @@ -6539,6 +6585,22 @@ foreach N { 128 256 512 1024 2048 } { }] } +# Return true if this is an AArch64 target that can run SME code. + +proc check_effective_target_aarch64_sme_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_sme_hw_available { + int + main (void) + { + asm volatile ("rdsvl x0, #1"); + return 0; + } + } [add_options_for_aarch64_sme ""]] +} + proc check_effective_target_arm_neonv2_hw { } { return [check_runtime arm_neon_hwv2_available { #include "arm_neon.h" @@ -8803,7 +8865,7 @@ proc check_effective_target_vect_pack_trunc { } { expr { [istarget powerpc*-*-*] || [check_effective_target_x86] || [istarget aarch64*-*-*] - || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok] + || ([check_effective_target_arm_neon_ok] && [check_effective_target_arm_little_endian]) || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) @@ -8829,7 +8891,7 @@ proc check_effective_target_vect_unpack { } { || [istarget aarch64*-*-*] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) - || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok] + || ([check_effective_target_arm_neon_ok] && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) @@ -9516,8 +9578,7 @@ proc check_effective_target_vect_condition { } { || [check_effective_target_x86] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok]) + || [check_effective_target_arm_neon_ok] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] @@ -9535,8 +9596,7 @@ proc check_effective_target_vect_cond_mixed { } { expr { [check_effective_target_x86] || [istarget aarch64*-*-*] || [istarget powerpc*-*-*] - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok]) + || [check_effective_target_arm_neon_ok] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] @@ -9717,8 +9777,7 @@ proc available_vector_sizes { } { lappend result [aarch64_sve_bits] } lappend result 128 64 - } elseif { [istarget arm*-*-*] - && [check_effective_target_arm_neon_ok] } { + } elseif { [check_effective_target_arm_neon_ok] } { lappend result 128 64 } elseif { [check_effective_target_x86] } { if { [check_avx_available] && ![check_prefer_avx128] } { @@ -9961,7 +10020,8 @@ proc check_effective_target_vect_logical_reduc { } { || [istarget amdgcn-*-*] || [check_effective_target_riscv_v] || [check_effective_target_loongarch_sx] - || [check_effective_target_x86]}] + || [check_effective_target_x86] + || [check_effective_target_s390_vx]}] } # Return 1 if the target supports the fold_extract_last optab. @@ -12478,10 +12538,16 @@ proc check_effective_target_aarch64_gas_has_build_attributes { } { # various architecture extensions via the .arch_extension pseudo-op. set exts { - "bf16" "cmpbr" "crc" "crypto" "dotprod" "f32mm" "f64mm" "fp" "fp8" - "fp8dot2" "fp8dot4" "fp8fma" "i8mm" "ls64" "lse" "lut" "sb" "simd" - "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "ssve-fp8dot2" - "ssve-fp8dot4" "ssve-fp8fma" "sve-b16b16" "sve" "sve2" + "bf16" "cmpbr" "crc" "crypto" "dotprod" "f32mm" "f64mm" "faminmax" + "fp" "fp8" "fp8dot2" "fp8dot4" "fp8fma" "i8mm" "ls64" "lse" "lut" + "sb" "simd" "sve-b16b16" "sve" "sve2" +} + +# We don't support SME without SVE2, so we'll use armv9 as the base +# archiecture for SME and the features that require it. +set exts_sve2 { + "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" + "ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" } foreach { aarch64_ext } $exts { @@ -12498,6 +12564,20 @@ foreach { aarch64_ext } $exts { }] } +foreach { aarch64_ext } $exts_sve2 { + eval [string map [list FUNC $aarch64_ext] { + proc check_effective_target_aarch64_asm_FUNC_ok { } { + if { [istarget aarch64*-*-*] } { + return [check_no_compiler_messages aarch64_FUNC_assembler object { + __asm__ (".arch_extension FUNC"); + } "-march=armv9-a+FUNC"] + } else { + return 0 + } + } + }] +} + proc check_effective_target_aarch64_asm_sve2p1_ok { } { if { [istarget aarch64*-*-*] } { return [check_no_compiler_messages aarch64_sve2p1_assembler object { @@ -14528,3 +14608,51 @@ proc check_effective_target_foldable_pi_based_trigonometry { } { } }] } +# +# Return 1 if the x86-64 target enables -mfentry by default, 0 +# otherwise. Cache the result. + +proc check_effective_target_fentry { } { + global tool + global GCC_UNDER_TEST + + if { ![check_effective_target_x86] } { + return 0 + } + + # Need auto-host.h to check linker support. + if { ![file exists ../../auto-host.h ] } { + return 0 + } + + return [check_cached_effective_target fentry { + # Set up and compile to see if ENABLE_X86_64_MFENTRY is + # non-zero. Include the current process ID in the file + # names to prevent conflicts with invocations for multiple + # testsuites. + + set src pie[pid].c + set obj pie[pid].o + + set f [open $src "w"] + puts $f "#include \"../../auto-host.h\"" + puts $f "#if ENABLE_X86_64_MFENTRY == 0 || !defined __x86_64__" + puts $f "# error -mfentry is not enabled by default." + puts $f "#endif" + close $f + + verbose "check_effective_target_fentry compiling testfile $src" 2 + set lines [${tool}_target_compile $src $obj object ""] + + file delete $src + file delete $obj + + if [string match "" $lines] then { + verbose "check_effective_target_fentry testfile compilation passed" 2 + return 1 + } else { + verbose "check_effective_target_fentry testfile compilation failed" 2 + return 0 + } + }] +} |