diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
56 files changed, 766 insertions, 89 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c new file mode 100644 index 0000000..e49ace1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_1.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.2-a+fp16" } */ + +/* +** test_fcmp_store: +** fcmp h0, h1 +** cset w0, eq +** ret +*/ +int +test_fcmp_store(_Float16 a, _Float16 b) +{ + return a == b; +} + +/* +** test_fcmpe_store: +** fcmpe h0, h1 +** cset w0, mi +** ret +*/ +int +test_fcmpe_store(_Float16 a, _Float16 b) +{ + return a < b; +} + +/* +** test_fcmp_branch: +** fcmp h0, h1 +** ... +*/ +_Float16 +test_fcmp_branch(_Float16 a, _Float16 b) +{ + if (a == b) + return a * b; + return a; +} + +/* +** test_fcmpe_branch: +** fcmpe h0, h1 +** ... +*/ +_Float16 +test_fcmpe_branch(_Float16 a, _Float16 b) +{ + if (a < b) + return a * b; + return a; +} + +/* { dg-final { check-function-bodies "**" "" "" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c new file mode 100644 index 0000000..0ff7cda --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/_Float16_cmp_2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.2-a+nofp16" } */ + +#include "_Float16_cmp_1.c" + +/* { dg-final { scan-assembler-not {\tfcmp\th[0-9]+} } } */ +/* { dg-final { scan-assembler-not {\tfcmpe\th[0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c index 0892ce7..a653296 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -39,7 +35,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -51,17 +46,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vld1_x2 and vld1q_x2. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c index 9465e4a..832ee75 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -40,7 +36,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -52,17 +47,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c index a1461fd..e5f55f0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <stdbool.h> #include <arm_neon.h> #include "arm-neon-ref.h" @@ -42,8 +38,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (poly64, 1, _p64) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -55,18 +49,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (poly64, 2, q_p64) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vld1_x4 and vld1q_x4. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c index 3cf5eb3..8399290 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -39,7 +35,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -51,17 +46,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vst1_x2 and vst1q_x2. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c index c05f8e7..e7d9e02 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -40,7 +36,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -52,17 +47,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vst1_x3 and vst1q_x3. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c index a9867c3..83b0567 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c @@ -1,7 +1,3 @@ -/* We haven't implemented these intrinsics for arm yet. */ -/* { dg-skip-if "unimplemented" { arm*-*-* } } */ -/* { dg-options "-O3" } */ - #include <arm_neon.h> #include "arm-neon-ref.h" @@ -41,8 +37,6 @@ VARIANT (int32, 2, _s32) \ VARIANT (int64, 1, _s64) \ VARIANT (poly8, 8, _p8) \ VARIANT (poly16, 4, _p16) \ -VARIANT (poly64, 1, _p64) \ -VARIANT (float16, 4, _f16) \ VARIANT (float32, 2, _f32) \ VARIANT (uint8, 16, q_u8) \ VARIANT (uint16, 8, q_u16) \ @@ -54,18 +48,30 @@ VARIANT (int32, 4, q_s32) \ VARIANT (int64, 2, q_s64) \ VARIANT (poly8, 16, q_p8) \ VARIANT (poly16, 8, q_p16) \ -VARIANT (poly64, 2, q_p64) \ -VARIANT (float16, 8, q_f16) \ VARIANT (float32, 4, q_f32) +#if defined (__ARM_FP16_FORMAT_IEEE) \ + || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \ + || defined (__aarch64__) +#define VARIANTS_F16(VARIANT) \ + VARIANT (float16, 4, _f16) \ + VARIANT (float16, 8, q_f16) +#else +#define VARIANTS_F16(VARIANTS_F16) +#endif + #ifdef __aarch64__ #define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) \ +VARIANT (poly64, 1, _p64) \ +VARIANT (poly64, 2, q_p64) \ VARIANT (mfloat8, 8, _mf8) \ VARIANT (mfloat8, 16, q_mf8) \ VARIANT (float64, 1, _f64) \ VARIANT (float64, 2, q_f64) #else -#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) +#define VARIANTS(VARIANT) VARIANTS_1(VARIANT) \ +VARIANTS_F16(VARIANT) #endif /* Tests of vst1_x4 and vst1q_x4. */ diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c index dcac6d5..3799fb4 100644 --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c @@ -315,3 +315,18 @@ #ifndef __ARM_FEATURE_FP8DOT2 #error Foo #endif + +#pragma GCC target "arch=armv9.4-a" +#ifdef __ARM_FEATURE_FAMINMAX +#error Foo +#endif + +#pragma GCC target "arch=armv9.5-a" +#ifndef __ARM_FEATURE_FAMINMAX +#error Foo +#endif + +#pragma GCC target "arch=armv8-a+faminmax" +#ifndef __ARM_FEATURE_FAMINMAX +#error Foo +#endif diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c b/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c index 5b26081..5eb60d9 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c @@ -1,11 +1,10 @@ /* { dg-do compile } */ /* { dg-options "-mavx512vl -mavx512bw -mavx512dq -O2 -masm=att -mstv -mno-stackrealign" } */ /* { dg-final { scan-assembler-not {not[bwlqd]\]} } } */ -/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$5} 4} } */ -/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$6} 4} } */ +/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$5} 2} } */ +/* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$6} 3} } */ /* { dg-final { scan-assembler-times {(?n)vpcmp[bwdq][ \t]*\$[37]} 4} } */ -/* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$5} 2} } */ -/* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$6} 2} } */ +/* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$6} 1} } */ /* { dg-final { scan-assembler-times {(?n)vcmpp[sd][ \t]*\$7} 2} } */ #include<immintrin.h> @@ -20,20 +19,14 @@ FOO (__m128i,, epi8, __mmask16, 128, 1); FOO (__m128i,, epi16, __mmask8, 128, 1); -FOO (__m128i,, epi32, __mmask8, 128, 1); -FOO (__m128i,, epi64, __mmask8, 128, 1); FOO (__m256i, 256, epi8, __mmask32, 256, 2); FOO (__m256i, 256, epi16, __mmask16, 256, 2); FOO (__m256i, 256, epi32, __mmask8, 256, 2); -FOO (__m256i, 256, epi64, __mmask8, 256, 2); FOO (__m512i, 512, epi8, __mmask64, 512, 3); FOO (__m512i, 512, epi16, __mmask32, 512, 3); FOO (__m512i, 512, epi32, __mmask16, 512, 3); FOO (__m512i, 512, epi64, __mmask8, 512, 3); -FOO (__m128,, ps, __mmask8, 128, 1); -FOO (__m128d,, pd, __mmask8, 128, 1); FOO (__m256, 256, ps, __mmask8, 256, 2); -FOO (__m256d, 256, pd, __mmask8, 256, 2); FOO (__m512, 512, ps, __mmask16, 512, 3); FOO (__m512d, 512, pd, __mmask8, 512, 3); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c index ef6a525..37ca646 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtuq-1.c @@ -12,5 +12,5 @@ void extern avx512f_test (void) { m = _mm512_cmpgt_epu64_mask (x, x); - m = _mm512_mask_cmpgt_epu64_mask (3, x, x); + m = _mm512_mask_cmpgt_epu64_mask (5, x, x); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr103750-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr103750-1.c new file mode 100644 index 0000000..a15fae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr103750-1.c @@ -0,0 +1,79 @@ +/* PR target/103750 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl" } */ +/* { dg-final { scan-assembler-not "and" } } */ + +#include <immintrin.h> +extern __m128i* pi128; +extern __m256i* pi256; + +extern __m128* ps128; +extern __m256* ps256; + +extern __m128d* pd128; +extern __m256d* pd256; + +extern char a; +void +foo () +{ + __mmask8 mask1 = _mm_cmpeq_epu32_mask (pi128[0], pi128[1]); + a = mask1 & 15; +} + +void +foo1 () +{ + __mmask8 mask1 = _mm_cmpeq_epu64_mask (pi128[0], pi128[1]); + a = mask1 & 3; +} + +void +foo2 () +{ + __mmask8 mask1 = _mm256_cmpeq_epu64_mask (pi256[0], pi256[1]); + a = mask1 & 15; +} + +void +sign_foo () +{ + __mmask8 mask1 = _mm_cmpeq_epi32_mask (pi128[0], pi128[1]); + a = mask1 & 15; +} + +void +sign_foo1 () +{ + __mmask8 mask1 = _mm_cmpeq_epi64_mask (pi128[0], pi128[1]); + a = mask1 & 3; +} + + +void +sign_foo2 () +{ + __mmask8 mask1 = _mm256_cmpeq_epi64_mask (pi256[0], pi256[1]); + a = mask1 & 15; +} + +void +float_foo () +{ + __mmask8 mask1 = _mm_cmp_ps_mask (ps128[0], ps128[1], 1); + a = mask1 & 15; +} + +void +double_foo () +{ + __mmask8 mask1 = _mm_cmp_pd_mask (pd128[0], pd128[1], 1); + a = mask1 & 3; +} + +void +double_foo2 () +{ + __mmask8 mask1 = _mm256_cmp_pd_mask (pd256[0], pd256[1], 1); + a = mask1 & 15; +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c index 69b200a..a798d06 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpeqq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpeq_epi64_mask (x128, x128); m = _mm256_cmpeq_epi64_mask (x256, x256); - m = _mm_mask_cmpeq_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpeq_epi64_mask (3, x256, x256); + m = _mm_mask_cmpeq_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpeq_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c index c925d32..736763f 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpequq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpeq_epu64_mask (x128, x128); m = _mm256_cmpeq_epu64_mask (x256, x256); - m = _mm_mask_cmpeq_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpeq_epu64_mask (3, x256, x256); + m = _mm_mask_cmpeq_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpeq_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c index ef40e41..19110a5 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpge_epi64_mask (x128, x128); m = _mm256_cmpge_epi64_mask (x256, x256); - m = _mm_mask_cmpge_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpge_epi64_mask (3, x256, x256); + m = _mm_mask_cmpge_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpge_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c index 1f7dd49..d82f8e5 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgeuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpge_epu64_mask (x128, x128); m = _mm256_cmpge_epu64_mask (x256, x256); - m = _mm_mask_cmpge_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpge_epu64_mask (3, x256, x256); + m = _mm_mask_cmpge_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpge_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c index 26cac3a..79f9430 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpgt_epi64_mask (x128, x128); m = _mm256_cmpgt_epi64_mask (x256, x256); - m = _mm_mask_cmpgt_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpgt_epi64_mask (3, x256, x256); + m = _mm_mask_cmpgt_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpgt_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c index 10717cd..bef015f 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpgtuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpgt_epu64_mask (x128, x128); m = _mm256_cmpgt_epu64_mask (x256, x256); - m = _mm_mask_cmpgt_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpgt_epu64_mask (3, x256, x256); + m = _mm_mask_cmpgt_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpgt_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c index 110ff70..9974aa5 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmple_epi64_mask (x128, x128); m = _mm256_cmple_epi64_mask (x256, x256); - m = _mm_mask_cmple_epi64_mask (3, x128, x128); - m = _mm256_mask_cmple_epi64_mask (3, x256, x256); + m = _mm_mask_cmple_epi64_mask (5, x128, x128); + m = _mm256_mask_cmple_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c index e3faf41..0a5a513 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpleuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmple_epu64_mask (x128, x128); m = _mm256_cmple_epu64_mask (x256, x256); - m = _mm_mask_cmple_epu64_mask (3, x128, x128); - m = _mm256_mask_cmple_epu64_mask (3, x256, x256); + m = _mm_mask_cmple_epu64_mask (5, x128, x128); + m = _mm256_mask_cmple_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c index 1b8f7f1..5f40c79 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmplt_epi64_mask (x128, x128); m = _mm256_cmplt_epi64_mask (x256, x256); - m = _mm_mask_cmplt_epi64_mask (3, x128, x128); - m = _mm256_mask_cmplt_epi64_mask (3, x256, x256); + m = _mm_mask_cmplt_epi64_mask (5, x128, x128); + m = _mm256_mask_cmplt_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c index 5c2f025..afda5e7 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpltuq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmplt_epu64_mask (x128, x128); m = _mm256_cmplt_epu64_mask (x256, x256); - m = _mm_mask_cmplt_epu64_mask (3, x128, x128); - m = _mm256_mask_cmplt_epu64_mask (3, x256, x256); + m = _mm_mask_cmplt_epu64_mask (5, x128, x128); + m = _mm256_mask_cmplt_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c index f48de10..5ef2548 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpneqq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpneq_epi64_mask (x128, x128); m = _mm256_cmpneq_epi64_mask (x256, x256); - m = _mm_mask_cmpneq_epi64_mask (3, x128, x128); - m = _mm256_mask_cmpneq_epi64_mask (3, x256, x256); + m = _mm_mask_cmpneq_epi64_mask (5, x128, x128); + m = _mm256_mask_cmpneq_epi64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c index 726a887..4a9aacf 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpcmpnequq-1.c @@ -16,6 +16,6 @@ avx512vl_test (void) { m = _mm_cmpneq_epu64_mask (x128, x128); m = _mm256_cmpneq_epu64_mask (x256, x256); - m = _mm_mask_cmpneq_epu64_mask (3, x128, x128); - m = _mm256_mask_cmpneq_epu64_mask (3, x256, x256); + m = _mm_mask_cmpneq_epu64_mask (5, x128, x128); + m = _mm256_mask_cmpneq_epu64_mask (5, x256, x256); } diff --git a/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c b/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c new file mode 100644 index 0000000..042eb7d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/blendv-to-maxmin.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v3 -O2 -mfpmath=sse" } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ + +double +foo (double a) +{ + if (a > 0.0) + return a; + return 0.0; +} + diff --git a/gcc/testsuite/gcc.target/i386/blendv-to-pand.c b/gcc/testsuite/gcc.target/i386/blendv-to-pand.c new file mode 100644 index 0000000..2896a2b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/blendv-to-pand.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3 -mfpmath=sse" } */ +/* { dg-final { scan-assembler-not "vblendv" } } */ + +void +foo (float* a, float* b, float* c, float* __restrict d, int n) +{ + for (int i = 0; i != n; i++) + { + c[i] *= 2.0f; + if (a[i] > b[i]) + d[i] = 0.0f; + else + d[i] = c[i]; + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr119919.c b/gcc/testsuite/gcc.target/i386/pr119919.c new file mode 100644 index 0000000..ed64656 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119919.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -fdump-tree-vect-details" } */ +int a[9*9]; +bool b[9]; +void test() +{ + for (int i = 0; i < 9; i++) + { + b[i] = a[i*9] != 0; + } +} + +/* { dg-final { scan-tree-dump "loop vectorized using 8 byte vectors" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr89618-2.c b/gcc/testsuite/gcc.target/i386/pr89618-2.c index c414053..11d658f 100644 --- a/gcc/testsuite/gcc.target/i386/pr89618-2.c +++ b/gcc/testsuite/gcc.target/i386/pr89618-2.c @@ -19,5 +19,9 @@ void foo (int n, int *off, double *a) } /* Make sure the cost model selects SSE vectors rather than AVX to avoid - too many scalar ops for the address computes in the loop. */ -/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" { target { ! ia32 } } } } */ + too many scalar ops for the address computes in the loop. + + Since open-coded scatters are costed wrong, we no longer vectorize after fixing + COND_EXPR costs. See PR119902. */ +/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" { target { ! ia32 } xfail *-*-* } } } */ +/* { dg-final { scan-tree-dump-not "loop vectorized using 32 byte vectors" "vect" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c b/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c new file mode 100644 index 0000000..ad9e07b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/recip-vec-divf-fma.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -mfma -mavx2" } */ +/* { dg-final { scan-assembler-times {(?n)vfn?m(add|sub)[1-3]*ps} 2 } } */ + +typedef float v4sf __attribute__((vector_size(16))); +/* (a - (rcp(b) * a * b)) * rcp(b) + rcp(b) * a */ + +v4sf +foo (v4sf a, v4sf b) +{ + return a / b; +} diff --git a/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc/testsuite/gcc.target/mips/clear-cache-1.c index f1554f5..cd11c66 100644 --- a/gcc/testsuite/gcc.target/mips/clear-cache-1.c +++ b/gcc/testsuite/gcc.target/mips/clear-cache-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-msynci isa_rev>=2" } */ /* { dg-final { scan-assembler "\tsynci\t" } } */ -/* { dg-final { scan-assembler "\tjr.hb\t" } } */ +/* { dg-final { scan-assembler "\tjrc?.hb\t" } } */ /* { dg-final { scan-assembler-not "_flush_cache|mips_sync_icache|_cacheflush" } } */ NOMIPS16 void f() diff --git a/gcc/testsuite/gcc.target/mips/memcpy-2.c b/gcc/testsuite/gcc.target/mips/memcpy-2.c new file mode 100644 index 0000000..df0cd18 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/memcpy-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev<=5 -fdump-rtl-expand" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-Os" } { "" } } */ + +__attribute__((nomips16)) +void +f1 (char *p) +{ + __builtin_memcpy (p, "12345", 5); +} + +/* { dg-final { scan-rtl-dump "mem/u.*mem/u" "expand" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c b/gcc/testsuite/gcc.target/powerpc/power11-3.c index fa1aedd..56bf881 100644 --- a/gcc/testsuite/gcc.target/powerpc/power11-3.c +++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-ifunc "" } */ /* Check if we can set the power11 target via a target_clones attribute. */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c b/gcc/testsuite/gcc.target/riscv/arch-25.c index 3be4ade..9201883 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-25.c +++ b/gcc/testsuite/gcc.target/riscv/arch-25.c @@ -2,4 +2,4 @@ /* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ int foo() {} /* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64ic_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-1.c b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c new file mode 100644 index 0000000..5627e16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32i_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-2.c b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c new file mode 100644 index 0000000..4c7d5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-3.c b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c new file mode 100644 index 0000000..7ff68f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-4.c b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c new file mode 100644 index 0000000..ef59b65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-5.c b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c new file mode 100644 index 0000000..14e9551 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf_zcd -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-6.c b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c new file mode 100644 index 0000000..30cda55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-7.c b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c new file mode 100644 index 0000000..b06388b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-8.c b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c new file mode 100644 index 0000000..fa76050 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca_zcd -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c index e477414..fc86dbe 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c index 7008eb5..4504158 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c index 89ebaaf..4ffc051 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c index cacbcaa..7ee8de2 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c new file mode 100644 index 0000000..cb28baf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */ +/* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ +zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c new file mode 100644 index 0000000..1b1ee18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */ +/* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ +zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync) \ + && defined (__riscv__xtheadvdot)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c new file mode 100644 index 0000000..1e27665 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */ +/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c new file mode 100644 index 0000000..6a54f09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */ +/* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_ +zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_ +zbb_zbc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_ +xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei ) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c new file mode 100644 index 0000000..6bcd687 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */ +/* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync) \ + && defined(__riscv_xtheadvector)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c new file mode 100644 index 0000000..36a6267 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */ +/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei ) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zvfbfmin) \ + && defined(__riscv_zvfbfwma) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadsync) \ + && defined(__riscv_xtheadvdot)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-1.c b/gcc/testsuite/gcc.target/s390/pr119873-1.c new file mode 100644 index 0000000..7a9a988 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-1.c @@ -0,0 +1,11 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +const char *foo (void *, void *, void *, void *, unsigned long, unsigned long); + +const char * +bar (void *a, void *b, void *c, void *d, unsigned long e, unsigned long f) +{ + [[gnu::musttail]] return foo (a, b, c, d, e, f); +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-2.c b/gcc/testsuite/gcc.target/s390/pr119873-2.c new file mode 100644 index 0000000..f275253 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-2.c @@ -0,0 +1,17 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +const char *foo (void *, void *, void *, void *, unsigned long, unsigned long); + +const char * +bar (void *a, void *b, void *c, void *d, unsigned long e, unsigned long f) +{ + [[gnu::musttail]] return foo (a, b, c, d, e + 1, f); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} + +const char * +baz (void *a, void *b, void *c, void *d, unsigned long e, unsigned long f) +{ + [[gnu::musttail]] return foo (a, b, c, d, f, e); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-3.c b/gcc/testsuite/gcc.target/s390/pr119873-3.c new file mode 100644 index 0000000..048fcaa --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-3.c @@ -0,0 +1,27 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern int foo (int, int, int, long long, int); + +int +bar (int u, int v, int w, long long x, int y) +{ + [[gnu::musttail]] return foo (u, v, w, x, y); +} + +extern int baz (int, int, int, int, int); + +int +qux (int u, int v, int w, int x, int y) +{ + [[gnu::musttail]] return baz (u, v, w, x, y); +} + +extern int corge (int, int, int, int, unsigned short); + +int +garply (int u, int v, int w, int x, unsigned short y) +{ + [[gnu::musttail]] return corge (u, v, w, x, y); +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-4.c b/gcc/testsuite/gcc.target/s390/pr119873-4.c new file mode 100644 index 0000000..384170c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-4.c @@ -0,0 +1,27 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern int foo (int, int, int, long long, int); + +int +bar (int u, int v, int w, long long x, int y) +{ + [[gnu::musttail]] return foo (u, v, w, x + 1, y - 1); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} + +extern int baz (int, int, int, int, int); + +int +qux (int u, int v, int w, int x, int y) +{ + [[gnu::musttail]] return baz (u, v, w, x, y + 1); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} + +extern int corge (int, int, int, int, unsigned short); + +int +garply (int u, int v, int w, int x, unsigned short y) +{ + [[gnu::musttail]] return corge (u, v, w, x, y + 1); /* { dg-error "cannot tail-call: target is not able to optimize the call into a sibling call" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/pr119873-5.c b/gcc/testsuite/gcc.target/s390/pr119873-5.c new file mode 100644 index 0000000..b5a7950 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-5.c @@ -0,0 +1,11 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -m31 -mzarch" } */ + +extern void foo (int x, int y, int z, long long w, int v); + +void +bar (int x, int y, int z, long long w, int v) +{ + [[gnu::musttail]] return foo (x, y, z, w, v); +} |