diff options
Diffstat (limited to 'gcc/doc/md.texi')
| -rw-r--r-- | gcc/doc/md.texi | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index ae7a601..70a2755 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1366,6 +1366,12 @@ as for @samp{<} apply. A register operand is allowed provided that it is in a general register. +@cindex hard registers in constraint +@item @samp{@{r@}} +An operand is bound to hard register @samp{r} which may be any general, +floating-point, or vector register except a fixed register like a stack pointer +register. The set of fixed registers is target dependent. + @cindex constants in constraints @cindex @samp{i} in constraint @item @samp{i} @@ -2171,12 +2177,6 @@ VFP floating-point registers @code{d0}-@code{d31} and the appropriate subset @code{d0}-@code{d15} based on command line options. Used for 64 bit values only. Not valid for Thumb1. -@item y -The iWMMX co-processor registers. - -@item z -The iWMMX GR registers. - @item G The floating-point constant 0.0 @@ -2210,9 +2210,6 @@ A symbol in the text segment of the current file @item Uv A memory reference suitable for VFP load/store insns (reg+constant offset) -@item Uy -A memory reference suitable for iWMMXt load/store instructions. - @item Uq A memory reference suitable for the ARMv4 ldrsb instruction. @end table @@ -2927,6 +2924,9 @@ A signed 16-bit constant. A memory operand whose address is formed by a base register and offset that is suitable for use in instructions with the same addressing mode as @code{st.w} and @code{ld.w}. +@item q +A general-purpose register except for $r0 and $r1 (for the csrxchg +instruction) @item I A signed 12-bit constant (for arithmetic instructions). @item K @@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15). RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use zfinx. +@item cR +Even-odd RVC general purpose register pair. + @item R Even-odd general purpose register pair. @@ -5000,8 +5003,8 @@ This pattern is not allowed to @code{FAIL}. Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional mask operand (operand 2) that specifies which elements of the destination vectors should be loaded. Other elements of the destination vectors are -taken from operand 3, which is an else operand similar to the one in -@code{maskload}. +taken from operand 3, which is an else operand in the subvector mode +@var{n}, similar to the one in @code{maskload}. The operation is equivalent to: @smallexample @@ -8592,7 +8595,7 @@ If this pattern is not defined, a call to the library function @cindex @code{spaceship@var{m}4} instruction pattern @item @samp{spaceship@var{m}4} -Initialize output operand 0 with mode of integer type to -1, 0, 1 or 2 +Initialize output operand 0 with mode of integer type to -1, 0, 1 or -128 if operand 1 with mode @var{m} compares less than operand 2, equal to operand 2, greater than operand 2 or is unordered with operand 2. Operand 3 should be @code{const0_rtx} if the result is used in comparisons, @@ -8600,7 +8603,7 @@ Operand 3 should be @code{const0_rtx} if the result is used in comparisons, is integral unsigned, @code{constm1_rtx} if the result is used as integer value and the comparison is integral signed and some other @code{CONST_INT} if the result is used as integer value and the comparison is floating point. -In the last case, instead of setting output operand 0 to 2 for unordered, +In the last case, instead of setting output operand 0 to -128 for unordered, set it to operand 3. @var{m} should be a scalar floating point mode. |