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Diffstat (limited to 'gcc/doc/extend.texi')
| -rw-r--r-- | gcc/doc/extend.texi | 542 |
1 files changed, 338 insertions, 204 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 0978c4c..17e6311 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -31,6 +31,7 @@ extensions, accepted by GCC in C90 mode and in C++. * Thread-Local:: Per-thread variables. * OpenMP:: Multiprocessing extensions. * OpenACC:: Extensions for offloading code to accelerator devices. +* _Countof:: The number of elements of arrays. * Inline:: Defining inline functions (as fast as macros). * Volatiles:: What constitutes an access to a volatile object. * Using Assembly Language with C:: Instructions and extensions for interfacing C with assembler. @@ -2886,13 +2887,18 @@ my_memcpy (void *dest, const void *src, size_t len) @cindex @code{nonnull_if_nonzero} function attribute @item nonnull_if_nonzero @itemx nonnull_if_nonzero (@var{arg-index}, @var{arg2-index}) +@itemx nonnull_if_nonzero (@var{arg-index}, @var{arg2-index}, @var{arg3-index}) The @code{nonnull_if_nonzero} attribute is a conditional version of the -@code{nonnull} attribute. It has two arguments, the first argument +@code{nonnull} attribute. It has two or three arguments, the first argument shall be argument index of a pointer argument which must be in some cases non-null and the second argument shall be argument index of an integral argument (other than boolean). If the integral argument is zero, the pointer argument can be null, if it is non-zero, the pointer -argument must not be null. +argument must not be null. If three arguments are provided, the third +argument shall be argument index of another integral argument (other than +boolean) and the pointer argument can be null if either of the integral +arguments are zero and if both are non-zero, the pointer argument must not +be null. @smallexample extern void * @@ -2902,12 +2908,21 @@ extern void * my_memcpy2 (void *dest, const void *src, size_t len) __attribute__((nonnull_if_nonzero (1, 3), nonnull_if_nonzero (2, 3))); +extern size_t +my_fread (void *buf, size_t size, size_t count, FILE *stream) + __attribute__((nonnull (4), + nonnull_if_nonzero (1, 2, 3))); @end smallexample With these declarations, it is invalid to call @code{my_memcpy (NULL, NULL, 0);} or to -call @code{my_memcpy2 (NULL, NULL, 4);} but it is valid -to call @code{my_memcpy2 (NULL, NULL, 0);}. This attribute should be +call @code{my_memcpy2 (NULL, NULL, 4);} or to call +@code{my_fread(@var{buf}, 0, 0, NULL);} or to call +@code{my_fread(NULL, 1, 1, @var{stream});} but it is valid +to call @code{my_memcpy2 (NULL, NULL, 0);} or +@code{my_fread(NULL, 0, 0, @var{stream});} or +@code{my_fread(NULL, 0, 1, @var{stream});} or +@code{my_fread(NULL, 1, 0, @var{stream});}. This attribute should be used on declarations which have e.g.@: an exception for zero sizes, in which case null may be passed. @@ -3878,10 +3893,21 @@ behavior and permissible arguments are the same as for the command-line option @cindex @code{outline-atomics} function attribute, AArch64 @item outline-atomics +@itemx no-outline-atomics Enable or disable calls to out-of-line helpers to implement atomic operations. This corresponds to the behavior of the command-line options @option{-moutline-atomics} and @option{-mno-outline-atomics}. +@cindex @code{max-vectorization} function attribute, AArch64 +@item max-vectorization +@itemx no-max-vectorization +@code{max-vectorization} tells GCC's vectorizer to treat all vector +loops as being more profitable than the original scalar loops when +optimizing the current function. @code{no-max-vectorization} disables +this behavior. +This corresponds to the behavior of the command-line options +@option{-mmax-vectorization} and @option{-mno-max-vectorization}. + @cindex @code{indirect_return} function attribute, AArch64 @item indirect_return The @code{indirect_return} attribute can be applied to a function type @@ -5628,12 +5654,12 @@ You can specify the kind of interrupt to be handled by adding an optional parameter to the interrupt attribute like this: @smallexample -void f (void) __attribute__ ((interrupt ("user"))); +void f (void) __attribute__ ((interrupt ("supervisor"))); @end smallexample -Permissible values for this parameter are @code{user}, @code{supervisor}, -and @code{machine}. If there is no parameter, then it defaults to -@code{machine}. +Permissible values for this parameter are @code{supervisor}, +@code{machine}, and @code{rnmi}. If there is no parameter, then it +defaults to @code{machine}. @cindex @code{riscv_vector_cc} function attribute, RISC-V @item riscv_vector_cc @@ -6112,10 +6138,18 @@ pass arguments, unless it takes a variable number of arguments. @cindex @code{no_callee_saved_registers} function attribute, x86 @item no_callee_saved_registers Use this attribute to indicate that the specified function has no -callee-saved registers. That is, all registers can be used as scratch -registers. For example, this attribute can be used for a function -called from the interrupt handler assembly stub which will preserve -all registers and return from interrupt. +callee-saved registers. That is, all registers, except for stack and +frame pointers, can be used as scratch registers. For example, this +attribute can be used for a function called from the interrupt handler +assembly stub which will preserve all registers and return from +interrupt. + +@cindex @code{preserve_none} function attribute, x86 +@item preserve_none +This attribute is similar to @code{no_callee_saved_registers}, except +on x86-64, r12, r13, r14, r15, rdi and rsi registers are used for +integer parameter passing and this calling convention is subject to +change. @cindex @code{no_caller_saved_registers} function attribute, x86 @item no_caller_saved_registers @@ -6124,9 +6158,10 @@ caller-saved registers. That is, all registers are callee-saved. For example, this attribute can be used for a function called from an interrupt handler. The compiler generates proper function entry and exit sequences to save and restore any modified registers, except for -the EFLAGS register. Since GCC doesn't preserve SSE, MMX nor x87 -states, the GCC option @option{-mgeneral-regs-only} should be used to -compile functions with @code{no_caller_saved_registers} attribute. +the EFLAGS register. Since GCC doesn't preserve YMM nor ZMM registers, +@code{no_caller_saved_registers} attribute can't be used on functions +with AVX enabled. Note that MMX and x87 registers aren't preserved by +@code{no_caller_saved_registers} attribute. @cindex @code{interrupt} function attribute, x86 @item interrupt @@ -6684,23 +6719,10 @@ Enable/disable the generation of the USER_MSR instructions. Enable/disable the generation of the APX features, including EGPR, PUSH2POP2, NDD and PPX. -@cindex @code{target("avx10.1-256")} function attribute, x86 -@item avx10.1-256 -@itemx no-avx10.1-256 -Enable the generation of the AVX10.1 instructions with 256 bit support. -Disable the generation of the AVX10.1 instructions. - @cindex @code{target("avx10.1")} function attribute, x86 @item avx10.1 @itemx no-avx10.1 -Enable the generation of the AVX10.1 instructions with 512 bit support. -Disable the generation of the AVX10.1 instructions. - -@cindex @code{target("avx10.1-512")} function attribute, x86 -@item avx10.1-512 -@itemx no-avx10.1-512 -Enable the generation of the AVX10.1 instructions with 512 bit support. -Disable the generation of the AVX10.1 instructions. +Enable/Disable the generation of the AVX10.1 instructions. @cindex @code{target("avx10.2")} function attribute, x86 @item avx10.2 @@ -6776,6 +6798,11 @@ Enable/disable the generation of RCPSS, RCPPS, RSQRTSS and RSQRTPS instructions followed an additional Newton-Raphson step instead of doing a floating-point division. +@cindex @code{target("80387")} function attribute, x86 +@item 80387 +@itemx no-80387 +Generate code containing 80387 instructions for floating point. + @cindex @code{target("general-regs-only")} function attribute, x86 @item general-regs-only Generate code which uses only the general registers. @@ -7116,9 +7143,11 @@ The @code{aligned} attribute can also be used for functions @cindex @code{counted_by} variable attribute @item counted_by (@var{count}) The @code{counted_by} attribute may be attached to the C99 flexible array -member of a structure. It indicates that the number of the elements of the -array is given by the field "@var{count}" in the same structure as the -flexible array member. +member, or a pointer field of a structure. It indicates that the number +of the elements of the array that is held by the flexible array member +field, or is pointed to by the pointer field, is given by the field +"@var{count}" in the same structure as the flexible array member or the +pointer field. This attribute is available only in C for now. In C++ this attribute is ignored. @@ -7139,8 +7168,22 @@ struct P @{ @end smallexample @noindent -specifies that the @code{array} is a flexible array member whose number of -elements is given by the field @code{count} in the same structure. +specifies that the @code{array} is a flexible array member whose number +of elements is given by the field @code{count} in the same structure. + +@smallexample +struct PP @{ + size_t count2; + char other1; + char *array2 __attribute__ ((counted_by (count2))); + int other2; +@} *pp; +@end smallexample + +@noindent +specifies that the @code{array2} is an array that is pointed by the +pointer field, and its number of elements is given by the field +@code{count2} in the same structure. The field that represents the number of the elements should have an integer type. Otherwise, the compiler reports an error and ignores @@ -7149,6 +7192,12 @@ the attribute. When the field that represents the number of the elements is assigned a negative integer value, the compiler treats the value as zero. +The @code{counted_by} attribute is not allowed for a pointer to @code{void}, +a pointer to function, or a pointer to a structure or union that includes +a flexible array member. However, it is allowed for a pointer to +non-void incomplete structure or union types, as long as the type could +be completed before the first reference to the pointer. + An explicit @code{counted_by} annotation defines a relationship between two objects, @code{p->array} and @code{p->count}, and there are the following requirements on the relationship between this pair: @@ -7164,6 +7213,13 @@ available all the time. This relationship must hold even after any of these related objects are updated during the program. @end itemize +In addition to the above requirements, there is one more requirement +between this pair if and only if @code{p->array} is an array that is +pointed by the pointer field: + +@code{p->array} and @code{p->count} can only be changed by changing the +whole structure at the same time. + It's the programmer's responsibility to make sure the above requirements to be kept all the time. Otherwise the compiler reports warnings and the results of the array bound sanitizer and the @@ -7185,6 +7241,8 @@ In the above, @code{ref1} uses @code{val1} as the number of the elements in @code{p->array}, and @code{ref2} uses @code{val2} as the number of elements in @code{p->array}. +Note, however, the above feature is not valid for the pointer field. + @cindex @code{alloc_size} variable attribute @item alloc_size (@var{position}) @itemx alloc_size (@var{position-1}, @var{position-2}) @@ -7336,7 +7394,7 @@ truncate the copy without appending the terminating @code{NUL} character. Using the attribute makes it possible to suppress the warning. However, when the array is declared with the attribute the call to @code{strlen} is diagnosed because when the array doesn't contain a @code{NUL}-terminated -string the call is undefined. To copy, compare, of search non-string +string the call is undefined. To copy, compare, or search non-string character arrays use the @code{memcpy}, @code{memcmp}, @code{memchr}, and other functions that operate on arrays of bytes. In addition, calling @code{strnlen} and @code{strndup} with such arrays is safe @@ -9188,7 +9246,7 @@ NoError: @item unused This feature is intended for program-generated code that may contain unused labels, but which is compiled with @option{-Wall}. It is -not normally appropriate to use in it human-written code, though it +not normally appropriate to use it in human-written code, though it could be useful in cases where the code that jumps to the label is contained within an @code{#ifdef} conditional. @@ -10393,6 +10451,11 @@ loop or a @code{#pragma GCC ivdep}, and applies only to the loop that follows. @var{n} is an integer constant expression specifying the unrolling factor. The values of @math{0} and @math{1} block any unrolling of the loop. +If the loop was vectorized the unroll factor specified will be used to seed the +vectorizer unroll factor. Whether the loop is unrolled or not will be +determined by target costing. The resulting vectorized loop may still be +unrolled more in later passes depending on the target costing. + @end table @node Thread-Local @@ -10679,7 +10742,7 @@ and @samp{[[omp::sequence(...)]]} in C and C++, GCC needs to be invoked with the @option{-fopenmp} option. This option also arranges for automatic linking of the OpenMP runtime library. -@xref{,,,libgomp,GNU Offloading and Multi Processing Runtime Library}. +@xref{Top,,,libgomp,GNU Offloading and Multi Processing Runtime Library}. @xref{OpenMP and OpenACC Options}, for additional options useful with @option{-fopenmp}. @@ -10701,11 +10764,41 @@ To enable the processing of OpenACC directives @samp{#pragma acc} in C and C++, GCC needs to be invoked with the @option{-fopenacc} option. This option also arranges for automatic linking of the OpenACC runtime library. -@xref{,,,libgomp,GNU Offloading and Multi Processing Runtime Library}. +@xref{Top,,,libgomp,GNU Offloading and Multi Processing Runtime Library}. @xref{OpenMP and OpenACC Options}, for additional options useful with @option{-fopenacc}. +@node _Countof +@section Determining the Number of Elements of Arrays +@cindex _Countof +@cindex number of elements + +The keyword @code{_Countof} determines +the number of elements of an array operand. +Its syntax is similar to @code{sizeof}. +The operand must be +a parenthesized complete array type name +or an expression of such a type. +For example: + +@smallexample +int a[n]; +_Countof (a); // returns n +_Countof (int [7][3]); // returns 7 +@end smallexample + +The result of this operator is an integer constant expression, +unless the array has a variable number of elements. +The operand is only evaluated +if the array has a variable number of elements. +For example: + +@smallexample +_Countof (int [7][n++]); // integer constant expression +_Countof (int [n++][7]); // run-time value; n++ is evaluated +@end smallexample + @node Inline @section An Inline Function is As Fast As a Macro @cindex inline functions @@ -12585,6 +12678,7 @@ The list below describes the supported modifiers and their effects for RISC-V. @item @code{z} @tab Print ''@code{zero}'' instead of 0 if the operand is an immediate with a value of zero. @item @code{i} @tab Print the character ''@code{i}'' if the operand is an immediate. @item @code{N} @tab Print the register encoding as integer (0 - 31). +@item @code{H} @tab Print the name of the next register for integer. @end multitable @anchor{shOperandmodifiers} @@ -12717,6 +12811,7 @@ the two, as explained in the sections below. @menu * Global Register Variables:: Variables declared at global scope. * Local Register Variables:: Variables declared within a function. +* Hard Register Constraints:: Operands forced into specific machine registers. @end menu @node Global Register Variables @@ -12922,6 +13017,167 @@ with slightly different characteristics (@pxref{MIPS Coprocessors,, Defining coprocessor specifics for MIPS targets, gccint, GNU Compiler Collection (GCC) Internals}). +@node Hard Register Constraints +@subsubsection Hard Register Constraints + +Similar to register @code{asm} but still distinct, hard register constraints +are another way to force operands of inline @code{asm} into specific machine +registers. In contrast to register @code{asm} where a variable is bound to a +machine register, a hard register constraint binds an @code{asm} operand to a +machine register. Assume in the following that @code{r4} is a general-purpose +register, @code{f5} a floating-point register, and @code{v6} a vector register +for some target. + +@smallexample +int x; +int y __attribute__ ((vector_size (16))); +@dots{} +asm ("some instructions" + : "=@{r4@}" (x) + : "@{f5@}" (42.0), "@{v6@}" (y)); +@end smallexample + +For the inline @code{asm}, variable @code{x} is bound to register @code{r4}, +and @code{y} is loaded to @code{v6}. Furthermore, constant @code{42.0} is +loaded into floating-point register @code{f5}. + +A key difference between register @code{asm} and hard register constraints is +that the latter are specified at the point where they are supposed to +materialize, namely at inline @code{asm}, which may lead to more readable code. + +@subsubheading Usage + +Each input operand is loaded into the register specified by its corresponding +hard register constraint. Furthermore, each hard register must be used at most +once among an alternative for inputs. This renders hard register constraints +more strict compared to register @code{asm} where multiple inputs may share a +register as for example in + +@smallexample +int x; +register int y asm ("0") = @dots{}; +asm ("" : "=r" (x) : "r" (y), "r" (y)); +@end smallexample + +or even + +@smallexample +register int x asm ("0") = 42; +register int y asm ("0") = 24; +asm ("" : "=r" (x) : "r" (x), "r" (y)); +@end smallexample + +The analogue for hard register constraints is invalid in order to prevent +subtle bugs. + +Likewise, two outputs must not share a register among an alternative. That +means, the following example is invalid + +@smallexample +int x, y; +asm ("" : "=@{r4@}" (x), "=@{r4@}" (y)); // invalid +@end smallexample + +which also aligns with register @code{asm}. Despite that, each output must +refer to a distinct object if a hard register constraint is involved. For +example, in the following, object @code{x} is assigned two registers. + +@smallexample +int x; +asm ("" : "=r" (x), "=r" (x)); +@end smallexample + +This is not allowed for hard register constraints in order to prevent subtle +bugs. Even if only one output operand has a hard register constraint, the code +is rejected since the allocation for the object is still ambiguous. + +@smallexample +int x; +asm ("" : "=r" (x), "=@{1@}" (x)); // invalid +@end smallexample + +The type of an operand must be supported by the corresponding machine register. + +A hard register constraint may refer to any general, floating-point, or vector +register except a fixed register as e.g.@: the stack-pointer register. The set +of allowed registers is target dependent analogue to register @code{asm}. +Furthermore, the referenced register must be a valid register name of the +target. Note, on some targets, a single register may be referred to by +different names where each name specifies the length of the register. For +example, on x86_64 the register names @code{rcx}, @code{ecx}, and @code{cx} all +refer to the same register but in different sizes. If any of those names is +used for a hard register constraint, the actual size of a register is +determined by its corresponding operand. For example + +@smallexample +long x; +asm ("mov\t$42, %0" : "=@{ecx@}" (x)); +@end smallexample + +Although the hard register constraint refers to register @code{ecx}, the actual +register will be @code{rcx} since on x86_64 a @code{long} is 8 byte in total. +This aligns with register @code{asm} where you could have + +@smallexample +register long x asm ("ecx"); +@end smallexample + +@subsubheading Interaction with Register @code{asm} + +A mixture of both constructs as for example + +@smallexample +register int x asm ("r4") = 42; +int y; +asm ("" : "=@{r5@}" (y) : "r" (x)); +@end smallexample + +is valid. + +If an operand is a register @code{asm} and the corresponding constraint a hard +register, then both must refer to the same register. That means + +@smallexample +register int x asm ("r4"); +asm ("" : "=@{r4@}" (x)); +@end smallexample + +is valid and + +@smallexample +register int x asm ("r4"); +asm ("" : "=@{r5@}" (x)); // invalid +@end smallexample + +is invalid. + +Note, register @code{asm} may not only be clobbered by function calls but also +by inline @code{asm} in conjunction with hard register constraints. For +example, in the following + +@smallexample +register int x asm ("r5") = 42; +int y; +asm ("" : "=@{r5@}" (y)); +asm ("" : "+r" (x)); +@end smallexample + +variable @code{x} materializes before the very first inline @code{asm} which +writes to register @code{r5} and therefore clobbers @code{x} which in turn is +read by the subsequent inline @code{asm}. + +@subsubheading Limitations + +At the moment fixed registers are not supported for hard register constraints. +Thus, idioms like + +@smallexample +register void *x asm ("rsp"); +asm ("" : "=r" (x)); +@end smallexample + +are not supported for hard register constraints. This might be lifted. + @node Size of an asm @subsection Size of an @code{asm} @@ -14373,6 +14629,9 @@ a function call results in a compile-time error. @findex acoshf @findex acoshl @findex acosl +@findex acospi +@findex acospif +@findex acospil @findex alloca @findex asin @findex asinf @@ -14380,15 +14639,24 @@ a function call results in a compile-time error. @findex asinhf @findex asinhl @findex asinl +@findex asinpi +@findex asinpif +@findex asinpil @findex atan @findex atan2 @findex atan2f @findex atan2l +@findex atan2pi +@findex atan2pif +@findex atan2pil @findex atanf @findex atanh @findex atanhf @findex atanhl @findex atanl +@findex atanpi +@findex atanpif +@findex atanpil @findex bcmp @findex bzero @findex cabs @@ -14452,6 +14720,9 @@ a function call results in a compile-time error. @findex coshf @findex coshl @findex cosl +@findex cospi +@findex cospif +@findex cospil @findex cpow @findex cpowf @findex cpowl @@ -14687,6 +14958,9 @@ a function call results in a compile-time error. @findex sinhf @findex sinhl @findex sinl +@findex sinpi +@findex sinpif +@findex sinpil @findex snprintf @findex sprintf @findex sqrt @@ -14721,6 +14995,9 @@ a function call results in a compile-time error. @findex tanhf @findex tanhl @findex tanl +@findex tanpi +@findex tanpif +@findex tanpil @findex tgamma @findex tgammaf @findex tgammal @@ -14763,7 +15040,10 @@ a particular case, a call to the library function is emitted. @opindex std Outside strict ISO C mode (@option{-ansi}, @option{-std=c90}, @option{-std=c99} or @option{-std=c11}), the functions -@code{_exit}, @code{alloca}, @code{bcmp}, @code{bzero}, +@code{_exit}, @code{alloca}, @code{acospi}, @code{acospif}, @code{acospil}, +@code{asinpi}, @code{asinpif}, @code{asinpil}, @code{atan2pi}, @code{atan2pif}, +@code{atan2pil}, @code{atanpi}, @code{atanpif}, @code{atanpil}, @code{bcmp}, +@code{bzero}, @code{cospi}, @code{cospif}, @code{cospil}, @code{dcgettext}, @code{dgettext}, @code{dremf}, @code{dreml}, @code{drem}, @code{exp10f}, @code{exp10l}, @code{exp10}, @code{ffsll}, @code{ffsl}, @code{ffs}, @code{fprintf_unlocked}, @@ -14778,11 +15058,12 @@ Outside strict ISO C mode (@option{-ansi}, @option{-std=c90}, @code{signbit}, @code{signbitf}, @code{signbitl}, @code{signbitd32}, @code{signbitd64}, @code{signbitd128}, @code{significandf}, @code{significandl}, @code{significand}, @code{sincosf}, -@code{sincosl}, @code{sincos}, @code{stpcpy}, @code{stpncpy}, -@code{strcasecmp}, @code{strdup}, @code{strfmon}, @code{strncasecmp}, -@code{strndup}, @code{strnlen}, @code{toascii}, @code{y0f}, @code{y0l}, -@code{y0}, @code{y1f}, @code{y1l}, @code{y1}, @code{ynf}, @code{ynl} and -@code{yn} +@code{sincosl}, @code{sincos}, @code{sinpif}, @code{sinpil}, @code{sinpi}, +@code{stpcpy}, @code{stpncpy}, @code{strcasecmp}, @code{strdup}, +@code{strfmon}, @code{strncasecmp}, @code{strndup}, @code{strnlen}, +@code{tanpif}, @code{tanpil}, @code{tanpi}, @code{toascii}, @code{y0f}, +@code{y0l}, @code{y0}, @code{y1f}, @code{y1l}, @code{y1}, @code{ynf}, +@code{ynl} and @code{yn} may be handled as built-in functions. All these functions have corresponding versions prefixed with @code{__builtin_}, which may be used even in strict C90 @@ -15439,7 +15720,7 @@ are 128-bit. Only supported on targets when 128-bit types are supported. Returns the calculated 8-bit bit-reversed CRC using the initial CRC (8-bit), data (8-bit) and the polynomial (8-bit). @var{crc} is the initial CRC, @var{data} is the data and -@var{poly} is the polynomial without leading 1. +@var{poly} is the polynomial without leading 1. @var{poly} is required to be a compile-time constant. Table-based or clmul-based CRC may be used for the calculation, depending on the target architecture. @enddefbuiltin @@ -15494,7 +15775,7 @@ is 32-bit. Returns the calculated 8-bit bit-forward CRC using the initial CRC (8-bit), data (8-bit) and the polynomial (8-bit). @var{crc} is the initial CRC, @var{data} is the data and -@var{poly} is the polynomial without leading 1. +@var{poly} is the polynomial without leading 1. @var{poly} is required to be a compile-time constant. Table-based or clmul-based CRC may be used for the calculation, depending on the target architecture. @enddefbuiltin @@ -16242,8 +16523,9 @@ invoke undefined behavior at run time. Warnings for out of bound accesses for vector subscription can be enabled with @option{-Warray-bounds}. -Vector comparison is supported with standard comparison -operators: @code{==, !=, <, <=, >, >=}. Comparison operands can be +Vector comparison is supported with standard comparison operators: +@code{==}, @code{!=}, @code{<}, @code{<=}, @code{>}, and +@code{>=}. Comparison operands can be vector expressions of integer-type or real-type. Comparison between integer-type vectors and real-type vectors are not supported. The result of the comparison is a vector of the same width and number of @@ -16971,7 +17253,8 @@ is computed. @smallexample struct V @{ char buf1[10]; int b; char buf2[10]; @} var; -char *p = &var.buf1[1], *q = &var.b; +char *p = &var.buf1[1]; +int *q = &var.b; /* Here the object p points to is var. */ assert (__builtin_object_size (p, 0) == sizeof (var) - 1); @@ -17904,7 +18187,6 @@ instructions, but allow the compiler to schedule those calls. * Alpha Built-in Functions:: * ARC Built-in Functions:: * ARC SIMD Built-in Functions:: -* ARM iWMMXt Built-in Functions:: * ARM C Language Extensions (ACLE):: * ARM Floating Point Status and Control Intrinsics:: * ARM ARMv8-M Security Extensions:: @@ -18520,160 +18802,6 @@ _v4hi __builtin_arc_vaddsub4h (__v4hi, __v4hi); _v4hi __builtin_arc_vsubadd4h (__v4hi, __v4hi); @end example -@node ARM iWMMXt Built-in Functions -@subsection ARM iWMMXt Built-in Functions - -These built-in functions are available for the ARM family of -processors when the @option{-mcpu=iwmmxt} switch is used: - -@smallexample -typedef int v2si __attribute__ ((vector_size (8))); -typedef short v4hi __attribute__ ((vector_size (8))); -typedef char v8qi __attribute__ ((vector_size (8))); - -int __builtin_arm_getwcgr0 (void); -void __builtin_arm_setwcgr0 (int); -int __builtin_arm_getwcgr1 (void); -void __builtin_arm_setwcgr1 (int); -int __builtin_arm_getwcgr2 (void); -void __builtin_arm_setwcgr2 (int); -int __builtin_arm_getwcgr3 (void); -void __builtin_arm_setwcgr3 (int); -int __builtin_arm_textrmsb (v8qi, int); -int __builtin_arm_textrmsh (v4hi, int); -int __builtin_arm_textrmsw (v2si, int); -int __builtin_arm_textrmub (v8qi, int); -int __builtin_arm_textrmuh (v4hi, int); -int __builtin_arm_textrmuw (v2si, int); -v8qi __builtin_arm_tinsrb (v8qi, int, int); -v4hi __builtin_arm_tinsrh (v4hi, int, int); -v2si __builtin_arm_tinsrw (v2si, int, int); -long long __builtin_arm_tmia (long long, int, int); -long long __builtin_arm_tmiabb (long long, int, int); -long long __builtin_arm_tmiabt (long long, int, int); -long long __builtin_arm_tmiaph (long long, int, int); -long long __builtin_arm_tmiatb (long long, int, int); -long long __builtin_arm_tmiatt (long long, int, int); -int __builtin_arm_tmovmskb (v8qi); -int __builtin_arm_tmovmskh (v4hi); -int __builtin_arm_tmovmskw (v2si); -long long __builtin_arm_waccb (v8qi); -long long __builtin_arm_wacch (v4hi); -long long __builtin_arm_waccw (v2si); -v8qi __builtin_arm_waddb (v8qi, v8qi); -v8qi __builtin_arm_waddbss (v8qi, v8qi); -v8qi __builtin_arm_waddbus (v8qi, v8qi); -v4hi __builtin_arm_waddh (v4hi, v4hi); -v4hi __builtin_arm_waddhss (v4hi, v4hi); -v4hi __builtin_arm_waddhus (v4hi, v4hi); -v2si __builtin_arm_waddw (v2si, v2si); -v2si __builtin_arm_waddwss (v2si, v2si); -v2si __builtin_arm_waddwus (v2si, v2si); -v8qi __builtin_arm_walign (v8qi, v8qi, int); -long long __builtin_arm_wand(long long, long long); -long long __builtin_arm_wandn (long long, long long); -v8qi __builtin_arm_wavg2b (v8qi, v8qi); -v8qi __builtin_arm_wavg2br (v8qi, v8qi); -v4hi __builtin_arm_wavg2h (v4hi, v4hi); -v4hi __builtin_arm_wavg2hr (v4hi, v4hi); -v8qi __builtin_arm_wcmpeqb (v8qi, v8qi); -v4hi __builtin_arm_wcmpeqh (v4hi, v4hi); -v2si __builtin_arm_wcmpeqw (v2si, v2si); -v8qi __builtin_arm_wcmpgtsb (v8qi, v8qi); -v4hi __builtin_arm_wcmpgtsh (v4hi, v4hi); -v2si __builtin_arm_wcmpgtsw (v2si, v2si); -v8qi __builtin_arm_wcmpgtub (v8qi, v8qi); -v4hi __builtin_arm_wcmpgtuh (v4hi, v4hi); -v2si __builtin_arm_wcmpgtuw (v2si, v2si); -long long __builtin_arm_wmacs (long long, v4hi, v4hi); -long long __builtin_arm_wmacsz (v4hi, v4hi); -long long __builtin_arm_wmacu (long long, v4hi, v4hi); -long long __builtin_arm_wmacuz (v4hi, v4hi); -v4hi __builtin_arm_wmadds (v4hi, v4hi); -v4hi __builtin_arm_wmaddu (v4hi, v4hi); -v8qi __builtin_arm_wmaxsb (v8qi, v8qi); -v4hi __builtin_arm_wmaxsh (v4hi, v4hi); -v2si __builtin_arm_wmaxsw (v2si, v2si); -v8qi __builtin_arm_wmaxub (v8qi, v8qi); -v4hi __builtin_arm_wmaxuh (v4hi, v4hi); -v2si __builtin_arm_wmaxuw (v2si, v2si); -v8qi __builtin_arm_wminsb (v8qi, v8qi); -v4hi __builtin_arm_wminsh (v4hi, v4hi); -v2si __builtin_arm_wminsw (v2si, v2si); -v8qi __builtin_arm_wminub (v8qi, v8qi); -v4hi __builtin_arm_wminuh (v4hi, v4hi); -v2si __builtin_arm_wminuw (v2si, v2si); -v4hi __builtin_arm_wmulsm (v4hi, v4hi); -v4hi __builtin_arm_wmulul (v4hi, v4hi); -v4hi __builtin_arm_wmulum (v4hi, v4hi); -long long __builtin_arm_wor (long long, long long); -v2si __builtin_arm_wpackdss (long long, long long); -v2si __builtin_arm_wpackdus (long long, long long); -v8qi __builtin_arm_wpackhss (v4hi, v4hi); -v8qi __builtin_arm_wpackhus (v4hi, v4hi); -v4hi __builtin_arm_wpackwss (v2si, v2si); -v4hi __builtin_arm_wpackwus (v2si, v2si); -long long __builtin_arm_wrord (long long, long long); -long long __builtin_arm_wrordi (long long, int); -v4hi __builtin_arm_wrorh (v4hi, long long); -v4hi __builtin_arm_wrorhi (v4hi, int); -v2si __builtin_arm_wrorw (v2si, long long); -v2si __builtin_arm_wrorwi (v2si, int); -v2si __builtin_arm_wsadb (v2si, v8qi, v8qi); -v2si __builtin_arm_wsadbz (v8qi, v8qi); -v2si __builtin_arm_wsadh (v2si, v4hi, v4hi); -v2si __builtin_arm_wsadhz (v4hi, v4hi); -v4hi __builtin_arm_wshufh (v4hi, int); -long long __builtin_arm_wslld (long long, long long); -long long __builtin_arm_wslldi (long long, int); -v4hi __builtin_arm_wsllh (v4hi, long long); -v4hi __builtin_arm_wsllhi (v4hi, int); -v2si __builtin_arm_wsllw (v2si, long long); -v2si __builtin_arm_wsllwi (v2si, int); -long long __builtin_arm_wsrad (long long, long long); -long long __builtin_arm_wsradi (long long, int); -v4hi __builtin_arm_wsrah (v4hi, long long); -v4hi __builtin_arm_wsrahi (v4hi, int); -v2si __builtin_arm_wsraw (v2si, long long); -v2si __builtin_arm_wsrawi (v2si, int); -long long __builtin_arm_wsrld (long long, long long); -long long __builtin_arm_wsrldi (long long, int); -v4hi __builtin_arm_wsrlh (v4hi, long long); -v4hi __builtin_arm_wsrlhi (v4hi, int); -v2si __builtin_arm_wsrlw (v2si, long long); -v2si __builtin_arm_wsrlwi (v2si, int); -v8qi __builtin_arm_wsubb (v8qi, v8qi); -v8qi __builtin_arm_wsubbss (v8qi, v8qi); -v8qi __builtin_arm_wsubbus (v8qi, v8qi); -v4hi __builtin_arm_wsubh (v4hi, v4hi); -v4hi __builtin_arm_wsubhss (v4hi, v4hi); -v4hi __builtin_arm_wsubhus (v4hi, v4hi); -v2si __builtin_arm_wsubw (v2si, v2si); -v2si __builtin_arm_wsubwss (v2si, v2si); -v2si __builtin_arm_wsubwus (v2si, v2si); -v4hi __builtin_arm_wunpckehsb (v8qi); -v2si __builtin_arm_wunpckehsh (v4hi); -long long __builtin_arm_wunpckehsw (v2si); -v4hi __builtin_arm_wunpckehub (v8qi); -v2si __builtin_arm_wunpckehuh (v4hi); -long long __builtin_arm_wunpckehuw (v2si); -v4hi __builtin_arm_wunpckelsb (v8qi); -v2si __builtin_arm_wunpckelsh (v4hi); -long long __builtin_arm_wunpckelsw (v2si); -v4hi __builtin_arm_wunpckelub (v8qi); -v2si __builtin_arm_wunpckeluh (v4hi); -long long __builtin_arm_wunpckeluw (v2si); -v8qi __builtin_arm_wunpckihb (v8qi, v8qi); -v4hi __builtin_arm_wunpckihh (v4hi, v4hi); -v2si __builtin_arm_wunpckihw (v2si, v2si); -v8qi __builtin_arm_wunpckilb (v8qi, v8qi); -v4hi __builtin_arm_wunpckilh (v4hi, v4hi); -v2si __builtin_arm_wunpckilw (v2si, v2si); -long long __builtin_arm_wxor (long long, long long); -long long __builtin_arm_wzero (); -@end smallexample - - @node ARM C Language Extensions (ACLE) @subsection ARM C Language Extensions (ACLE) @@ -30725,6 +30853,12 @@ A binary type trait: @code{true} whenever the @var{type1} and @var{type2} refer to the same type. @enddefbuiltin +@defbuiltin{size_t __builtin_structured_binding_size (@var{type})} +This trait returns the structured binding size ([dcl.struct.bind]) +of @var{type}. If a type does not have a structured binding size, +an error is diagnosed unless it is used in SFINAE contexts. +@enddefbuiltin + @node Deprecated Features @section Deprecated Features |